| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * OpenSPARC T2 Processor File: mmi-blaze.h |
| 5 | * Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. |
| 6 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. |
| 7 | * |
| 8 | * The above named program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public |
| 10 | * License version 2 as published by the Free Software Foundation. |
| 11 | * |
| 12 | * The above named program is distributed in the hope that it will be |
| 13 | * useful, but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 15 | * General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public |
| 18 | * License along with this work; if not, write to the Free Software |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. |
| 20 | * |
| 21 | * ========== Copyright Header End ============================================ |
| 22 | */ |
| 23 | #ifndef _mmi_blaze_h_ |
| 24 | #define _mmi_blaze_h_ |
| 25 | |
| 26 | /* mmi-blaze.h |
| 27 | * blaze implementation-dependent parts of the MMI API |
| 28 | */ |
| 29 | |
| 30 | #include <sys/types.h> |
| 31 | |
| 32 | |
| 33 | #include "types.h" |
| 34 | #include "cpu_interface.h" // #include "cpu.h" |
| 35 | #include "mem.h" |
| 36 | #include "system.h" |
| 37 | #include "tracemod.h" |
| 38 | |
| 39 | typedef cpuT cpu_t; |
| 40 | typedef memT mem_t; |
| 41 | typedef uint32_t resettype_t; |
| 42 | typedef uint32_t cpuctlreg_t; |
| 43 | typedef uint32_t trapreg_t; |
| 44 | typedef uint32_t objtype_t; |
| 45 | typedef tracemod_t module_t; |
| 46 | |
| 47 | /* for non-peripheral "devices" that implement ASIs */ |
| 48 | /*typedef int (*fn_asi_action) (void *cbd, uint32_t asi, uint64_t vaddr, uint64_t *buf, int size, cpu_t *cpu); |
| 49 | typedef int (*fn_asi_action_2) (void *cbd, uint32_t asi, uint64_t vaddr, uint64_t *buf, int size, uint32_t cpuid);*/ |
| 50 | |
| 51 | #ifdef __cplusplus |
| 52 | extern "C" { |
| 53 | #endif |
| 54 | #if 0 |
| 55 | } |
| 56 | #endif |
| 57 | |
| 58 | |
| 59 | /*void mmi_register_asi_action(module_t *module, fn_asi_action ld_handler, fn_asi_action st_handler); |
| 60 | void mmi_register_asi_action_2 (module_t *module, uint32_t asi, fn_asi_action_2 ld_handler, fn_asi_action_2 st_handler); */ |
| 61 | |
| 62 | int mmi_register_cb_data (module_t *module, void *cb_data); |
| 63 | void * mmi_get_cb_data (module_t *module); |
| 64 | void * mmi_get_asi_cb_data (module_t *module); |
| 65 | |
| 66 | typedef void (*fn_event_cpu)(void *cb_data, cpu_t *cpu, void *info); |
| 67 | |
| 68 | int mmi_register_cb_instr (module_t *module, fn_event_cpu handler); |
| 69 | int mmi_register_cb_memop (module_t *module, fn_event_cpu handler); |
| 70 | int mmi_register_cb_trap (module_t *module, fn_event_cpu handler); |
| 71 | int mmi_register_cb_trapexit (module_t *module, fn_event_cpu handler); |
| 72 | int mmi_register_cb_tlb (module_t *module, fn_event_cpu handler); |
| 73 | int mmi_register_cb_cpustate (module_t *module, fn_event_cpu handler); |
| 74 | |
| 75 | typedef void (*fn_event_dma)(void *cb_data, void *info); |
| 76 | int mmi_register_cb_dma (module_t *module, fn_event_dma handler); |
| 77 | |
| 78 | /* set this mask using definitions from tracemod.h */ |
| 79 | int mmi_set_cb_mask (module_t *module, uint32_t mask); |
| 80 | |
| 81 | mem_t* mmi_get_memobj (cpu_t *cpu); |
| 82 | // FIXME: actually for SCHIZO we have TWO TLBs (PCI A, B) |
| 83 | int mmi_iommu_va2pa (module_t *module, int is_read, uint64_t va, uint64_t *pa); |
| 84 | int mmi_mmu_va2pa (module_t *module, int is_read, uint64_t va, uint64_t *pa); |
| 85 | int mmi_mmu_va2pa_by_id (uint32_t cpuid, int is_read, uint64_t va, uint64_t *pa); |
| 86 | |
| 87 | |
| 88 | #define mmi_memread8s memread8s |
| 89 | #define mmi_memread8u memread8u |
| 90 | #define mmi_memread16s memread16s |
| 91 | #define mmi_memread16u memread16u |
| 92 | #define mmi_memread32s memread32s |
| 93 | #define mmi_memread32u memread32u |
| 94 | #define mmi_memread64s memread64s |
| 95 | #define mmi_memread64u memread64u |
| 96 | #define mmi_memread_blk memread8u_blk_nl |
| 97 | |
| 98 | #define mmi_memwrite8 memwrite8u_nl |
| 99 | #define mmi_memwrite16 memwrite16u_nl |
| 100 | #define mmi_memwrite32 memwrite32u_nl |
| 101 | #define mmi_memwrite64 memwrite64u_nl |
| 102 | #define mmi_memwrite_blk memwrite8u_blk_nl |
| 103 | #define mmi_mem_casx mem_casx |
| 104 | |
| 105 | // |
| 106 | |
| 107 | int mmi_get_ncpu (); |
| 108 | |
| 109 | |
| 110 | // get the sid of the Vcpu, given the Vcpu pointer |
| 111 | int mmi_get_cpu_sid (cpu_t *cpu); |
| 112 | |
| 113 | // given the sid, get the Vcpu pointer |
| 114 | cpu_t *mmi_get_cpuptr_by_sid (int id) ; |
| 115 | |
| 116 | // ?? int |
| 117 | char *mmi_get_comment_string (void *obj, objtype_t type); |
| 118 | //????????? |
| 119 | int mmi_complete_delayed_load (cpu_t *cpu, uint64_t value); |
| 120 | int mmi_delay_execution (cpu_t *cpu, blaze_cycle_t delay); |
| 121 | |
| 122 | int mmi_stop(); |
| 123 | int mmi_run(); |
| 124 | int mmi_is_stopped(); |
| 125 | int mmi_run_single_threaded(); |
| 126 | |
| 127 | typedef uint32_t vartype_t; |
| 128 | enum { |
| 129 | |
| 130 | VAR_INT = 555, // 32 bit |
| 131 | VAR_LONG_INT, |
| 132 | VAR_STRING, |
| 133 | VAR_BOOL |
| 134 | }; |
| 135 | |
| 136 | typedef void (*fn_setvar)(void *cb_data, void *value); |
| 137 | |
| 138 | int mmi_register_ui_variable (module_t *module, const char *varname, |
| 139 | vartype_t vartype, void *varptr, int writable, fn_setvar writer); |
| 140 | |
| 141 | int mmi_set_ui_variable (module_t *module, const char *varname, void *varptr); |
| 142 | |
| 143 | #if 0 |
| 144 | { |
| 145 | #endif |
| 146 | #ifdef __cplusplus |
| 147 | } // extern "C" |
| 148 | #endif |
| 149 | |
| 150 | |
| 151 | #endif // _mmi_blaze_h_ |