* ========== Copyright Header Begin ==========================================
* OpenSPARC T2 Processor File: N2_NcuCsr.h
* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
* The above named program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public
* License version 2 as published by the Free Software Foundation.
* The above named program is distributed in the hope that it will be
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
* You should have received a copy of the GNU General Public
* License along with this work; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
* ========== Copyright Header End ============================================
/************************************************************************
** Copyright (C) 2005, Sun Microsystems, Inc.
** Sun considers its source code as an unpublished, proprietary
** trade secret and it is available only under strict license provisions.
** This copyright notice is placed here only to protect Sun in the event
** the source is deemed a published work. Disassembly, decompilation,
** or other means of reducing the object code to human readable form
** is prohibited by the license agreement under which this code is
** provided to the user or company in possession of this copy."
*************************************************************************/
class N2_NcuCsr
: public SS_BaseCsr
static const int NUMBER_ENTRIES
;
static RegisterAttribute attributeTable
[];
static const uint64_t NCU_ASI_COREAVAIL
= 0x9001040000;
static const uint64_t NCU_ASI_CORE_ENABLE_STATUS
= 0x9001040010;
static const uint64_t NCU_ASI_CORE_ENABLE
= 0x9001040020;
static const uint64_t NCU_ASI_XIR_STEERING
= 0x9001040030;
static const uint64_t NCU_ASI_CORE_RUNNINGRW
= 0x9001040050;
static const uint64_t NCU_ASI_CORE_RUNNING_STATUS
= 0x9001040058;
static const uint64_t NCU_ASI_CORE_RUNNING_W1S
= 0x9001040060;
static const uint64_t NCU_ASI_CORE_RUNNING_W1C
= 0x9001040068;
static const uint64_t NCU_ASI_INTVECDISP
= 0x9001cc0000;
static const uint64_t NCU_ASI_TICK_ENABLE
= 0x9001040038;
static const uint64_t NCU_ASI_OVERLAP_MODE
= 0x9001140010;
static const uint64_t NCU_ASI_WMR_VEC_MASK
= 0x9001140018;
int read64( SS_Paddr addr
,
int access
=MemoryTransaction::READ
,
int write64( SS_Paddr addr
,
int access
=MemoryTransaction::WRITE
,
uint64_t io2asiRead(SS_Paddr paddr
);
void io2asiWrite(SS_Paddr paddr
, uint64_t value
);
void warmReset() { SS_BaseCsr::warmReset(values_
, NUMBER_ENTRIES
); }