projects / unix-history / blame
| Commit | Line | Data |
|---|---|---|
| 430f81c3 MK |
1 | /* |
| 2 | * @(#)if_acereg.h 7.1 (Berkeley) %G% | |
| 3 | */ | |
| 27900e4b SL |
4 | |
| 5 | /* | |
| 6 | * VERSAbus ACC ethernet controller definitions | |
| 7 | */ | |
| 8 | ||
| 9 | /* | |
| 10 | * Register definitions | |
| 11 | */ | |
| 12 | struct acedevice { | |
| 13 | short station[6]; /* station address */ | |
| 14 | short bcastena[2]; /* broadcast enable */ | |
| 15 | short hash[8]; /* multicast hash codes */ | |
| 16 | short csr; /* control and status register */ | |
| 17 | short tseg; /* current transmit segment # */ | |
| 18 | short rseg; /* current receive segment # */ | |
| 19 | short segb; /* segment boundary register */ | |
| 20 | short lrf; /* lost receive frame counter */ | |
| 21 | short ivct; /* interrupt vector register */ | |
| 22 | short resv; /* reserved for future use */ | |
| 23 | short fcoll; /* force collision register */ | |
| 24 | }; | |
| 25 | ||
| 26 | /* | |
| 27 | * Transmit segment in dual ported ram. | |
| 28 | */ | |
| 29 | struct tx_segment { | |
| 30 | short tx_csr; /* packet status */ | |
| 31 | char tx_data[2014]; | |
| 32 | short tx_backoff[16]; /* random backoff counters */ | |
| 33 | }; | |
| 34 | ||
| 35 | /* | |
| 36 | * Receive segment in dual ported ram. | |
| 37 | */ | |
| 38 | struct rx_segment { | |
| 39 | short rx_csr; /* packet status */ | |
| 40 | char rx_data[2046]; | |
| 41 | }; | |
| 42 | ||
| 43 | /* | |
| 44 | * ACC statistics block. | |
| 45 | */ | |
| 46 | struct ace_stats { | |
| 47 | int rx_datagrams; /* valid packets received */ | |
| 48 | int rx_crc_errors; /* CRC errors */ | |
| 49 | int rx_overruns; /* packets too large */ | |
| 50 | int rx_underruns; /* packets too small */ | |
| 51 | int rx_align_errors; /* packets w/ odd byte count */ | |
| 52 | int rx_reserved; | |
| 53 | int rx_busy; /* recv segment filled */ | |
| 54 | int rx_mbuf; /* out of mbufs */ | |
| 55 | int rx_oddoff; /* odd offset in mbuf */ | |
| 56 | int rx_rintcnt; /* recvr interrupt */ | |
| 57 | ||
| 58 | int tx_datagrams; /* packets xmit'd */ | |
| 59 | int tx_retries; /* collision retries */ | |
| 60 | int tx_discarded; /* packets w/ max retries */ | |
| 61 | int tx_busy; /* xmit segment filled in acestart */ | |
| 62 | int tx_cbusy; /* xmit segment filled in acecint */ | |
| 63 | int tx_mbuf; /* total mbufs */ | |
| 64 | int tx_oddoff; /* odd offset in mbuf */ | |
| 65 | int tx_outcnt; /* calls to aceoutput */ | |
| 66 | int tx_startcnt; /* calls to acestart */ | |
| 67 | int tx_cintcnt; /* xmit's completed */ | |
| 68 | }; | |
| 69 | ||
| 70 | /* | |
| 71 | * Control status definitions. | |
| 72 | */ | |
| 73 | #define CSR_OBCENA 0x0200 /* enable xmit of odd byte count */ | |
| 74 | #define CSR_ACTIVE 0x0080 /* board active */ | |
| 75 | #define CSR_RESET 0x0040 /* reset board */ | |
| 76 | #define CSR_PROMISC 0x0020 /* enable promiscous mode */ | |
| 77 | #define CSR_CRCDIS 0x0010 /* disable CRC generation */ | |
| 78 | #define CSR_LOOP3 0x0008 /* enable loopback mode 3 */ | |
| 79 | #define CSR_LOOP2 0x0004 /* enable loopback mode 2 */ | |
| 80 | #define CSR_IENA 0x0002 /* interrupt enable */ | |
| 81 | #define CSR_GO 0x0001 /* enable micro-engine */ | |
| 82 | ||
| 83 | #define ACE_CSRBITS \ | |
| 84 | "\20\12OBCENA\10ACTIVE\7RESET\6PROMISC\5CRCDIS\4LOOP3\3LOOP2\2IENA\1GO" | |
| 85 | /* | |
| 86 | * Transmit packet status definitions. | |
| 87 | */ | |
| 88 | #define TCS_TBFULL (short)0x8000 /* buffer filled, send it */ | |
| 89 | #define TCS_TBC (short)0x07FF /* byte count */ | |
| 90 | #define TCS_TBMT (short)0x8000 /* buffer empty */ | |
| 91 | #define TCS_RTFAIL (short)0x4000 /* retries failed */ | |
| 92 | #define TCS_RTC (short)0x000F /* collision retry mask */ | |
| 93 | ||
| 94 | /* | |
| 95 | * Receive packet status definitions. | |
| 96 | */ | |
| 97 | #define RCS_RBMT 0x8000 /* buffer ready for recv */ | |
| 98 | #define RCS_RBFULL 0x8000 /* buffer full, take data */ | |
| 99 | #define RCS_ROVRN 0x4000 /* overrun error */ | |
| 100 | #define RCS_RCRC 0x2000 /* CRC error */ | |
| 101 | #define RCS_RODD 0x1000 /* odd byte count error */ | |
| 102 | #define RCS_RBC 0x07FF /* byte count mask */ | |
| 103 | ||
| 104 | #define ACE_RCSBITS "\20\20RBFULL\17ROVRN\16RCSR\15RODD" | |
| 105 | ||
| 106 | #define CRC_SIZE 4 /* number of bytes in a rx seg's CRC */ | |
| 107 | #define RCW_SIZE 2 /* number of bytes in a rx seg's csr */ | |
| 108 | #define SEG_MAX 15 /* largest valid segment number */ | |
| 109 | #define ET_MINLEN 64 /* min frame size */ | |
| 110 | #define ET_MAXLEN 1514 /* max frame size w/o CRC & RCW */ |