projects / unix-history / blame
| Commit | Line | Data |
|---|---|---|
| e80bb6f4 | 1 | /* if_ilreg.h 4.2 82/06/23 */ |
| ac5a9f24 BF |
2 | |
| 3 | /* | |
| 4 | * Interlan Ethernet Communications Controller interface | |
| 5 | */ | |
| 6 | struct ildevice { | |
| 7 | short il_csr; /* Command and Status Register */ | |
| 8 | short il_bar; /* Buffer Address Register */ | |
| 9 | short il_bcr; /* Byte Count Register */ | |
| 10 | }; | |
| 11 | ||
| 12 | /* | |
| 13 | * Command and status bits | |
| 14 | */ | |
| e80bb6f4 | 15 | #define IL_EUA 0xc000 /* Extended Unibus Address */ |
| ac5a9f24 BF |
16 | #define IL_CMD 0x3f00 /* Command Function Code */ |
| 17 | #define IL_CDONE 0x0080 /* Command Done */ | |
| 18 | #define IL_CIE 0x0040 /* Command Interrupt Enable */ | |
| 19 | #define IL_RDONE 0x0020 /* Receive DMA Done */ | |
| 20 | #define IL_RIE 0x0010 /* Receive Interrupt Enable */ | |
| 21 | #define IL_STATUS 0x000f /* Command Status Code */ | |
| 22 | ||
| e80bb6f4 | 23 | #define IL_BITS "\20\10CDONE\7CIE\6RDONE\5RIE" |
| ac5a9f24 | 24 | |
| e80bb6f4 | 25 | /* command definitions */ |
| ac5a9f24 BF |
26 | #define ILC_MLPBAK 0x0100 /* Set Module Interface Loopback Mode */ |
| 27 | #define ILC_ILPBAK 0x0200 /* Set Internal Loopback Mode */ | |
| 28 | #define ILC_CLPBAK 0x0300 /* Clear Loopback Mode */ | |
| 29 | #define ILC_PRMSC 0x0400 /* Set Promiscuous Receive Mode */ | |
| 30 | #define ILC_CLPRMSC 0x0500 /* Clear Promiscuous Receive Mode */ | |
| 31 | #define ILC_RCVERR 0x0600 /* Set Receive-On-Error Bit */ | |
| 32 | #define ILC_CRCVERR 0x0700 /* Clear Receive-On-Error Bit */ | |
| 33 | #define ILC_OFFLINE 0x0800 /* Go Offline */ | |
| 34 | #define ILC_ONLINE 0x0900 /* Go Online */ | |
| 35 | #define ILC_DIAG 0x0a00 /* Run On-board Diagnostics */ | |
| 36 | #define ILC_STAT 0x1800 /* Report and Reset Statistics */ | |
| 37 | #define ILC_DELAYS 0x1900 /* Report Collision Delay Times */ | |
| 38 | #define ILC_RCV 0x2000 /* Supply Receive Buffer */ | |
| 39 | #define ILC_LDXMIT 0x2800 /* Load Transmit Data */ | |
| 40 | #define ILC_XMIT 0x2900 /* Load Transmit Data and Send */ | |
| 41 | #define ILC_LDGRPS 0x2a00 /* Load Group Addresses */ | |
| 42 | #define ILC_RMGRPS 0x2b00 /* Delete Group Addresses */ | |
| 43 | #define ILC_FLUSH 0x3000 /* Flush Receive BAR/BCR Queue */ | |
| 44 | #define ILC_RESET 0x3f00 /* Reset */ | |
| 45 | ||
| 46 | /* | |
| e80bb6f4 | 47 | * Error codes found in the status bits of the csr. |
| ac5a9f24 | 48 | */ |
| e80bb6f4 SL |
49 | #define ILERR_SUCCESS 0 /* command successful */ |
| 50 | #define ILERR_RETRIES 1 /* " " with retries */ | |
| 51 | #define ILERR_BADCMD 2 /* illegal command */ | |
| 52 | #define ILERR_INVCMD 3 /* invalid command */ | |
| 53 | #define ILERR_RECVERR 4 /* receiver error */ | |
| 54 | #define ILERR_BUFSIZ 5 /* buffer size too big */ | |
| 55 | #define ILERR_FRAMESIZ 6 /* frame size too small */ | |
| 56 | #define ILERR_COLLISIONS 8 /* excessive collisions */ | |
| 57 | #define ILERR_BUFALIGNMENT 10 /* buffer not word aligned */ | |
| 58 | #define ILERR_NXM 15 /* non-existent memory */ | |
| 59 | ||
| 60 | #define NILERRS 16 | |
| 61 | #ifdef ILERRS | |
| 62 | char *ilerrs[NILERRS] = { | |
| 63 | "success", /* 0 */ | |
| 64 | "success with retries", /* 1 */ | |
| 65 | "illegal command", /* 2 */ | |
| 66 | "inappropriate command", /* 3 */ | |
| 67 | "failure", /* 4 */ | |
| 68 | "buffer size exceeded", /* 5 */ | |
| 69 | "frame too small", /* 6 */ | |
| 70 | 0, /* 7 */ | |
| 71 | "excessive collisions", /* 8 */ | |
| 72 | 0, /* 9 */ | |
| 73 | "buffer alignment error", /* 10 */ | |
| 74 | 0, /* 11 */ | |
| 75 | 0, /* 12 */ | |
| 76 | 0, /* 13 */ | |
| 77 | 0, /* 14 */ | |
| 78 | "non-existent memory" /* 15 */ | |
| ac5a9f24 | 79 | }; |
| e80bb6f4 SL |
80 | #endif |
| 81 | ||
| 82 | /* | |
| 83 | * Diagnostics codes. | |
| 84 | */ | |
| 85 | #define ILDIAG_SUCCESS 0 /* no problems */ | |
| 86 | #define ILDIAG_CHKSUMERR 1 /* ROM/RAM checksum error */ | |
| 87 | #define ILDIAG_DMAERR 2 /* DMA not working */ | |
| 88 | #define ILDIAG_XMITERR 3 /* xmit circuitry failure */ | |
| 89 | #define ILDIAG_RECVERR 4 /* rcvr circuitry failure */ | |
| 90 | #define ILDIAG_LOOPBACK 5 /* loopback test failed */ | |
| ac5a9f24 | 91 | |
| e80bb6f4 SL |
92 | #define NILDIAGS 6 |
| 93 | #ifdef ILDIAGS | |
| 94 | char *ildiag[NILDIAGS] = { | |
| 95 | "success", /* 0 */ | |
| 96 | "checksum error", /* 1 */ | |
| 97 | "NM10 dma error", /* 2 */ | |
| 98 | "transmitter error", /* 3 */ | |
| 99 | "receiver error", /* 4 */ | |
| 100 | "loopback failure", /* 5 */ | |
| ac5a9f24 | 101 | }; |
| e80bb6f4 SL |
102 | #endif |
| 103 | ||
| 104 | /* | |
| 105 | * Frame status bits, returned in frame status byte | |
| 106 | * at the top of each received packet. | |
| 107 | */ | |
| 108 | #define ILFSTAT_C 0x1 /* CRC error */ | |
| 109 | #define ILFSTAT_A 0x2 /* alignment error */ | |
| 110 | #define ILFSTAT_L 0x4 /* 1+ frames lost just before */ |