generalize uba code to handle Q bus more gracefully
[unix-history] / usr / src / sys / vax / uba / rlreg.h
CommitLineData
da7c5cc6 1/*
0880b18e 2 * Copyright (c) 1982, 1986 Regents of the University of California.
da7c5cc6
KM
3 * All rights reserved. The Berkeley software License Agreement
4 * specifies the terms and conditions for redistribution.
5 *
0880b18e 6 * @(#)rlreg.h 7.1 (Berkeley) %G%
da7c5cc6 7 */
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8
9struct rldevice {
10 short rlcs; /* control status */
11 u_short rlba; /* bus address */
12 union { /* disk address */
13 u_short seek; /* disk seek address */
14 u_short rw; /* disk read/write address */
15 u_short getstat; /* get disk status command */
16 } rlda;
17 union { /* multi-purpose register */
18 u_short getstat; /* get status */
19 u_short readhdr; /* read header */
20 u_short rw; /* read/write word count */
21 } rlmp;
22};
23
24#define NRLCYLN 512 /* number of cylinders per disk */
25#define NRLTRKS 2 /* number of tracks per cylinder */
26#define NRLSECT 40 /* number of sectors per track */
27#define NRLBPSC 256 /* bytes per sector */
28
29/* rlcs */
30/* commands */
31#define RL_NOOP 0000000 /* no-operation */
32#define RL_WCHECK 0000002 /* write check */
33#define RL_GETSTAT 0000004 /* get status */
34#define RL_SEEK 0000006 /* seek */
35#define RL_RHDR 0000010 /* read header */
36#define RL_WRITE 0000012 /* write data */
37#define RL_READ 0000014 /* read data */
38#define RL_RDNCK 0000016 /* read data without hdr check */
39
40#define RL_DRDY 0000001 /* When set indicates drive ready */
41#define RL_BAE 0000060 /* UNIBUS address bits 16 & 17 */
42#define RL_IE 0000100 /* interrupt enable */
43#define RL_CRDY 0000200 /* controller ready */
44#define RL_DS0 0000400 /* drive select 0 */
45#define RL_DS1 0001000 /* drive select 1 */
46#define RL_OPI 0002000 /* operation incomplete */
47#define RL_DCRC 0004000 /* CRC error occurred */
48#define RL_DLT 0010000 /* data late or header not found */
49#define RL_NXM 0020000 /* non-existant memory */
50#define RL_DE 0040000 /* selected drive flagged an error */
51#define RL_ERR 0100000 /* composite error */
52
53#define RL_DCRDY (RL_DRDY | RL_CRDY)
54
55#define RLCS_BITS \
56"\10\20ERR\17DE\16NXM\15DLT\14DCRC\13OPI\1DRDY"
57
58/* da_seek */
59#define RLDA_LOW 0000001 /* lower cylinder seek */
60#define RLDA_HGH 0000005 /* higher cylinder seek */
61#define RLDA_HSU 0000000 /* upper head select */
62#define RLDA_HSL 0000020 /* lower head select */
63#define RLDA_CA 0177600 /* cylinder address */
64
65/* da_rw */
66#define RLDA_SA 0000077 /* sector address */
67#define RLDA_HST 0000000 /* upper head select */
68#define RLDA_HSB 0000100 /* lower head select */
69
70/* da_getstat */
71
72#define RL_GSTAT 0000003 /* Get status */
73#define RL_RESET 0000013 /* get status with reset */
74
75/* mp_getstat */
76#define RLMP_STA 0000001 /* drive state: load cartridge */
77#define RLMP_STB 0000002 /* drive state: brush cycle */
78#define RLMP_STC 0000004 /* drive state: seek */
79#define RLMP_BH 0000010 /* set when brushes are home */
80#define RLMP_HO 0000020 /* set when brushes over the disk */
81#define RLMP_CO 0000040 /* set when cover open */
82#define RLMP_HS 0000100 /* indicates selected head:
83 0 upper head
84 1 lower head */
85#define RLMP_DT 0000200 /* indicates drive type:
86 0 RL01
87 1 RL02 */
88#define RLMP_DSE 0000400 /* set on multiple drive selection */
89#define RLMP_VC 0001000 /* set on pack mounted and spining */
90#define RLMP_WGE 0002000 /* write gate error */
91#define RLMP_SPE 0004000 /* spin speed error */
92#define RLMP_SKTO 0010000 /*\\b* seek time out error */
93#define RLMP_WL 0020000 /* set on protected drive */
94#define RLMP_CHE 0040000 /* current head error */
95#define RLMP_WDE 0100000 /* write data error */
96
97/* mp_rhc */
98#define RLMP_SA 0000077 /* sector address */
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99#define RLMP_CA 0177600 /* cylinder address */
100
101/* check these bits after a get status and reset */
102#define RLMP_STATUS (RLMP_WDE|RLMP_CHE|RLMP_SKTO|RLMP_SPE|RLMP_WGE \
103 |RLMP_VC|RLMP_DSE|RLMP_CO|RLMP_HO|RLMP_BH|RLMP_STC|RLMP_STB|RLMP_STA)
104
105/* these are the bits that should be on in the above check */
106#define RLMP_STATOK (RLMP_HO|RLMP_BH|RLMP_STC|RLMP_STA)
107
108/* mp_rw */
109#define RLMP_WC 0017777 /* word count 2's complement */
110
111#define RLER_BITS \
112"\10\20WDE\17CHE\16WL\15SKTO\14SPE\13WGE\12VC\11DSE\
113\10DT\7HS\6CO\5HO\4BH\3STC\2STB\1STA"