[unix-history] / usr / src / sys / vax / uba / dmfreg.h

/*
 * Copyright (c) 1982, 1986 Regents of the University of California.
 * All rights reserved.  The Berkeley software License Agreement
 * specifies the terms and conditions for redistribution.
 *
 *	@(#)dmfreg.h	7.1 (Berkeley) %G%
 */

/*
 * DMF-32 definitions.
 */

/*
 * "dmf" (unqualified) refers to the async portion of the dmf32,
 * "dmfc" to the combo portion,
 * "dmfs" to the sync portion,
 * "dmfl" to the lp portion, and
 * "dmfd" to the dr portion.
 */
struct dmfdevice {
	short	dmfccsr0;		/* combo csr 0 */
	short	dmfccsr1;		/* combo csr 1 */
	short	dmfs[4];
	short	dmfcsr;			/* control-status register */
	short	dmflpr;			/* line parameter register */
	short	dmfrbuf;		/* receiver buffer (ro) */
	union {
		u_short	dmfirw;		/* indirect register word */
		u_char	dmfirc[2];	/*    "         "    bytes */
	} dmfun;
	short	dmfl_ctrl;	/* line printer control register */
	short	dmfl_indrct;	/* line printer indirect register */
	short	dmfd[4];	/* for dr11 (not implemented) */
};

#define	dmfrsp	dmfrbuf		/* receive silo parameter register (wo) */
#define	dmftbuf	dmfun.dmfirc[0]	/* transmit buffer */
#define	dmftsc	dmfun.dmfirc[0]	/* transmit silo count */
#define	dmfrms	dmfun.dmfirc[1]	/* receive modem status */
#define	dmflctms dmfun.dmfirw	/* line control, transmit modem status */
#define	dmftba	dmfun.dmfirw	/* transmit buffer address */
#define	dmftcc	dmfun.dmfirw	/* transmit character count */

/* bits in dmfcsr */
#define	DMF_TI	0100000		/* transmit interrupt */
#define	DMF_TIE	0040000		/* transmit interrupt enable */
#define	DMF_NXM	0020000		/* non-existant memory */
#define	DMF_LIN	0003400		/* transmit line number */
#define	DMF_RI	0000200		/* receiver interrupt */
#define	DMF_RIE	0000100		/* receiver interrupt enable */
#define	DMF_CLR	0000040		/* master reset */
#define	DMF_IAD	0000037		/* indirect address register */

#define	DMFIR_TBUF	000	/* select tbuf indirect register */
#define	DMFIR_LCR	010	/* select lcr indirect register */
#define	DMFIR_TBA	020	/* select tba indirect register */
#define	DMFIR_TCC	030	/* select tcc indirect register */

/* bits in dmflpr */
#define	BITS6	(01<<3)
#define	BITS7	(02<<3)
#define	BITS8	(03<<3)
#define	TWOSB	0200
#define	PENABLE	040
#define	EPAR	0100

#define	DMF_IE	(DMF_TIE|DMF_RIE)

#define	DMF_SILOCNT	32		/* size of DMF output silo (per line) */

/* bits in dmfrbuf */
#define	DMF_DSC		0004000		/* data set change */
#define	DMF_PE		0010000		/* parity error */
#define	DMF_FE		0020000		/* framing error */
#define	DMF_DO		0040000		/* data overrun */

/* bits in dmfrms */
#define	DMF_USRR	0004		/* user modem signal (pin 25) */
#define	DMF_SR		0010		/* secondary receive */
#define	DMF_CTS		0020		/* clear to send */
#define	DMF_CAR		0040		/* carrier detect */
#define	DMF_RNG		0100		/* ring */
#define	DMF_DSR		0200		/* data set ready */

/* bits in dmftms */
#define	DMF_USRW	0001		/* user modem signal (pin 18) */
#define	DMF_DTR		0002		/* data terminal ready */
#define	DMF_RATE	0004		/* data signal rate select */
#define	DMF_ST		0010		/* secondary transmit */
#define	DMF_RTS		0020		/* request to send */
#define	DMF_BRK		0040		/* pseudo break bit */
#define	DMF_PREEMPT	0200		/* preempt output */

/* flags for modem control */
#define	DMF_ON	(DMF_DTR|DMF_RTS)
#define	DMF_OFF	0

/* bits in dmflctms */
#define	DMF_MIE		0040		/* modem interrupt enable */
#define	DMF_FLUSH	0020		/* flush transmit silo */
#define	DMF_RBRK	0010		/* real break bit */
#define	DMF_RE		0004		/* receive enable */
#define	DMF_AUTOX	0002		/* auto XON/XOFF */
#define	DMF_TE		0001		/* transmit enable */

#define	DMFLCR_ENA	(DMF_MIE|DMF_RE|DMF_TE)

/* bits in dm lsr, copied from dh.c */
#define	DML_USR		0001000		/* usr modem sig, not a real DM bit */
#define	DML_DSR		0000400		/* data set ready, not a real DM bit */
#define	DML_RNG		0000200		/* ring */
#define	DML_CAR		0000100		/* carrier detect */
#define	DML_CTS		0000040		/* clear to send */
#define	DML_SR		0000020		/* secondary receive */
#define	DML_ST		0000010		/* secondary transmit */
#define	DML_RTS		0000004		/* request to send */
#define	DML_DTR		0000002		/* data terminal ready */
#define	DML_LE		0000001		/* line enable */

/* dmf line printer csr def */
#define DMFL_PEN	(1<<0)		/* print enable */
#define DMFL_RESET	(1<<1)		/* master reset */
#define DMFL_FORMAT	(1<<2)		/* format control */
#define DMFL_UNUSED	(3<<3)
#define DMFL_MAINT	(1<<5)		/* maintenance mode on */
#define DMFL_IE		(1<<6)		/* intr enable */
#define DMFL_PDONE	(1<<7)		/* print done bit */
#define DMFL_INDIR	(7<<8)		/* indirect reg */
#define DMFL_UNUSED2	(1<<11)
#define DMFL_CONV	(1<<12)		/* connect verify */
#define	DMFL_DAVRDY	(1<<13)		/* davfu ready */
#define DMFL_OFFLINE	(1<<14)		/* printer offline */
#define DMFL_DMAERR	(1<<15)		/* dma error bit */
#define DMFL_BUFSIZ	512		/* max chars per dma */
#define DMFL_DEFCOLS	132		/* default # of cols/line <=255 */
#define DMFL_DEFLINES	66		/* default # of lines/page <=255 */
#define DMFL_OPTIONS	((1 << 8) | (1 << 9) | (1 << 15))
					/* auto cr, real ff, no lower to upper */

/*
 *  Bits in the configuration register
 */
#define DMFC_CONFMASK	0xf000		/* picks off the configuration bits */
#define	DMFC_DR		0x1000		/* DR11 parallel interface */
#define DMFC_LP		0x2000		/* LP dma parallel lineprinter i'face */
#define DMFC_SYNC	0x4000		/* Synchronous serial interface */
#define DMFC_ASYNC	0x8000		/* 8 Serial ports */
Commit	Line	Data
da7c5cc6	1	/*
0880b18e	2	* Copyright (c) 1982, 1986 Regents of the University of California.
da7c5cc6 KM	3	* All rights reserved. The Berkeley software License Agreement
	4	* specifies the terms and conditions for redistribution.
	5	*
0880b18e	6	* @(#)dmfreg.h 7.1 (Berkeley) %G%
da7c5cc6	7	*/
7e1a3cad SL	8
	9	/*
	10	* DMF-32 definitions.
	11	*/
	12
	13	/*
	14	* "dmf" (unqualified) refers to the async portion of the dmf32,
	15	* "dmfc" to the combo portion,
	16	* "dmfs" to the sync portion,
	17	* "dmfl" to the lp portion, and
	18	* "dmfd" to the dr portion.
	19	*/
	20	struct dmfdevice {
	21	short dmfccsr0; /* combo csr 0 */
	22	short dmfccsr1; /* combo csr 1 */
	23	short dmfs[4];
	24	short dmfcsr; /* control-status register */
	25	short dmflpr; /* line parameter register */
	26	short dmfrbuf; /* receiver buffer (ro) */
	27	union {
	28	u_short dmfirw; /* indirect register word */
	29	u_char dmfirc[2]; /* " " bytes */
	30	} dmfun;
26505102 MK	31	short dmfl_ctrl; /* line printer control register */
	32	short dmfl_indrct; /* line printer indirect register */
	33	short dmfd[4]; /* for dr11 (not implemented) */
7e1a3cad SL	34	};
	35
	36	#define dmfrsp dmfrbuf /* receive silo parameter register (wo) */
	37	#define dmftbuf dmfun.dmfirc[0] /* transmit buffer */
	38	#define dmftsc dmfun.dmfirc[0] /* transmit silo count */
	39	#define dmfrms dmfun.dmfirc[1] /* receive modem status */
9c95d9b6	40	#define dmflctms dmfun.dmfirw /* line control, transmit modem status */
7e1a3cad SL	41	#define dmftba dmfun.dmfirw /* transmit buffer address */
	42	#define dmftcc dmfun.dmfirw /* transmit character count */
	43
	44	/* bits in dmfcsr */
	45	#define DMF_TI 0100000 /* transmit interrupt */
	46	#define DMF_TIE 0040000 /* transmit interrupt enable */
	47	#define DMF_NXM 0020000 /* non-existant memory */
	48	#define DMF_LIN 0003400 /* transmit line number */
	49	#define DMF_RI 0000200 /* receiver interrupt */
	50	#define DMF_RIE 0000100 /* receiver interrupt enable */
	51	#define DMF_CLR 0000040 /* master reset */
	52	#define DMF_IAD 0000037 /* indirect address register */
	53
	54	#define DMFIR_TBUF 000 /* select tbuf indirect register */
	55	#define DMFIR_LCR 010 /* select lcr indirect register */
	56	#define DMFIR_TBA 020 /* select tba indirect register */
	57	#define DMFIR_TCC 030 /* select tcc indirect register */
	58
	59	/* bits in dmflpr */
	60	#define BITS6 (01<<3)
	61	#define BITS7 (02<<3)
	62	#define BITS8 (03<<3)
	63	#define TWOSB 0200
	64	#define PENABLE 040
46245e68	65	#define EPAR 0100
7e1a3cad SL	66
	67	#define DMF_IE (DMF_TIE\|DMF_RIE)
	68
	69	#define DMF_SILOCNT 32 /* size of DMF output silo (per line) */
	70
	71	/* bits in dmfrbuf */
	72	#define DMF_DSC 0004000 /* data set change */
	73	#define DMF_PE 0010000 /* parity error */
	74	#define DMF_FE 0020000 /* framing error */
	75	#define DMF_DO 0040000 /* data overrun */
	76
	77	/* bits in dmfrms */
	78	#define DMF_USRR 0004 /* user modem signal (pin 25) */
	79	#define DMF_SR 0010 /* secondary receive */
	80	#define DMF_CTS 0020 /* clear to send */
	81	#define DMF_CAR 0040 /* carrier detect */
	82	#define DMF_RNG 0100 /* ring */
	83	#define DMF_DSR 0200 /* data set ready */
	84
	85	/* bits in dmftms */
	86	#define DMF_USRW 0001 /* user modem signal (pin 18) */
	87	#define DMF_DTR 0002 /* data terminal ready */
	88	#define DMF_RATE 0004 /* data signal rate select */
	89	#define DMF_ST 0010 /* secondary transmit */
	90	#define DMF_RTS 0020 /* request to send */
	91	#define DMF_BRK 0040 /* pseudo break bit */
	92	#define DMF_PREEMPT 0200 /* preempt output */
	93
	94	/* flags for modem control */
	95	#define DMF_ON (DMF_DTR\|DMF_RTS)
	96	#define DMF_OFF 0
	97
9c95d9b6	98	/* bits in dmflctms */
7e1a3cad SL	99	#define DMF_MIE 0040 /* modem interrupt enable */
	100	#define DMF_FLUSH 0020 /* flush transmit silo */
	101	#define DMF_RBRK 0010 /* real break bit */
	102	#define DMF_RE 0004 /* receive enable */
	103	#define DMF_AUTOX 0002 /* auto XON/XOFF */
	104	#define DMF_TE 0001 /* transmit enable */
	105
	106	#define DMFLCR_ENA (DMF_MIE\|DMF_RE\|DMF_TE)
	107
	108	/* bits in dm lsr, copied from dh.c */
	109	#define DML_USR 0001000 /* usr modem sig, not a real DM bit */
	110	#define DML_DSR 0000400 /* data set ready, not a real DM bit */
	111	#define DML_RNG 0000200 /* ring */
	112	#define DML_CAR 0000100 /* carrier detect */
	113	#define DML_CTS 0000040 /* clear to send */
	114	#define DML_SR 0000020 /* secondary receive */
	115	#define DML_ST 0000010 /* secondary transmit */
	116	#define DML_RTS 0000004 /* request to send */
	117	#define DML_DTR 0000002 /* data terminal ready */
	118	#define DML_LE 0000001 /* line enable */
	119
2775cc1e JB	120	/* dmf line printer csr def */
	121	#define DMFL_PEN (1<<0) /* print enable */
	122	#define DMFL_RESET (1<<1) /* master reset */
	123	#define DMFL_FORMAT (1<<2) /* format control */
	124	#define DMFL_UNUSED (3<<3)
	125	#define DMFL_MAINT (1<<5) /* maintenance mode on */
	126	#define DMFL_IE (1<<6) /* intr enable */
	127	#define DMFL_PDONE (1<<7) /* print done bit */
	128	#define DMFL_INDIR (7<<8) /* indirect reg */
	129	#define DMFL_UNUSED2 (1<<11)
	130	#define DMFL_CONV (1<<12) /* connect verify */
	131	#define DMFL_DAVRDY (1<<13) /* davfu ready */
	132	#define DMFL_OFFLINE (1<<14) /* printer offline */
	133	#define DMFL_DMAERR (1<<15) /* dma error bit */
	134	#define DMFL_BUFSIZ 512 /* max chars per dma */
	135	#define DMFL_DEFCOLS 132 /* default # of cols/line <=255 */
	136	#define DMFL_DEFLINES 66 /* default # of lines/page <=255 */
26505102 MK	137	#define DMFL_OPTIONS ((1 << 8) \| (1 << 9) \| (1 << 15))
26505102 MK	138	/* auto cr, real ff, no lower to upper */
2775cc1e JB	139
	140	/*
	141	* Bits in the configuration register
	142	*/
	143	#define DMFC_CONFMASK 0xf000 /* picks off the configuration bits */
	144	#define DMFC_DR 0x1000 /* DR11 parallel interface */
	145	#define DMFC_LP 0x2000 /* LP dma parallel lineprinter i'face */
	146	#define DMFC_SYNC 0x4000 /* Synchronous serial interface */
	147	#define DMFC_ASYNC 0x8000 /* 8 Serial ports */