Commit | Line | Data |
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2a75a0e9 BJ |
1 | /* vp.c 3.1 %H% */ |
2 | ||
3 | #ifdef ERNIE | |
4 | #include "../h/param.h" | |
5 | #include "../h/dir.h" | |
6 | #include "../h/user.h" | |
7 | #include "../h/buf.h" | |
8 | #include "../h/systm.h" | |
9 | #include "../h/map.h" | |
10 | #include "../h/pte.h" | |
11 | #include "../h/uba.h" | |
12 | ||
13 | /* | |
14 | * Versatec matrix printer/plotter | |
15 | * dma interface driver | |
16 | */ | |
17 | int vpbdp = 1; | |
18 | ||
19 | unsigned minvpph(); | |
20 | ||
21 | #define VPPRI (PZERO-1) | |
22 | ||
23 | struct vpregs { | |
24 | short plbcr; | |
25 | short fill; | |
26 | short prbcr; | |
27 | unsigned short pbaddr; | |
28 | short plcsr; | |
29 | short plbuf; | |
30 | short prcsr; | |
31 | unsigned short prbuf; | |
32 | }; | |
33 | ||
34 | #define VPADDR ((struct vpregs *)(UBA0_DEV + 0177500)) | |
35 | ||
36 | #define ERROR 0100000 | |
37 | #define DTCINTR 040000 | |
38 | #define DMAACT 020000 | |
39 | #define READY 0200 | |
40 | #define IENABLE 0100 | |
41 | #define TERMCOM 040 | |
42 | #define FFCOM 020 | |
43 | #define EOTCOM 010 | |
44 | #define CLRCOM 04 | |
45 | #define RESET 02 | |
46 | #define SPP 01 | |
47 | ||
48 | struct { | |
49 | int vp_state; | |
50 | int vp_count; | |
51 | int vp_bufp; | |
52 | } vp11; | |
53 | int vp_ubinfo; | |
54 | ||
55 | struct buf rvpbuf; | |
56 | ||
57 | #define VISOPEN 01 | |
58 | #define CMNDS 076 | |
59 | #define MODE 0700 | |
60 | #define PRINT 0100 | |
61 | #define PLOT 0200 | |
62 | #define PPLOT 0400 | |
63 | #define VBUSY 01000 | |
64 | ||
65 | vpopen() | |
66 | { | |
67 | ||
68 | if (vp11.vp_state & VISOPEN) { | |
69 | u.u_error = ENXIO; | |
70 | return; | |
71 | } | |
72 | vp11.vp_state = VISOPEN | PRINT | CLRCOM | RESET; | |
73 | vp11.vp_count = 0; | |
74 | VPADDR->prcsr = IENABLE | DTCINTR; | |
75 | vptimo(); | |
76 | while (vp11.vp_state & CMNDS) { | |
77 | VOID spl4(); | |
78 | if (vperror(READY)) { | |
79 | vpclose(); | |
80 | u.u_error = EIO; | |
81 | return; | |
82 | } | |
83 | vpstart(); | |
84 | VOID spl0(); | |
85 | } | |
86 | } | |
87 | ||
88 | vpstrategy(bp) | |
89 | register struct buf *bp; | |
90 | { | |
91 | register int e; | |
92 | ||
93 | VOID spl4(); | |
94 | while (vp11.vp_state & VBUSY) | |
95 | sleep((caddr_t)&vp11, VPPRI); | |
96 | vp11.vp_state |= VBUSY; | |
97 | VOID spl0(); | |
98 | vp_ubinfo = ubasetup(bp, vpbdp); | |
99 | vp11.vp_bufp = vp_ubinfo & 0x3ffff; | |
100 | VOID spl4(); | |
101 | if (e = vperror(READY)) | |
102 | goto brkout; | |
103 | vp11.vp_count = bp->b_bcount; | |
104 | vpstart(); | |
105 | while ((vp11.vp_state&PLOT ? VPADDR->plcsr : VPADDR->prcsr) & DMAACT) | |
106 | sleep((caddr_t)&vp11, VPPRI); | |
107 | vp11.vp_count = 0; | |
108 | vp11.vp_bufp = 0; | |
109 | if ((vp11.vp_state&MODE) == PPLOT) | |
110 | vp11.vp_state = (vp11.vp_state &~ MODE) | PLOT; | |
111 | VOID spl0(); | |
112 | brkout: | |
113 | ubafree(vp_ubinfo), vp_ubinfo = 0; | |
114 | vp11.vp_state &= ~VBUSY; | |
115 | iodone(bp); | |
116 | if (e) | |
117 | u.u_error = EIO; | |
118 | wakeup((caddr_t)&vp11); | |
119 | } | |
120 | ||
121 | int vpblock = 16384; | |
122 | ||
123 | unsigned | |
124 | minvpph(bp) | |
125 | struct buf *bp; | |
126 | { | |
127 | ||
128 | if (bp->b_bcount > vpblock) | |
129 | bp->b_bcount = vpblock; | |
130 | } | |
131 | ||
132 | /*ARGSUSED*/ | |
133 | vpwrite(dev) | |
134 | { | |
135 | ||
136 | physio(vpstrategy, &rvpbuf, dev, B_WRITE, minvpph); | |
137 | } | |
138 | ||
139 | vperror(bit) | |
140 | { | |
141 | register int state, e; | |
142 | ||
143 | state = vp11.vp_state & PLOT; | |
144 | while ((e = (state ? VPADDR->plcsr : VPADDR->prcsr) & (bit|ERROR)) == 0) | |
145 | sleep((caddr_t)&vp11, VPPRI); | |
146 | return (e & ERROR); | |
147 | } | |
148 | ||
149 | vpstart() | |
150 | { | |
151 | register short bit; | |
152 | ||
153 | if (vp11.vp_count) { | |
154 | VPADDR->pbaddr = vp11.vp_bufp; | |
155 | if (vp11.vp_state & (PRINT|PPLOT)) | |
156 | VPADDR->prbcr = vp11.vp_count; | |
157 | else | |
158 | VPADDR->plbcr = vp11.vp_count; | |
159 | return; | |
160 | } | |
161 | for (bit = 1; bit != 0; bit <<= 1) | |
162 | if (vp11.vp_state&bit&CMNDS) { | |
163 | VPADDR->plcsr |= bit; | |
164 | vp11.vp_state &= ~bit; | |
165 | return; | |
166 | } | |
167 | } | |
168 | ||
169 | /*ARGSUSED*/ | |
170 | vpioctl(dev, cmd, addr, flag) | |
171 | register caddr_t addr; | |
172 | { | |
173 | register int m; | |
174 | ||
175 | switch (cmd) { | |
176 | ||
177 | case ('v'<<8)+0: | |
178 | VOID suword(addr, vp11.vp_state); | |
179 | return; | |
180 | ||
181 | case ('v'<<8)+1: | |
182 | m = fuword(addr); | |
183 | if (m == -1) { | |
184 | u.u_error = EFAULT; | |
185 | return; | |
186 | } | |
187 | vp11.vp_state = (vp11.vp_state & ~MODE) | (m&(MODE|CMNDS)); | |
188 | break; | |
189 | ||
190 | default: | |
191 | u.u_error = ENOTTY; | |
192 | return; | |
193 | } | |
194 | VOID spl4(); | |
195 | VOID vperror(READY); | |
196 | if (vp11.vp_state&PPLOT) | |
197 | VPADDR->plcsr |= SPP; | |
198 | else | |
199 | VPADDR->plcsr &= ~SPP; | |
200 | vp11.vp_count = 0; | |
201 | while (CMNDS & vp11.vp_state) { | |
202 | VOID vperror(READY); | |
203 | vpstart(); | |
204 | } | |
205 | VOID spl0(); | |
206 | } | |
207 | ||
208 | vptimo() | |
209 | { | |
210 | ||
211 | if (vp11.vp_state&VISOPEN) | |
212 | timeout(vptimo, (caddr_t)0, HZ/10); | |
213 | vpintr(0); | |
214 | } | |
215 | ||
216 | /*ARGSUSED*/ | |
217 | vpintr(dev) | |
218 | { | |
219 | ||
220 | wakeup((caddr_t)&vp11); | |
221 | } | |
222 | ||
223 | vpclose() | |
224 | { | |
225 | ||
226 | vp11.vp_state = 0; | |
227 | vp11.vp_count = 0; | |
228 | vp11.vp_bufp = 0; | |
229 | VPADDR->plcsr = 0; | |
230 | } | |
231 | #endif |