[unix-history] / usr / src / sys / sparc / sbus / dmareg.h

/*
 * Copyright (c) 1992 The Regents of the University of California.
 * All rights reserved.
 *
 * This software was developed by the Computer Systems Engineering group
 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
 * contributed to Berkeley.
 *
 * All advertising materials mentioning features or use of this software
 * must display the following acknowledgement:
 *	This product includes software developed by the University of
 *	California, Lawrence Berkeley Laboratory.
 *
 * %sccs.include.redist.c%
 *
 *	@(#)dmareg.h	7.3 (Berkeley) %G%
 *
 * from: $Header: dmareg.h,v 1.5 92/11/26 02:28:08 torek Exp $ (LBL)
 */

/*
 * Sun-4c Sbus slot 0 DMA registers.
 */
struct dmareg {
	u_long	dma_csr;	/* control/status register */
	u_long	dma_addr;	/* address (virtual: is fed to MMU) */
	u_long	dma_bc;		/* byte count (not used) */
	u_long	dma_diag;	/* diagnostic register (not used) */
};

/*
 * Bits in dma_csr.
 *
 * Notes in [brackets]:
 *	1: not self-clearing, must be reset after being set.
 *	2: `drain' is like Unibus `bdp purge', i.e., it tells
 *	   the chip to finish up, because there is no more data
 *	   going into the buffer register.  Needed only in rev
 *	   1 dma chips.  Self-clearing (hence write-only).
 *	3: only in rev 1 dma chips.
 *	4: only in rev 2 dma chips.
 *	5: also enables scsi interrupts.
 */
#define	DMA_REV(csr)	(((csr) >> 28) & 0xf)	/* device id field */
#define	DMAREV_1	0x8		/* device id = rev 1 DMA */
#define	DMAREV_2	0x9		/* device id = rev 2 DMA */

#define	DMA_1ZERO	0x0fff0000	/* unused; reads as zero [3] */
#define	DMA_NAL		0x08000000	/* next address loaded [4] (ro) */
#define	DMA_AL		0x04000000	/* address loaded [4] (ro) */
#define	DMA_ON		0x02000000	/* working [4] (ro) */
#define	DMA_NAE		0x01000000	/* next-address enable [4] (rw) */
#define	DMA_DTCI	0x00800000	/* disable DMA_TC intr [4] (rw) */
#define	DMA_TURBO	0x00400000	/* faster 53C90A mode [4] (rw) */
#define	DMA_LERR	0x00200000	/* LANCE error [4] (ro) */
#define	DMA_ALE		0x00100000	/* LANCE addr latch ena [4] (rw) */
#define	DMA_2ZERO	0x000f0000	/* unused; reads as zero [4] */
#define	DMA_ILACC	0x00008000	/* set for new AMD ethernet chip */
#define	DMA_TC		0x00004000	/* terminal count: dma_bc ran out */
#define	DMA_BCE		0x00002000	/* byte count enable (leave 0) */
#define	DMA_BO		0x00001800	/* byte offset (ro) */
#define	DMA_RP		0x00000400	/* request pending (ro) */
#define	DMA_ENA		0x00000200	/* enable the dma chip */
#define	DMA_READ	0x00000100	/* set for dev=>mem, i.e., read() */
#define	DMA_RESET	0x00000080	/* reset dma chip [1] */
#define	DMA_DRAIN	0x00000040	/* drain buffered data [2,3] (wo) */
#define	DMA_ERR		0x00000040	/* slave error [4] (ro) */
#define	DMA_FLUSH	0x00000020	/* clear PC, EP, and TC [4] (wo) */
#define	DMA_IE		0x00000010	/* interrupt enable [4,5] */
#define	DMA_PC		0x0000000c	/* bytes in pack reg (ro) */
#define	DMA_EP		0x00000002	/* error pending (ro) */
#define	DMA_IP		0x00000001	/* interrupt pending (ro) */

#define	DMA_BITS \
"\20\34NAL\33AL\32ON\31NAE\30DTCI\27TURBO\26LERR\25ALE\
\20ILACC\17TC\16BCE\13RP\12ENA\11READ\10RESET\7DRAIN/ERR\6FLUSH\5IE\2EP\1IP"

/* DMA_BYTE turns the DMA_BO field into a byte index */
#define	DMA_BYTE(csr)	(((csr) >> 11) & 3)

/* DMA_NPACK turns the DMA_PC field into a byte count */
#define	DMA_NPACK(csr)	(((csr) >> 2) & 3)

/* DMA_INTR is true if the DMA chip says an ESP or DMA interrupt is pending */
#define	DMA_INTR(csr)	((csr) & (DMA_IP | DMA_EP))
Commit	Line	Data
03f392a4 CT	1	/*
	2	* Copyright (c) 1992 The Regents of the University of California.
	3	* All rights reserved.
	4	*
	5	* This software was developed by the Computer Systems Engineering group
	6	* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
	7	* contributed to Berkeley.
	8	*
b480239a KB	9	* All advertising materials mentioning features or use of this software
	10	* must display the following acknowledgement:
	11	* This product includes software developed by the University of
1869bdc0	12	* California, Lawrence Berkeley Laboratory.
b480239a	13	*
03f392a4 CT	14	* %sccs.include.redist.c%
03f392a4 CT	15	*
1869bdc0	16	* @(#)dmareg.h 7.3 (Berkeley) %G%
03f392a4	17	*
1869bdc0	18	* from: $Header: dmareg.h,v 1.5 92/11/26 02:28:08 torek Exp $ (LBL)
03f392a4 CT	19	*/
	20
	21	/*
	22	* Sun-4c Sbus slot 0 DMA registers.
	23	*/
	24	struct dmareg {
	25	u_long dma_csr; /* control/status register */
	26	u_long dma_addr; /* address (virtual: is fed to MMU) */
	27	u_long dma_bc; /* byte count (not used) */
	28	u_long dma_diag; /* diagnostic register (not used) */
	29	};
	30
	31	/*
	32	* Bits in dma_csr.
	33	*
	34	* Notes in [brackets]:
	35	* 1: not self-clearing, must be reset after being set.
	36	* 2: `drain' is like Unibus `bdp purge', i.e., it tells
	37	* the chip to finish up, because there is no more data
	38	* going into the buffer register. Needed only in rev
	39	* 1 dma chips. Self-clearing (hence write-only).
	40	* 3: only in rev 1 dma chips.
	41	* 4: only in rev 2 dma chips.
	42	* 5: also enables scsi interrupts.
	43	*/
	44	#define DMA_REV(csr) (((csr) >> 28) & 0xf) /* device id field */
	45	#define DMAREV_1 0x8 /* device id = rev 1 DMA */
	46	#define DMAREV_2 0x9 /* device id = rev 2 DMA */
	47
	48	#define DMA_1ZERO 0x0fff0000 /* unused; reads as zero [3] */
	49	#define DMA_NAL 0x08000000 /* next address loaded [4] (ro) */
	50	#define DMA_AL 0x04000000 /* address loaded [4] (ro) */
	51	#define DMA_ON 0x02000000 /* working [4] (ro) */
	52	#define DMA_NAE 0x01000000 /* next-address enable [4] (rw) */
	53	#define DMA_DTCI 0x00800000 /* disable DMA_TC intr [4] (rw) */
	54	#define DMA_TURBO 0x00400000 /* faster 53C90A mode [4] (rw) */
	55	#define DMA_LERR 0x00200000 /* LANCE error [4] (ro) */
	56	#define DMA_ALE 0x00100000 /* LANCE addr latch ena [4] (rw) */
	57	#define DMA_2ZERO 0x000f0000 /* unused; reads as zero [4] */
	58	#define DMA_ILACC 0x00008000 /* set for new AMD ethernet chip */
	59	#define DMA_TC 0x00004000 /* terminal count: dma_bc ran out */
	60	#define DMA_BCE 0x00002000 /* byte count enable (leave 0) */
	61	#define DMA_BO 0x00001800 /* byte offset (ro) */
	62	#define DMA_RP 0x00000400 /* request pending (ro) */
	63	#define DMA_ENA 0x00000200 /* enable the dma chip */
	64	#define DMA_READ 0x00000100 /* set for dev=>mem, i.e., read() */
	65	#define DMA_RESET 0x00000080 /* reset dma chip [1] */
	66	#define DMA_DRAIN 0x00000040 /* drain buffered data [2,3] (wo) */
	67	#define DMA_ERR 0x00000040 /* slave error [4] (ro) */
	68	#define DMA_FLUSH 0x00000020 /* clear PC, EP, and TC [4] (wo) */
	69	#define DMA_IE 0x00000010 /* interrupt enable [4,5] */
	70	#define DMA_PC 0x0000000c /* bytes in pack reg (ro) */
	71	#define DMA_EP 0x00000002 /* error pending (ro) */
	72	#define DMA_IP 0x00000001 /* interrupt pending (ro) */
	73
	74	#define DMA_BITS \
	75	"\20\34NAL\33AL\32ON\31NAE\30DTCI\27TURBO\26LERR\25ALE\
	76	\20ILACC\17TC\16BCE\13RP\12ENA\11READ\10RESET\7DRAIN/ERR\6FLUSH\5IE\2EP\1IP"
	77
	78	/* DMA_BYTE turns the DMA_BO field into a byte index */
	79	#define DMA_BYTE(csr) (((csr) >> 11) & 3)
	80
	81	/* DMA_NPACK turns the DMA_PC field into a byte count */
	82	#define DMA_NPACK(csr) (((csr) >> 2) & 3)
83
84	/* DMA_INTR is true if the DMA chip says an ESP or DMA interrupt is pending */
85	#define DMA_INTR(csr) ((csr) & (DMA_IP \| DMA_EP))