[unix-history] / usr / src / sys / vax / uba / dz.c

/*	dz.c	6.5	84/12/20	*/

#include "dz.h"
#if NDZ > 0
/*
 *  DZ-11/DZ-32 Driver
 *
 * This driver mimics dh.c; see it for explanation of common code.
 */
#include "bk.h"

#include "../machine/pte.h"

#include "param.h"
#include "systm.h"
#include "ioctl.h"
#include "tty.h"
#include "dir.h"
#include "user.h"
#include "proc.h"
#include "map.h"
#include "buf.h"
#include "vm.h"
#include "conf.h"
#include "bkmac.h"
#include "file.h"
#include "uio.h"
#include "kernel.h"

#include "pdma.h"
#include "ubavar.h"
#include "dzreg.h"

/*
 * Driver information for auto-configuration stuff.
 */
int	dzprobe(), dzattach(), dzrint();
struct	uba_device *dzinfo[NDZ];
u_short	dzstd[] = { 0 };
struct	uba_driver dzdriver =
	{ dzprobe, 0, dzattach, 0, dzstd, "dz", dzinfo };

#define	NDZLINE 	(NDZ*8)
#define	FASTTIMER	(hz/30)		/* rate to drain silos, when in use */

int	dzstart(), dzxint(), dzdma();
int	ttrstrt();
struct	tty dz_tty[NDZLINE];
int	dz_cnt = { NDZLINE };
int	dzact;
int	dzsilos;			/* mask of dz's with silo in use */
int	dzchars[NDZ];			/* recent input count */
int	dzrate[NDZ];			/* smoothed input count */
int	dztimerintvl;			/* time interval for dztimer */
int	dzhighrate = 100;		/* silo on if dzchars > dzhighrate */
int	dzlowrate = 75;			/* silo off if dzrate < dzlowrate */

#define dzwait(x)	while (((x)->dzlcs & DZ_ACK) == 0)

/*
 * Software copy of dzbrk since it isn't readable
 */
char	dz_brk[NDZ];
char	dzsoftCAR[NDZ];
char	dz_lnen[NDZ];	/* saved line enable bits for DZ32 */

/*
 * The dz11 doesn't interrupt on carrier transitions, so
 * we have to use a timer to watch it.
 */
char	dz_timer;		/* timer started? */

/*
 * Pdma structures for fast output code
 */
struct	pdma dzpdma[NDZLINE];

char	dz_speeds[] =
	{ 0,020,021,022,023,024,0,025,026,027,030,032,034,036,037,0 };
 
#ifndef PORTSELECTOR
#define	ISPEED	B300
#define	IFLAGS	(EVENP|ODDP|ECHO)
#else
#define	ISPEED	B4800
#define	IFLAGS	(EVENP|ODDP)
#endif

dzprobe(reg)
	caddr_t reg;
{
	register int br, cvec;
	register struct dzdevice *dzaddr = (struct dzdevice *)reg;

#ifdef lint
	br = 0; cvec = br; br = cvec;
	dzrint(0); dzxint((struct tty *)0);
#endif
	dzaddr->dzcsr = DZ_TIE|DZ_MSE|DZ_32;
	if (dzaddr->dzcsr & DZ_32)
		dzaddr->dzlnen = 1;
	else
		dzaddr->dztcr = 1;		/* enable any line */
	DELAY(100000);
	dzaddr->dzcsr = DZ_CLR|DZ_32;		/* reset everything */
	if (cvec && cvec != 0x200)
		cvec -= 4;
	return (sizeof (struct dzdevice));
}

dzattach(ui)
	register struct uba_device *ui;
{
	register struct pdma *pdp = &dzpdma[ui->ui_unit*8];
	register struct tty *tp = &dz_tty[ui->ui_unit*8];
	register int cntr;
	extern dzscan();

	for (cntr = 0; cntr < 8; cntr++) {
		pdp->p_addr = (struct dzdevice *)ui->ui_addr;
		pdp->p_arg = (int)tp;
		pdp->p_fcn = dzxint;
		pdp++, tp++;
	}
	dzsoftCAR[ui->ui_unit] = ui->ui_flags;
	if (dz_timer == 0) {
		dz_timer++;
		timeout(dzscan, (caddr_t)0, hz);
		dztimerintvl = FASTTIMER;
	}
}

/*ARGSUSED*/
dzopen(dev, flag)
	dev_t dev;
{
	register struct tty *tp;
	register int unit;
 
	unit = minor(dev);
	if (unit >= dz_cnt || dzpdma[unit].p_addr == 0)
		return (ENXIO);
	tp = &dz_tty[unit];
	tp->t_addr = (caddr_t)&dzpdma[unit];
	tp->t_oproc = dzstart;
	if ((tp->t_state & TS_ISOPEN) == 0) {
		ttychars(tp);
		tp->t_ospeed = tp->t_ispeed = ISPEED;
		tp->t_flags = IFLAGS;
		/* tp->t_state |= TS_HUPCLS; */
		dzparam(unit);
	} else if (tp->t_state&TS_XCLUDE && u.u_uid != 0)
		return (EBUSY);
	(void) dzmctl(dev, DZ_ON, DMSET);
	(void) spl5();
	while ((tp->t_state & TS_CARR_ON) == 0) {
		tp->t_state |= TS_WOPEN;
		sleep((caddr_t)&tp->t_rawq, TTIPRI);
	}
	(void) spl0();
	return ((*linesw[tp->t_line].l_open)(dev, tp));
}
 
/*ARGSUSED*/
dzclose(dev, flag)
	dev_t dev;
{
	register struct tty *tp;
	register int unit;
	register struct dzdevice *dzaddr;
	int dz;
 
	unit = minor(dev);
	dz = unit >> 3;
	tp = &dz_tty[unit];
	(*linesw[tp->t_line].l_close)(tp);
	dzaddr = dzpdma[unit].p_addr;
	if (dzaddr->dzcsr&DZ_32)
		(void) dzmctl(dev, DZ_BRK, DMBIC);
	else
		dzaddr->dzbrk = (dz_brk[dz] &= ~(1 << (unit&07)));
	if ((tp->t_state&(TS_HUPCLS|TS_WOPEN)) || (tp->t_state&TS_ISOPEN) == 0)
		(void) dzmctl(dev, DZ_OFF, DMSET);
	ttyclose(tp);
}
 
dzread(dev, uio)
	dev_t dev;
	struct uio *uio;
{
	register struct tty *tp;
 
	tp = &dz_tty[minor(dev)];
	return ((*linesw[tp->t_line].l_read)(tp, uio));
}
 
dzwrite(dev, uio)
	dev_t dev;
	struct uio *uio;
{
	register struct tty *tp;
 
	tp = &dz_tty[minor(dev)];
	return ((*linesw[tp->t_line].l_write)(tp, uio));
}
 
/*ARGSUSED*/
dzrint(dz)
	int dz;
{
	register struct tty *tp;
	register int c;
	register struct dzdevice *dzaddr;
	register struct tty *tp0;
	register int unit;
	int overrun = 0;
 
	if ((dzact & (1<<dz)) == 0)
		return;
	unit = dz * 8;
	dzaddr = dzpdma[unit].p_addr;
	tp0 = &dz_tty[unit];
	dzaddr->dzcsr &= ~(DZ_RIE|DZ_MIE);	/* the manual says this song */
	dzaddr->dzcsr |= DZ_RIE|DZ_MIE;		/*   and dance is necessary */
	while (dzaddr->dzcsr & DZ_MSC) {	/* DZ32 modem change interrupt */
		c = dzaddr->dzmtsr;
		tp = tp0 + (c&7);
		if (tp >= &dz_tty[dz_cnt])
			break;
		dzaddr->dzlcs = c&7;	/* get status of modem lines */
		dzwait(dzaddr);		/* wait for them */
		if (c & DZ_CD)		/* carrier status change? */
		if (dzaddr->dzlcs & DZ_CD) {	/* carrier up? */
			if ((tp->t_state&TS_CARR_ON) == 0) {
				wakeup((caddr_t)&tp->t_rawq);
				tp->t_state |= TS_CARR_ON;
			}
		} else {	/* no carrier */
			if (tp->t_state&TS_CARR_ON) {
				gsignal(tp->t_pgrp, SIGHUP);
				gsignal(tp->t_pgrp, SIGCONT);
				dzaddr->dzlcs = DZ_ACK|(c&7);
				ttyflush(tp, FREAD|FWRITE);
			}
			tp->t_state &= ~TS_CARR_ON;
		}
	}
	while ((c = dzaddr->dzrbuf) < 0) {	/* char present */
		dzchars[dz]++;
		tp = tp0 + ((c>>8)&07);
		if (tp >= &dz_tty[dz_cnt])
			continue;
		if ((tp->t_state & TS_ISOPEN) == 0) {
			wakeup((caddr_t)&tp->t_rawq);
#ifdef PORTSELECTOR
			if ((tp->t_state&TS_WOPEN) == 0)
#endif
			continue;
		}
		if (c&DZ_FE)
			if (tp->t_flags & RAW)
				c = 0;
			else
				c = tp->t_intrc;
		if (c&DZ_DO && overrun == 0) {
			/* printf("dz%d,%d: silo overflow\n", dz, (c>>8)&7); */
			overrun = 1;
		}
		if (c&DZ_PE)	
			if (((tp->t_flags & (EVENP|ODDP)) == EVENP)
			  || ((tp->t_flags & (EVENP|ODDP)) == ODDP))
				continue;
#if NBK > 0
		if (tp->t_line == NETLDISC) {
			c &= 0177;
			BKINPUT(c, tp);
		} else
#endif
			(*linesw[tp->t_line].l_rint)(c, tp);
	}
}
 
/*ARGSUSED*/
dzioctl(dev, cmd, data, flag)
	dev_t dev;
	caddr_t data;
{
	register struct tty *tp;
	register int unit = minor(dev);
	register int dz = unit >> 3;
	register struct dzdevice *dzaddr;
	int error;
 
	tp = &dz_tty[unit];
	error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag);
	if (error >= 0)
		return (error);
	error = ttioctl(tp, cmd, data, flag);
	if (error >= 0) {
		if (cmd == TIOCSETP || cmd == TIOCSETN || cmd == TIOCLBIS ||
		    cmd == TIOCLBIC || cmd == TIOCLSET)
			dzparam(unit);
		return (error);
	}
	switch (cmd) {

	case TIOCSBRK:
		dzaddr = ((struct pdma *)(tp->t_addr))->p_addr;
		if (dzaddr->dzcsr&DZ_32)
			(void) dzmctl(dev, DZ_BRK, DMBIS);
		else
			dzaddr->dzbrk = (dz_brk[dz] |= 1 << (unit&07));
		break;

	case TIOCCBRK:
		dzaddr = ((struct pdma *)(tp->t_addr))->p_addr;
		if (dzaddr->dzcsr&DZ_32)
			(void) dzmctl(dev, DZ_BRK, DMBIC);
		else
			dzaddr->dzbrk = (dz_brk[dz] &= ~(1 << (unit&07)));
		break;

	case TIOCSDTR:
		(void) dzmctl(dev, DZ_DTR|DZ_RTS, DMBIS);
		break;

	case TIOCCDTR:
		(void) dzmctl(dev, DZ_DTR|DZ_RTS, DMBIC);
		break;

	case TIOCMSET:
		(void) dzmctl(dev, dmtodz(*(int *)data), DMSET);
		break;

	case TIOCMBIS:
		(void) dzmctl(dev, dmtodz(*(int *)data), DMBIS);
		break;

	case TIOCMBIC:
		(void) dzmctl(dev, dmtodz(*(int *)data), DMBIC);
		break;

	case TIOCMGET:
		*(int *)data = dztodm(dzmctl(dev, 0, DMGET));
		break;

	default:
		return (ENOTTY);
	}
	return (0);
}

dmtodz(bits)
	register int bits;
{
	register int b;

	b = (bits >>1) & 0370;
	if (bits & DML_ST) b |= DZ_ST;
	if (bits & DML_RTS) b |= DZ_RTS;
	if (bits & DML_DTR) b |= DZ_DTR;
	if (bits & DML_LE) b |= DZ_LE;
	return(b);
}

dztodm(bits)
	register int bits;
{
	register int b;

	b = (bits << 1) & 0360;
	if (bits & DZ_DSR) b |= DML_DSR;
	if (bits & DZ_DTR) b |= DML_DTR;
	if (bits & DZ_ST) b |= DML_ST;
	if (bits & DZ_RTS) b |= DML_RTS;
	return(b);
}
 
dzparam(unit)
	register int unit;
{
	register struct tty *tp;
	register struct dzdevice *dzaddr;
	register int lpr;
 
	tp = &dz_tty[unit];
	dzaddr = dzpdma[unit].p_addr;
	if (dzsilos & (1 << (unit >> 3)))
		dzaddr->dzcsr = DZ_IEN | DZ_SAE;
	else
		dzaddr->dzcsr = DZ_IEN;
	dzact |= (1<<(unit>>3));
	if (tp->t_ispeed == 0) {
		(void) dzmctl(unit, DZ_OFF, DMSET);	/* hang up line */
		return;
	}
	lpr = (dz_speeds[tp->t_ispeed]<<8) | (unit & 07);
	if (tp->t_flags & (RAW|LITOUT))
		lpr |= BITS8;
	else
		lpr |= (BITS7|PENABLE);
	if ((tp->t_flags & EVENP) == 0)
		lpr |= OPAR;
	if (tp->t_ispeed == B110)
		lpr |= TWOSB;
	dzaddr->dzlpr = lpr;
}
 
dzxint(tp)
	register struct tty *tp;
{
	register struct pdma *dp;
	register dz, unit;
 
	dp = (struct pdma *)tp->t_addr;
	tp->t_state &= ~TS_BUSY;
	if (tp->t_state & TS_FLUSH)
		tp->t_state &= ~TS_FLUSH;
	else {
		ndflush(&tp->t_outq, dp->p_mem-tp->t_outq.c_cf);
		dp->p_end = dp->p_mem = tp->t_outq.c_cf;
	}
	if (tp->t_line)
		(*linesw[tp->t_line].l_start)(tp);
	else
		dzstart(tp);
	dz = minor(tp->t_dev) >> 3;
	unit = minor(tp->t_dev) & 7;
	if (tp->t_outq.c_cc == 0 || (tp->t_state&TS_BUSY)==0)
		if (dp->p_addr->dzcsr & DZ_32)
			dp->p_addr->dzlnen = (dz_lnen[dz] &= ~(1<<unit));
		else
			dp->p_addr->dztcr &= ~(1<<unit);
}

dzstart(tp)
	register struct tty *tp;
{
	register struct pdma *dp;
	register struct dzdevice *dzaddr;
	register int cc;
	int s, dz, unit;
 
	dp = (struct pdma *)tp->t_addr;
	dzaddr = dp->p_addr;
	s = spl5();
	if (tp->t_state & (TS_TIMEOUT|TS_BUSY|TS_TTSTOP))
		goto out;
	if (tp->t_outq.c_cc <= TTLOWAT(tp)) {
		if (tp->t_state&TS_ASLEEP) {
			tp->t_state &= ~TS_ASLEEP;
			wakeup((caddr_t)&tp->t_outq);
		}
		if (tp->t_wsel) {
			selwakeup(tp->t_wsel, tp->t_state & TS_WCOLL);
			tp->t_wsel = 0;
			tp->t_state &= ~TS_WCOLL;
		}
	}
	if (tp->t_outq.c_cc == 0)
		goto out;
	if (tp->t_flags & (RAW|LITOUT))
		cc = ndqb(&tp->t_outq, 0);
	else {
		cc = ndqb(&tp->t_outq, 0200);
		if (cc == 0) {
			cc = getc(&tp->t_outq);
			timeout(ttrstrt, (caddr_t)tp, (cc&0x7f) + 6);
			tp->t_state |= TS_TIMEOUT;
			goto out;
		}
	}
	tp->t_state |= TS_BUSY;
	dp->p_end = dp->p_mem = tp->t_outq.c_cf;
	dp->p_end += cc;
	dz = minor(tp->t_dev) >> 3;
	unit = minor(tp->t_dev) & 7;
	if (dzaddr->dzcsr & DZ_32)
		dzaddr->dzlnen = (dz_lnen[dz] |= (1<<unit));
	else
		dzaddr->dztcr |= (1<<unit);
out:
	splx(s);
}
 
/*
 * Stop output on a line.
 */
/*ARGSUSED*/
dzstop(tp, flag)
	register struct tty *tp;
{
	register struct pdma *dp;
	register int s;

	dp = (struct pdma *)tp->t_addr;
	s = spl5();
	if (tp->t_state & TS_BUSY) {
		dp->p_end = dp->p_mem;
		if ((tp->t_state&TS_TTSTOP)==0)
			tp->t_state |= TS_FLUSH;
	}
	splx(s);
}
 
dzmctl(dev, bits, how)
	dev_t dev;
	int bits, how;
{
	register struct dzdevice *dzaddr;
	register int unit, mbits;
	int b, s;

	unit = minor(dev);
	b = 1<<(unit&7);
	dzaddr = dzpdma[unit].p_addr;
	s = spl5();
	if (dzaddr->dzcsr & DZ_32) {
		dzwait(dzaddr)
		DELAY(100);		/* IS 100 TOO MUCH? */
		dzaddr->dzlcs = unit&7;
		DELAY(100);
		dzwait(dzaddr)
		DELAY(100);
		mbits = dzaddr->dzlcs;
		mbits &= 0177770;
	} else {
		mbits = (dzaddr->dzdtr & b) ? DZ_DTR : 0;
		mbits |= (dzaddr->dzmsr & b) ? DZ_CD : 0;
		mbits |= (dzaddr->dztbuf & b) ? DZ_RI : 0;
	}
	switch (how) {
	case DMSET:
		mbits = bits;
		break;

	case DMBIS:
		mbits |= bits;
		break;

	case DMBIC:
		mbits &= ~bits;
		break;

	case DMGET:
		(void) splx(s);
		return(mbits);
	}
	if (dzaddr->dzcsr & DZ_32) {
		mbits |= DZ_ACK|(unit&7);
		dzaddr->dzlcs = mbits;
	} else {
		if (mbits & DZ_DTR)
			dzaddr->dzdtr |= b;
		else
			dzaddr->dzdtr &= ~b;
	}
	(void) splx(s);
	return(mbits);
}
 
int dztransitions, dzfasttimers;		/*DEBUG*/
dzscan()
{
	register i;
	register struct dzdevice *dzaddr;
	register bit;
	register struct tty *tp;
	register car;
	int olddzsilos = dzsilos;
	int dztimer();
 
	for (i = 0; i < dz_cnt ; i++) {
		dzaddr = dzpdma[i].p_addr;
		if (dzaddr == 0)
			continue;
		tp = &dz_tty[i];
		bit = 1<<(i&07);
		car = 0;
		if (dzsoftCAR[i>>3]&bit)
			car = 1;
		else if (dzaddr->dzcsr & DZ_32) {
			dzaddr->dzlcs = i&07;
			dzwait(dzaddr);
			car = dzaddr->dzlcs & DZ_CD;
		} else
			car = dzaddr->dzmsr&bit;
		if (car) {
			/* carrier present */
			if ((tp->t_state & TS_CARR_ON) == 0) {
				wakeup((caddr_t)&tp->t_rawq);
				tp->t_state |= TS_CARR_ON;
			}
		} else {
			if ((tp->t_state&TS_CARR_ON) &&
			    (tp->t_flags&NOHANG) == 0) {
				/* carrier lost */
				if (tp->t_state&TS_ISOPEN) {
					gsignal(tp->t_pgrp, SIGHUP);
					gsignal(tp->t_pgrp, SIGCONT);
					dzaddr->dzdtr &= ~bit;
					ttyflush(tp, FREAD|FWRITE);
				}
				tp->t_state &= ~TS_CARR_ON;
			}
		}
	}
	for (i = 0; i < NDZ; i++) {
		ave(dzrate[i], dzchars[i], 8);
		if (dzchars[i] > dzhighrate && ((dzsilos & (1 << i)) == 0)) {
			dzpdma[i << 3].p_addr->dzcsr = DZ_IEN | DZ_SAE;
			dzsilos |= (1 << i);
			dztransitions++;		/*DEBUG*/
		} else if ((dzsilos & (1 << i)) && (dzrate[i] < dzlowrate)) {
			dzpdma[i << 3].p_addr->dzcsr = DZ_IEN;
			dzsilos &= ~(1 << i);
		}
		dzchars[i] = 0;
	}
	if (dzsilos && !olddzsilos)
		timeout(dztimer, (caddr_t)0, dztimerintvl);
	timeout(dzscan, (caddr_t)0, hz);
}

dztimer()
{
	register int dz;
	register int s;

	if (dzsilos == 0)
		return;
	s = spl5();
	dzfasttimers++;		/*DEBUG*/
	for (dz = 0; dz < NDZ; dz++)
		if (dzsilos & (1 << dz))
		    dzrint(dz);
	splx(s);
	timeout(dztimer, (caddr_t) 0, dztimerintvl);
}

/*
 * Reset state of driver if UBA reset was necessary.
 * Reset parameters and restart transmission on open lines.
 */
dzreset(uban)
	int uban;
{
	register int unit;
	register struct tty *tp;
	register struct uba_device *ui;

	for (unit = 0; unit < NDZLINE; unit++) {
		ui = dzinfo[unit >> 3];
		if (ui == 0 || ui->ui_ubanum != uban || ui->ui_alive == 0)
			continue;
		if (unit%8 == 0)
			printf(" dz%d", unit>>3);
		tp = &dz_tty[unit];
		if (tp->t_state & (TS_ISOPEN|TS_WOPEN)) {
			dzparam(unit);
			(void) dzmctl(unit, DZ_ON, DMSET);
			tp->t_state &= ~TS_BUSY;
			dzstart(tp);
		}
	}
}
#endif
Commit	Line	Data
21220e35	1	/* dz.c 6.5 84/12/20 */
5074fa57	2
66b4fb09	3	#include "dz.h"
a3cb8f60	4	#if NDZ > 0
5074fa57	5	/*
4abcd051	6	* DZ-11/DZ-32 Driver
7e00c42b BJ	7	*
7e00c42b BJ	8	* This driver mimics dh.c; see it for explanation of common code.
5074fa57	9	*/
e2c4935e	10	#include "bk.h"
961945a8 SL	11
	12	#include "../machine/pte.h"
	13
52163dab JB	14	#include "param.h"
	15	#include "systm.h"
	16	#include "ioctl.h"
	17	#include "tty.h"
	18	#include "dir.h"
	19	#include "user.h"
	20	#include "proc.h"
	21	#include "map.h"
	22	#include "buf.h"
	23	#include "vm.h"
	24	#include "conf.h"
	25	#include "bkmac.h"
	26	#include "file.h"
	27	#include "uio.h"
	28	#include "kernel.h"
d3ebf5ee	29
52163dab JB	30	#include "pdma.h"
	31	#include "ubavar.h"
	32	#include "dzreg.h"
896962b1	33
7e00c42b BJ	34	/*
	35	* Driver information for auto-configuration stuff.
	36	*/
71236e46	37	int dzprobe(), dzattach(), dzrint();
6a1a96ff	38	struct uba_device *dzinfo[NDZ];
3f3a34c3	39	u_short dzstd[] = { 0 };
3f3a34c3	40	struct uba_driver dzdriver =
71236e46	41	{ dzprobe, 0, dzattach, 0, dzstd, "dz", dzinfo };
3f3a34c3	42
a3cb8f60	43	#define NDZLINE (NDZ*8)
acd2f01b	44	#define FASTTIMER (hz/30) /* rate to drain silos, when in use */
bea90e0b	45
7e00c42b	46	int dzstart(), dzxint(), dzdma();
771d8988	47	int ttrstrt();
a3cb8f60 BJ	48	struct tty dz_tty[NDZLINE];
a3cb8f60 BJ	49	int dz_cnt = { NDZLINE };
9dca4f86	50	int dzact;
acd2f01b MK	51	int dzsilos; /* mask of dz's with silo in use */
	52	int dzchars[NDZ]; /* recent input count */
	53	int dzrate[NDZ]; /* smoothed input count */
	54	int dztimerintvl; /* time interval for dztimer */
	55	int dzhighrate = 100; /* silo on if dzchars > dzhighrate */
	56	int dzlowrate = 75; /* silo off if dzrate < dzlowrate */
5074fa57	57
bea90e0b BJ	58	#define dzwait(x) while (((x)->dzlcs & DZ_ACK) == 0)
bea90e0b BJ	59
7e00c42b BJ	60	/*
	61	* Software copy of dzbrk since it isn't readable
	62	*/
a3cb8f60 BJ	63	char dz_brk[NDZ];
a3cb8f60 BJ	64	char dzsoftCAR[NDZ];
bea90e0b	65	char dz_lnen[NDZ]; /* saved line enable bits for DZ32 */
5074fa57	66
7e00c42b	67	/*
bea90e0b	68	* The dz11 doesn't interrupt on carrier transitions, so
7e00c42b BJ	69	* we have to use a timer to watch it.
	70	*/
	71	char dz_timer; /* timer started? */
	72
	73	/*
	74	* Pdma structures for fast output code
	75	*/
a3cb8f60	76	struct pdma dzpdma[NDZLINE];
7e00c42b	77
3f3a34c3	78	char dz_speeds[] =
57644725	79	{ 0,020,021,022,023,024,0,025,026,027,030,032,034,036,037,0 };
5074fa57	80
df07bd9e SL	81	#ifndef PORTSELECTOR
	82	#define ISPEED B300
	83	#define IFLAGS (EVENP\|ODDP\|ECHO)
	84	#else
	85	#define ISPEED B4800
	86	#define IFLAGS (EVENP\|ODDP)
	87	#endif
	88
71236e46	89	dzprobe(reg)
3f3a34c3 BJ	90	caddr_t reg;
3f3a34c3 BJ	91	{
88d5b764	92	register int br, cvec;
4abcd051	93	register struct dzdevice dzaddr = (struct dzdevice )reg;
3f3a34c3	94
71236e46	95	#ifdef lint
a0eab615	96	br = 0; cvec = br; br = cvec;
89b8a44c	97	dzrint(0); dzxint((struct tty *)0);
71236e46	98	#endif
bea90e0b BJ	99	dzaddr->dzcsr = DZ_TIE\|DZ_MSE\|DZ_32;
	100	if (dzaddr->dzcsr & DZ_32)
	101	dzaddr->dzlnen = 1;
	102	else
	103	dzaddr->dztcr = 1; /* enable any line */
88d5b764	104	DELAY(100000);
bea90e0b	105	dzaddr->dzcsr = DZ_CLR\|DZ_32; /* reset everything */
88d5b764 BJ	106	if (cvec && cvec != 0x200)
88d5b764 BJ	107	cvec -= 4;
4abcd051	108	return (sizeof (struct dzdevice));
3f3a34c3 BJ	109	}
3f3a34c3 BJ	110
71236e46	111	dzattach(ui)
6a1a96ff	112	register struct uba_device *ui;
3f3a34c3 BJ	113	{
	114	register struct pdma pdp = &dzpdma[ui->ui_unit8];
	115	register struct tty tp = &dz_tty[ui->ui_unit8];
71236e46	116	register int cntr;
a3cb8f60	117	extern dzscan();
3f3a34c3	118
71236e46	119	for (cntr = 0; cntr < 8; cntr++) {
4abcd051	120	pdp->p_addr = (struct dzdevice *)ui->ui_addr;
3f3a34c3 BJ	121	pdp->p_arg = (int)tp;
	122	pdp->p_fcn = dzxint;
	123	pdp++, tp++;
	124	}
7e286c72	125	dzsoftCAR[ui->ui_unit] = ui->ui_flags;
be2b272c BJ	126	if (dz_timer == 0) {
be2b272c BJ	127	dz_timer++;
7780575a	128	timeout(dzscan, (caddr_t)0, hz);
acd2f01b	129	dztimerintvl = FASTTIMER;
be2b272c	130	}
3f3a34c3 BJ	131	}
3f3a34c3 BJ	132
5074fa57	133	/ARGSUSED/
3f3a34c3 BJ	134	dzopen(dev, flag)
3f3a34c3 BJ	135	dev_t dev;
5074fa57 BJ	136	{
5074fa57 BJ	137	register struct tty *tp;
3f3a34c3	138	register int unit;
5074fa57	139
3f3a34c3	140	unit = minor(dev);
7da157da BJ	141	if (unit >= dz_cnt \|\| dzpdma[unit].p_addr == 0)
7da157da BJ	142	return (ENXIO);
3f3a34c3 BJ	143	tp = &dz_tty[unit];
3f3a34c3 BJ	144	tp->t_addr = (caddr_t)&dzpdma[unit];
5074fa57	145	tp->t_oproc = dzstart;
941944c9	146	if ((tp->t_state & TS_ISOPEN) == 0) {
5074fa57	147	ttychars(tp);
df07bd9e SL	148	tp->t_ospeed = tp->t_ispeed = ISPEED;
df07bd9e SL	149	tp->t_flags = IFLAGS;
941944c9	150	/* tp->t_state \|= TS_HUPCLS; */
3f3a34c3	151	dzparam(unit);
7da157da BJ	152	} else if (tp->t_state&TS_XCLUDE && u.u_uid != 0)
7da157da BJ	153	return (EBUSY);
668cc26d	154	(void) dzmctl(dev, DZ_ON, DMSET);
771d8988	155	(void) spl5();
941944c9 BJ	156	while ((tp->t_state & TS_CARR_ON) == 0) {
941944c9 BJ	157	tp->t_state \|= TS_WOPEN;
5074fa57 BJ	158	sleep((caddr_t)&tp->t_rawq, TTIPRI);
5074fa57 BJ	159	}
771d8988	160	(void) spl0();
7da157da	161	return ((*linesw[tp->t_line].l_open)(dev, tp));
5074fa57 BJ	162	}
5074fa57 BJ	163
3f3a34c3 BJ	164	/ARGSUSED/
	165	dzclose(dev, flag)
	166	dev_t dev;
5074fa57 BJ	167	{
5074fa57 BJ	168	register struct tty *tp;
3f3a34c3	169	register int unit;
4abcd051	170	register struct dzdevice *dzaddr;
fa627691	171	int dz;
5074fa57	172
3f3a34c3 BJ	173	unit = minor(dev);
	174	dz = unit >> 3;
	175	tp = &dz_tty[unit];
5074fa57	176	(*linesw[tp->t_line].l_close)(tp);
bea90e0b BJ	177	dzaddr = dzpdma[unit].p_addr;
bea90e0b BJ	178	if (dzaddr->dzcsr&DZ_32)
668cc26d	179	(void) dzmctl(dev, DZ_BRK, DMBIC);
bea90e0b BJ	180	else
bea90e0b BJ	181	dzaddr->dzbrk = (dz_brk[dz] &= ~(1 << (unit&07)));
4f5daa2a	182	if ((tp->t_state&(TS_HUPCLS\|TS_WOPEN)) \|\| (tp->t_state&TS_ISOPEN) == 0)
668cc26d	183	(void) dzmctl(dev, DZ_OFF, DMSET);
5074fa57 BJ	184	ttyclose(tp);
	185	}
	186
740e4029	187	dzread(dev, uio)
3f3a34c3	188	dev_t dev;
740e4029	189	struct uio *uio;
5074fa57 BJ	190	{
	191	register struct tty *tp;
	192
3f3a34c3	193	tp = &dz_tty[minor(dev)];
740e4029	194	return ((*linesw[tp->t_line].l_read)(tp, uio));
5074fa57 BJ	195	}
5074fa57 BJ	196
406ddcbe	197	dzwrite(dev, uio)
3f3a34c3	198	dev_t dev;
406ddcbe	199	struct uio *uio;
5074fa57 BJ	200	{
	201	register struct tty *tp;
	202
3f3a34c3	203	tp = &dz_tty[minor(dev)];
078d920f	204	return ((*linesw[tp->t_line].l_write)(tp, uio));
5074fa57 BJ	205	}
5074fa57 BJ	206
9dca4f86	207	/ARGSUSED/
3f3a34c3 BJ	208	dzrint(dz)
3f3a34c3 BJ	209	int dz;
5074fa57 BJ	210	{
	211	register struct tty *tp;
	212	register int c;
4abcd051	213	register struct dzdevice *dzaddr;
9dca4f86	214	register struct tty *tp0;
3f3a34c3	215	register int unit;
b19fe459	216	int overrun = 0;
5074fa57	217
88d5b764 BJ	218	if ((dzact & (1<<dz)) == 0)
	219	return;
	220	unit = dz * 8;
	221	dzaddr = dzpdma[unit].p_addr;
	222	tp0 = &dz_tty[unit];
bea90e0b BJ	223	dzaddr->dzcsr &= ~(DZ_RIE\|DZ_MIE); /* the manual says this song */
	224	dzaddr->dzcsr \|= DZ_RIE\|DZ_MIE; /* and dance is necessary */
	225	while (dzaddr->dzcsr & DZ_MSC) { /* DZ32 modem change interrupt */
	226	c = dzaddr->dzmtsr;
	227	tp = tp0 + (c&7);
	228	if (tp >= &dz_tty[dz_cnt])
	229	break;
	230	dzaddr->dzlcs = c&7; /* get status of modem lines */
	231	dzwait(dzaddr); /* wait for them */
	232	if (c & DZ_CD) /* carrier status change? */
	233	if (dzaddr->dzlcs & DZ_CD) { /* carrier up? */
	234	if ((tp->t_state&TS_CARR_ON) == 0) {
	235	wakeup((caddr_t)&tp->t_rawq);
	236	tp->t_state \|= TS_CARR_ON;
	237	}
	238	} else { /* no carrier */
	239	if (tp->t_state&TS_CARR_ON) {
	240	gsignal(tp->t_pgrp, SIGHUP);
	241	gsignal(tp->t_pgrp, SIGCONT);
	242	dzaddr->dzlcs = DZ_ACK\|(c&7);
66923854	243	ttyflush(tp, FREAD\|FWRITE);
bea90e0b BJ	244	}
	245	tp->t_state &= ~TS_CARR_ON;
	246	}
	247	}
88d5b764	248	while ((c = dzaddr->dzrbuf) < 0) { /* char present */
acd2f01b	249	dzchars[dz]++;
88d5b764 BJ	250	tp = tp0 + ((c>>8)&07);
	251	if (tp >= &dz_tty[dz_cnt])
	252	continue;
941944c9	253	if ((tp->t_state & TS_ISOPEN) == 0) {
88d5b764	254	wakeup((caddr_t)&tp->t_rawq);
df07bd9e SL	255	#ifdef PORTSELECTOR
	256	if ((tp->t_state&TS_WOPEN) == 0)
	257	#endif
5074fa57	258	continue;
9dca4f86	259	}
7e00c42b	260	if (c&DZ_FE)
88d5b764	261	if (tp->t_flags & RAW)
7e00c42b	262	c = 0;
88d5b764	263	else
21a85e60	264	c = tp->t_intrc;
b19fe459	265	if (c&DZ_DO && overrun == 0) {
bea90e0b	266	/* printf("dz%d,%d: silo overflow\n", dz, (c>>8)&7); */
b19fe459 BJ	267	overrun = 1;
b19fe459 BJ	268	}
7e00c42b	269	if (c&DZ_PE)
88d5b764 BJ	270	if (((tp->t_flags & (EVENP\|ODDP)) == EVENP)
	271	\|\| ((tp->t_flags & (EVENP\|ODDP)) == ODDP))
	272	continue;
e2c4935e	273	#if NBK > 0
88d5b764 BJ	274	if (tp->t_line == NETLDISC) {
	275	c &= 0177;
	276	BKINPUT(c, tp);
	277	} else
e2c4935e	278	#endif
88d5b764	279	(*linesw[tp->t_line].l_rint)(c, tp);
5074fa57 BJ	280	}
	281	}
	282
	283	/ARGSUSED/
942f05a9	284	dzioctl(dev, cmd, data, flag)
3f3a34c3	285	dev_t dev;
942f05a9	286	caddr_t data;
5074fa57 BJ	287	{
5074fa57 BJ	288	register struct tty *tp;
3f3a34c3 BJ	289	register int unit = minor(dev);
3f3a34c3 BJ	290	register int dz = unit >> 3;
4abcd051	291	register struct dzdevice *dzaddr;
7da157da	292	int error;
5074fa57	293
3f3a34c3	294	tp = &dz_tty[unit];
7da157da BJ	295	error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag);
	296	if (error >= 0)
	297	return (error);
	298	error = ttioctl(tp, cmd, data, flag);
	299	if (error >= 0) {
21220e35 JB	300	if (cmd == TIOCSETP \|\| cmd == TIOCSETN \|\| cmd == TIOCLBIS \|\|
21220e35 JB	301	cmd == TIOCLBIC \|\| cmd == TIOCLSET)
3f3a34c3	302	dzparam(unit);
7da157da BJ	303	return (error);
	304	}
	305	switch (cmd) {
3f3a34c3	306
dc44829a	307	case TIOCSBRK:
bea90e0b BJ	308	dzaddr = ((struct pdma *)(tp->t_addr))->p_addr;
bea90e0b BJ	309	if (dzaddr->dzcsr&DZ_32)
668cc26d	310	(void) dzmctl(dev, DZ_BRK, DMBIS);
bea90e0b BJ	311	else
bea90e0b BJ	312	dzaddr->dzbrk = (dz_brk[dz] \|= 1 << (unit&07));
dc44829a	313	break;
942f05a9	314
dc44829a	315	case TIOCCBRK:
bea90e0b BJ	316	dzaddr = ((struct pdma *)(tp->t_addr))->p_addr;
bea90e0b BJ	317	if (dzaddr->dzcsr&DZ_32)
668cc26d	318	(void) dzmctl(dev, DZ_BRK, DMBIC);
bea90e0b BJ	319	else
bea90e0b BJ	320	dzaddr->dzbrk = (dz_brk[dz] &= ~(1 << (unit&07)));
dc44829a	321	break;
942f05a9	322
dc44829a	323	case TIOCSDTR:
668cc26d	324	(void) dzmctl(dev, DZ_DTR\|DZ_RTS, DMBIS);
dc44829a	325	break;
942f05a9	326
dc44829a	327	case TIOCCDTR:
668cc26d	328	(void) dzmctl(dev, DZ_DTR\|DZ_RTS, DMBIC);
bea90e0b	329	break;
942f05a9	330
bea90e0b	331	case TIOCMSET:
942f05a9	332	(void) dzmctl(dev, dmtodz((int )data), DMSET);
bea90e0b	333	break;
942f05a9	334
bea90e0b	335	case TIOCMBIS:
942f05a9	336	(void) dzmctl(dev, dmtodz((int )data), DMBIS);
bea90e0b	337	break;
942f05a9	338
bea90e0b	339	case TIOCMBIC:
942f05a9	340	(void) dzmctl(dev, dmtodz((int )data), DMBIC);
bea90e0b	341	break;
942f05a9	342
bea90e0b	343	case TIOCMGET:
942f05a9	344	(int )data = dztodm(dzmctl(dev, 0, DMGET));
dc44829a	345	break;
942f05a9	346
dc44829a	347	default:
7da157da	348	return (ENOTTY);
dc44829a	349	}
7da157da	350	return (0);
5074fa57	351	}
bea90e0b BJ	352
	353	dmtodz(bits)
	354	register int bits;
	355	{
	356	register int b;
	357
	358	b = (bits >>1) & 0370;
	359	if (bits & DML_ST) b \|= DZ_ST;
	360	if (bits & DML_RTS) b \|= DZ_RTS;
	361	if (bits & DML_DTR) b \|= DZ_DTR;
	362	if (bits & DML_LE) b \|= DZ_LE;
	363	return(b);
	364	}
	365
	366	dztodm(bits)
	367	register int bits;
	368	{
	369	register int b;
	370
	371	b = (bits << 1) & 0360;
	372	if (bits & DZ_DSR) b \|= DML_DSR;
	373	if (bits & DZ_DTR) b \|= DML_DTR;
	374	if (bits & DZ_ST) b \|= DML_ST;
	375	if (bits & DZ_RTS) b \|= DML_RTS;
	376	return(b);
	377	}
5074fa57	378
3f3a34c3 BJ	379	dzparam(unit)
3f3a34c3 BJ	380	register int unit;
5074fa57 BJ	381	{
5074fa57 BJ	382	register struct tty *tp;
4abcd051	383	register struct dzdevice *dzaddr;
3f3a34c3	384	register int lpr;
5074fa57	385
3f3a34c3 BJ	386	tp = &dz_tty[unit];
3f3a34c3 BJ	387	dzaddr = dzpdma[unit].p_addr;
acd2f01b MK	388	if (dzsilos & (1 << (unit >> 3)))
	389	dzaddr->dzcsr = DZ_IEN \| DZ_SAE;
	390	else
	391	dzaddr->dzcsr = DZ_IEN;
3f3a34c3	392	dzact \|= (1<<(unit>>3));
5074fa57	393	if (tp->t_ispeed == 0) {
668cc26d	394	(void) dzmctl(unit, DZ_OFF, DMSET); /* hang up line */
5074fa57 BJ	395	return;
5074fa57 BJ	396	}
3f3a34c3	397	lpr = (dz_speeds[tp->t_ispeed]<<8) \| (unit & 07);
21a85e60	398	if (tp->t_flags & (RAW\|LITOUT))
5074fa57 BJ	399	lpr \|= BITS8;
	400	else
	401	lpr \|= (BITS7\|PENABLE);
	402	if ((tp->t_flags & EVENP) == 0)
	403	lpr \|= OPAR;
7e00c42b BJ	404	if (tp->t_ispeed == B110)
7e00c42b BJ	405	lpr \|= TWOSB;
5074fa57 BJ	406	dzaddr->dzlpr = lpr;
	407	}
	408
	409	dzxint(tp)
3f3a34c3	410	register struct tty *tp;
5074fa57 BJ	411	{
5074fa57 BJ	412	register struct pdma *dp;
acd2f01b	413	register dz, unit;
5074fa57	414
3f3a34c3	415	dp = (struct pdma *)tp->t_addr;
941944c9 BJ	416	tp->t_state &= ~TS_BUSY;
	417	if (tp->t_state & TS_FLUSH)
	418	tp->t_state &= ~TS_FLUSH;
bea90e0b	419	else {
46014098	420	ndflush(&tp->t_outq, dp->p_mem-tp->t_outq.c_cf);
bea90e0b BJ	421	dp->p_end = dp->p_mem = tp->t_outq.c_cf;
bea90e0b BJ	422	}
5074fa57 BJ	423	if (tp->t_line)
	424	(*linesw[tp->t_line].l_start)(tp);
	425	else
	426	dzstart(tp);
bea90e0b BJ	427	dz = minor(tp->t_dev) >> 3;
bea90e0b BJ	428	unit = minor(tp->t_dev) & 7;
941944c9	429	if (tp->t_outq.c_cc == 0 \|\| (tp->t_state&TS_BUSY)==0)
bea90e0b BJ	430	if (dp->p_addr->dzcsr & DZ_32)
	431	dp->p_addr->dzlnen = (dz_lnen[dz] &= ~(1<<unit));
	432	else
	433	dp->p_addr->dztcr &= ~(1<<unit);
5074fa57 BJ	434	}
	435
	436	dzstart(tp)
3f3a34c3	437	register struct tty *tp;
5074fa57 BJ	438	{
5074fa57 BJ	439	register struct pdma *dp;
4abcd051	440	register struct dzdevice *dzaddr;
3f3a34c3	441	register int cc;
bea90e0b	442	int s, dz, unit;
5074fa57	443
3f3a34c3	444	dp = (struct pdma *)tp->t_addr;
5074fa57	445	dzaddr = dp->p_addr;
3f3a34c3	446	s = spl5();
941944c9	447	if (tp->t_state & (TS_TIMEOUT\|TS_BUSY\|TS_TTSTOP))
5074fa57	448	goto out;
941944c9 BJ	449	if (tp->t_outq.c_cc <= TTLOWAT(tp)) {
	450	if (tp->t_state&TS_ASLEEP) {
	451	tp->t_state &= ~TS_ASLEEP;
	452	wakeup((caddr_t)&tp->t_outq);
	453	}
	454	if (tp->t_wsel) {
	455	selwakeup(tp->t_wsel, tp->t_state & TS_WCOLL);
	456	tp->t_wsel = 0;
	457	tp->t_state &= ~TS_WCOLL;
	458	}
5074fa57 BJ	459	}
	460	if (tp->t_outq.c_cc == 0)
	461	goto out;
21a85e60	462	if (tp->t_flags & (RAW\|LITOUT))
5074fa57 BJ	463	cc = ndqb(&tp->t_outq, 0);
	464	else {
	465	cc = ndqb(&tp->t_outq, 0200);
	466	if (cc == 0) {
	467	cc = getc(&tp->t_outq);
7e00c42b	468	timeout(ttrstrt, (caddr_t)tp, (cc&0x7f) + 6);
941944c9	469	tp->t_state \|= TS_TIMEOUT;
5074fa57 BJ	470	goto out;
	471	}
	472	}
941944c9	473	tp->t_state \|= TS_BUSY;
5074fa57 BJ	474	dp->p_end = dp->p_mem = tp->t_outq.c_cf;
5074fa57 BJ	475	dp->p_end += cc;
bea90e0b BJ	476	dz = minor(tp->t_dev) >> 3;
	477	unit = minor(tp->t_dev) & 7;
	478	if (dzaddr->dzcsr & DZ_32)
	479	dzaddr->dzlnen = (dz_lnen[dz] \|= (1<<unit));
	480	else
	481	dzaddr->dztcr \|= (1<<unit);
3f3a34c3 BJ	482	out:
3f3a34c3 BJ	483	splx(s);
5074fa57 BJ	484	}
	485
	486	/*
	487	* Stop output on a line.
5074fa57 BJ	488	*/
	489	/ARGSUSED/
	490	dzstop(tp, flag)
3f3a34c3	491	register struct tty *tp;
5074fa57 BJ	492	{
	493	register struct pdma *dp;
	494	register int s;
	495
3f3a34c3	496	dp = (struct pdma *)tp->t_addr;
88d5b764	497	s = spl5();
941944c9	498	if (tp->t_state & TS_BUSY) {
5074fa57	499	dp->p_end = dp->p_mem;
941944c9 BJ	500	if ((tp->t_state&TS_TTSTOP)==0)
941944c9 BJ	501	tp->t_state \|= TS_FLUSH;
5074fa57 BJ	502	}
	503	splx(s);
	504	}
	505
bea90e0b BJ	506	dzmctl(dev, bits, how)
	507	dev_t dev;
	508	int bits, how;
5074fa57	509	{
4abcd051	510	register struct dzdevice *dzaddr;
bea90e0b BJ	511	register int unit, mbits;
	512	int b, s;
	513
	514	unit = minor(dev);
	515	b = 1<<(unit&7);
3f3a34c3	516	dzaddr = dzpdma[unit].p_addr;
bea90e0b BJ	517	s = spl5();
	518	if (dzaddr->dzcsr & DZ_32) {
	519	dzwait(dzaddr)
	520	DELAY(100); /* IS 100 TOO MUCH? */
	521	dzaddr->dzlcs = unit&7;
	522	DELAY(100);
	523	dzwait(dzaddr)
	524	DELAY(100);
	525	mbits = dzaddr->dzlcs;
	526	mbits &= 0177770;
	527	} else {
	528	mbits = (dzaddr->dzdtr & b) ? DZ_DTR : 0;
	529	mbits \|= (dzaddr->dzmsr & b) ? DZ_CD : 0;
	530	mbits \|= (dzaddr->dztbuf & b) ? DZ_RI : 0;
	531	}
	532	switch (how) {
	533	case DMSET:
	534	mbits = bits;
	535	break;
	536
	537	case DMBIS:
	538	mbits \|= bits;
	539	break;
	540
	541	case DMBIC:
	542	mbits &= ~bits;
	543	break;
	544
	545	case DMGET:
	546	(void) splx(s);
	547	return(mbits);
	548	}
	549	if (dzaddr->dzcsr & DZ_32) {
	550	mbits \|= DZ_ACK\|(unit&7);
	551	dzaddr->dzlcs = mbits;
	552	} else {
	553	if (mbits & DZ_DTR)
	554	dzaddr->dzdtr \|= b;
	555	else
	556	dzaddr->dzdtr &= ~b;
	557	}
	558	(void) splx(s);
	559	return(mbits);
5074fa57 BJ	560	}
5074fa57 BJ	561
acd2f01b	562	int dztransitions, dzfasttimers; /DEBUG/
5074fa57 BJ	563	dzscan()
	564	{
	565	register i;
4abcd051	566	register struct dzdevice *dzaddr;
5074fa57 BJ	567	register bit;
5074fa57 BJ	568	register struct tty *tp;
bea90e0b	569	register car;
acd2f01b MK	570	int olddzsilos = dzsilos;
acd2f01b MK	571	int dztimer();
5074fa57 BJ	572
	573	for (i = 0; i < dz_cnt ; i++) {
	574	dzaddr = dzpdma[i].p_addr;
be2b272c BJ	575	if (dzaddr == 0)
be2b272c BJ	576	continue;
5074fa57 BJ	577	tp = &dz_tty[i];
5074fa57 BJ	578	bit = 1<<(i&07);
bea90e0b BJ	579	car = 0;
	580	if (dzsoftCAR[i>>3]&bit)
	581	car = 1;
	582	else if (dzaddr->dzcsr & DZ_32) {
	583	dzaddr->dzlcs = i&07;
	584	dzwait(dzaddr);
	585	car = dzaddr->dzlcs & DZ_CD;
	586	} else
	587	car = dzaddr->dzmsr&bit;
	588	if (car) {
5074fa57	589	/* carrier present */
941944c9	590	if ((tp->t_state & TS_CARR_ON) == 0) {
5074fa57	591	wakeup((caddr_t)&tp->t_rawq);
941944c9	592	tp->t_state \|= TS_CARR_ON;
5074fa57 BJ	593	}
5074fa57 BJ	594	} else {
941944c9	595	if ((tp->t_state&TS_CARR_ON) &&
21a85e60	596	(tp->t_flags&NOHANG) == 0) {
5074fa57	597	/* carrier lost */
941944c9	598	if (tp->t_state&TS_ISOPEN) {
dc44829a	599	gsignal(tp->t_pgrp, SIGHUP);
160cf9ed	600	gsignal(tp->t_pgrp, SIGCONT);
dc44829a	601	dzaddr->dzdtr &= ~bit;
66923854	602	ttyflush(tp, FREAD\|FWRITE);
dc44829a	603	}
941944c9	604	tp->t_state &= ~TS_CARR_ON;
5074fa57	605	}
5074fa57 BJ	606	}
5074fa57 BJ	607	}
acd2f01b MK	608	for (i = 0; i < NDZ; i++) {
	609	ave(dzrate[i], dzchars[i], 8);
	610	if (dzchars[i] > dzhighrate && ((dzsilos & (1 << i)) == 0)) {
abca5f3b	611	dzpdma[i << 3].p_addr->dzcsr = DZ_IEN \| DZ_SAE;
acd2f01b MK	612	dzsilos \|= (1 << i);
	613	dztransitions++; /DEBUG/
	614	} else if ((dzsilos & (1 << i)) && (dzrate[i] < dzlowrate)) {
abca5f3b	615	dzpdma[i << 3].p_addr->dzcsr = DZ_IEN;
acd2f01b MK	616	dzsilos &= ~(1 << i);
	617	}
	618	dzchars[i] = 0;
	619	}
	620	if (dzsilos && !olddzsilos)
	621	timeout(dztimer, (caddr_t)0, dztimerintvl);
	622	timeout(dzscan, (caddr_t)0, hz);
5074fa57	623	}
9dca4f86 BJ	624
	625	dztimer()
	626	{
aa890753	627	register int dz;
acd2f01b	628	register int s;
9dca4f86	629
acd2f01b MK	630	if (dzsilos == 0)
	631	return;
	632	s = spl5();
	633	dzfasttimers++; /DEBUG/
a3cb8f60	634	for (dz = 0; dz < NDZ; dz++)
acd2f01b MK	635	if (dzsilos & (1 << dz))
acd2f01b MK	636	dzrint(dz);
aa890753	637	splx(s);
acd2f01b	638	timeout(dztimer, (caddr_t) 0, dztimerintvl);
9dca4f86	639	}
46014098 BJ	640
	641	/*
	642	* Reset state of driver if UBA reset was necessary.
0072a3c2	643	* Reset parameters and restart transmission on open lines.
46014098	644	*/
3f3a34c3	645	dzreset(uban)
5aa9d5ea	646	int uban;
46014098	647	{
3f3a34c3	648	register int unit;
46014098	649	register struct tty *tp;
6a1a96ff	650	register struct uba_device *ui;
46014098	651
a3cb8f60	652	for (unit = 0; unit < NDZLINE; unit++) {
5aa9d5ea RE	653	ui = dzinfo[unit >> 3];
	654	if (ui == 0 \|\| ui->ui_ubanum != uban \|\| ui->ui_alive == 0)
	655	continue;
b19fe459 BJ	656	if (unit%8 == 0)
b19fe459 BJ	657	printf(" dz%d", unit>>3);
3f3a34c3	658	tp = &dz_tty[unit];
941944c9	659	if (tp->t_state & (TS_ISOPEN\|TS_WOPEN)) {
3f3a34c3	660	dzparam(unit);
668cc26d	661	(void) dzmctl(unit, DZ_ON, DMSET);
941944c9	662	tp->t_state &= ~TS_BUSY;
0072a3c2	663	dzstart(tp);
46014098 BJ	664	}
46014098 BJ	665	}
46014098	666	}
a5cc519e	667	#endif