projects / unix-history / blame
| Commit | Line | Data |
|---|---|---|
| 28a753c6 WJ |
1 | /*- |
| 2 | * Copyright (c) 1991 The Regents of the University of California. | |
| 3 | * All rights reserved. | |
| 4 | * | |
| 5 | * Redistribution and use in source and binary forms, with or without | |
| 6 | * modification, are permitted provided that the following conditions | |
| 7 | * are met: | |
| 8 | * 1. Redistributions of source code must retain the above copyright | |
| 9 | * notice, this list of conditions and the following disclaimer. | |
| 10 | * 2. Redistributions in binary form must reproduce the above copyright | |
| 11 | * notice, this list of conditions and the following disclaimer in the | |
| 12 | * documentation and/or other materials provided with the distribution. | |
| 13 | * 3. All advertising materials mentioning features or use of this software | |
| 14 | * must display the following acknowledgement: | |
| 15 | * This product includes software developed by the University of | |
| 16 | * California, Berkeley and its contributors. | |
| 17 | * 4. Neither the name of the University nor the names of its contributors | |
| 18 | * may be used to endorse or promote products derived from this software | |
| 19 | * without specific prior written permission. | |
| 20 | * | |
| 21 | * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND | |
| 22 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
| 23 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
| 24 | * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE | |
| 25 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
| 26 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS | |
| 27 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | |
| 28 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT | |
| 29 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY | |
| 30 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF | |
| 31 | * SUCH DAMAGE. | |
| 32 | * | |
| 33 | * @(#)comreg.h 7.2 (Berkeley) 5/9/91 | |
| 34 | */ | |
| 35 | ||
| 36 | ||
| 37 | /* 16 bit baud rate divisor (lower byte in dca_data, upper in dca_ier) */ | |
| 38 | #define COMBRD(x) (1843200 / (16*(x))) | |
| 39 | ||
| 40 | /* interrupt enable register */ | |
| 41 | #define IER_ERXRDY 0x1 | |
| 42 | #define IER_ETXRDY 0x2 | |
| 43 | #define IER_ERLS 0x4 | |
| 44 | #define IER_EMSC 0x8 | |
| 45 | ||
| 46 | /* interrupt identification register */ | |
| 47 | #define IIR_IMASK 0xf | |
| 48 | #define IIR_RXTOUT 0xc | |
| 49 | #define IIR_RLS 0x6 | |
| 50 | #define IIR_RXRDY 0x4 | |
| 51 | #define IIR_TXRDY 0x2 | |
| 52 | #define IIR_NOPEND 0x1 | |
| 53 | #define IIR_MLSC 0x0 | |
| 54 | #define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */ | |
| 55 | ||
| 56 | /* fifo control register */ | |
| 57 | #define FIFO_ENABLE 0x01 | |
| 58 | #define FIFO_RCV_RST 0x02 | |
| 59 | #define FIFO_XMT_RST 0x04 | |
| 60 | #define FIFO_DMA_MODE 0x08 | |
| 61 | #define FIFO_TRIGGER_1 0x00 | |
| 62 | #define FIFO_TRIGGER_4 0x40 | |
| 63 | #define FIFO_TRIGGER_8 0x80 | |
| 64 | #define FIFO_TRIGGER_14 0xc0 | |
| 65 | ||
| 66 | /* character format control register */ | |
| 67 | #define CFCR_DLAB 0x80 | |
| 68 | #define CFCR_SBREAK 0x40 | |
| 69 | #define CFCR_PZERO 0x30 | |
| 70 | #define CFCR_PONE 0x20 | |
| 71 | #define CFCR_PEVEN 0x10 | |
| 72 | #define CFCR_PODD 0x00 | |
| 73 | #define CFCR_PENAB 0x08 | |
| 74 | #define CFCR_STOPB 0x04 | |
| 75 | #define CFCR_8BITS 0x03 | |
| 76 | #define CFCR_7BITS 0x02 | |
| 77 | #define CFCR_6BITS 0x01 | |
| 78 | #define CFCR_5BITS 0x00 | |
| 79 | ||
| 80 | /* modem control register */ | |
| 81 | #define MCR_LOOPBACK 0x10 | |
| 82 | #define MCR_IENABLE 0x08 | |
| 83 | #define MCR_DRS 0x04 | |
| 84 | #define MCR_RTS 0x02 | |
| 85 | #define MCR_DTR 0x01 | |
| 86 | ||
| 87 | /* line status register */ | |
| 88 | #define LSR_RCV_FIFO 0x80 | |
| 89 | #define LSR_TSRE 0x40 | |
| 90 | #define LSR_TXRDY 0x20 | |
| 91 | #define LSR_BI 0x10 | |
| 92 | #define LSR_FE 0x08 | |
| 93 | #define LSR_PE 0x04 | |
| 94 | #define LSR_OE 0x02 | |
| 95 | #define LSR_RXRDY 0x01 | |
| 96 | #define LSR_RCV_MASK 0x1f | |
| 97 | ||
| 98 | /* modem status register */ | |
| 99 | #define MSR_DCD 0x80 | |
| 100 | #define MSR_RI 0x40 | |
| 101 | #define MSR_DSR 0x20 | |
| 102 | #define MSR_CTS 0x10 | |
| 103 | #define MSR_DDCD 0x08 | |
| 104 | #define MSR_TERI 0x04 | |
| 105 | #define MSR_DDSR 0x02 | |
| 106 | #define MSR_DCTS 0x01 | |
| 107 | ||
| 108 | /* | |
| 109 | * WARNING: Serial console is assumed to be at COM1 address | |
| 110 | * and CONUNIT must be 0. | |
| 111 | */ | |
| 112 | #define CONADDR (0x3f8) | |
| 113 | #define CONUNIT (0) |