[unix-history] / sys / i386 / isa / vector.s

/*
 *	from: vector.s, 386BSD 0.1 unknown origin
 *	$Id: vector.s,v 1.6 1994/01/10 23:15:09 ache Exp $
 */

#include "i386/isa/icu.h"
#include "i386/isa/isa.h"
#include "vector.h"

#define	ICU_EOI			0x20	/* XXX - define elsewhere */

#define	IRQ_BIT(irq_num)	(1 << ((irq_num) % 8))
#define	IRQ_BYTE(irq_num)	((irq_num) / 8)

#ifdef AUTO_EOI_1
#define	ENABLE_ICU1		/* use auto-EOI to reduce i/o */
#else
#define	ENABLE_ICU1 \
	movb	$ICU_EOI,%al ;	/* as soon as possible send EOI ... */ \
	FASTER_NOP ;		/* ... ASAP ... */ \
	outb	%al,$IO_ICU1	/* ... to clear in service bit */
#endif

#ifdef AUTO_EOI_2
/*
 * The data sheet says no auto-EOI on slave, but it sometimes works.
 */
#define	ENABLE_ICU1_AND_2	ENABLE_ICU1
#else
#define	ENABLE_ICU1_AND_2 \
	movb	$ICU_EOI,%al ;	/* as above */ \
	FASTER_NOP ; \
	outb	%al,$IO_ICU2 ;	/* but do second icu first */ \
	FASTER_NOP ; \
	outb	%al,$IO_ICU1	/* then first icu */
#endif

#ifdef FAST_INTR_HANDLER_USES_ES
#define	ACTUALLY_PUSHED		1
#define	MAYBE_MOVW_AX_ES	movl	%ax,%es
#define	MAYBE_POPL_ES		popl	%es
#define	MAYBE_PUSHL_ES		pushl	%es
#else
/*
 * We can usually skip loading %es for fastintr handlers.  %es should
 * only be used for string instructions, and fastintr handlers shouldn't
 * do anything slow enough to justify using a string instruction.
 */
#define	ACTUALLY_PUSHED		0
#define	MAYBE_MOVW_AX_ES
#define	MAYBE_POPL_ES
#define	MAYBE_PUSHL_ES
#endif

/*
 * Macros for interrupt interrupt entry, call to handler, and exit.
 *
 * XXX - the interrupt frame is set up to look like a trap frame.  This is
 * usually a waste of time.  The only interrupt handlers that want a frame
 * are the clock handler (it wants a clock frame), the npx handler (it's
 * easier to do right all in assembler).  The interrupt return routine
 * needs a trap frame for rare AST's (it could easily convert the frame).
 * The direct costs of setting up a trap frame are two pushl's (error
 * code and trap number), an addl to get rid of these, and pushing and
 * popping the call-saved regs %esi, %edi and %ebp twice,  The indirect
 * costs are making the driver interface nonuniform so unpending of
 * interrupts is more complicated and slower (call_driver(unit) would
 * be easier than ensuring an interrupt frame for all handlers.  Finally,
 * there are some struct copies in the npx handler and maybe in the clock
 * handler that could be avoided by working more with pointers to frames
 * instead of frames.
 *
 * XXX - should we do a cld on every system entry to avoid the requirement
 * for scattered cld's?
 *
 * Coding notes for *.s:
 *
 * If possible, avoid operations that involve an operand size override.
 * Word-sized operations might be smaller, but the operand size override
 * makes them slower on on 486's and no faster on 386's unless perhaps
 * the instruction pipeline is depleted.  E.g.,
 *
 *	Use movl to seg regs instead of the equivalent but more descriptive
 *	movw - gas generates an irelevant (slower) operand size override.
 *
 *	Use movl to ordinary regs in preference to movw and especially
 *	in preference to movz[bw]l.  Use unsigned (long) variables with the
 *	top bits clear instead of unsigned short variables to provide more
 *	opportunities for movl.
 *
 * If possible, use byte-sized operations.  They are smaller and no slower.
 *
 * Use (%reg) instead of 0(%reg) - gas generates larger code for the latter.
 *
 * If the interrupt frame is made more flexible,  INTR can push %eax first
 * and decide the ipending case with less overhead, e.g., by avoiding
 * loading segregs.
 */

#define	FAST_INTR(unit, irq_num, id_num, handler, enable_icus) \
	pushl	%eax ;		/* save only call-used registers */ \
	pushl	%ecx ; \
	pushl	%edx ; \
	pushl	%ds ; \
	MAYBE_PUSHL_ES ; \
	movl	$KDSEL,%eax ; \
	movl	%ax,%ds ; \
	MAYBE_MOVW_AX_ES ; \
	FAKE_MCOUNT((4+ACTUALLY_PUSHED)*4(%esp)) ; \
	pushl	$unit ; \
	call	handler ;	/* do the work ASAP */ \
	enable_icus ;		/* (re)enable ASAP (helps edge trigger?) */ \
	addl	$4,%esp ; \
	incl	_cnt+V_INTR ;	/* book-keeping can wait */ \
	incl	_intrcnt_actv + (id_num) * 4 ; \
	movl	_cpl,%eax ;	/* are we unmasking pending HWIs or SWIs? */ \
	notl	%eax ; \
	andl	_ipending,%eax ; \
	jne	1f ;		/* yes, handle them */ \
	MEXITCOUNT ; \
	MAYBE_POPL_ES ; \
	popl	%ds ; \
	popl	%edx ; \
	popl	%ecx ; \
	popl	%eax ; \
	iret ; \
; \
	ALIGN_TEXT ; \
1: ; \
	movl	_cpl,%eax ; \
	movl	$HWI_MASK|SWI_MASK,_cpl ;	/* limit nesting ... */ \
	sti ;			/* ... to do this as early as possible */ \
	MAYBE_POPL_ES ;		/* discard most of thin frame ... */ \
	popl	%ecx ;		/* ... original %ds ... */ \
	popl	%edx ; \
	xchgl	%eax,(1+ACTUALLY_PUSHED)*4(%esp) ; /* orig %eax; save cpl */ \
	pushal ;		/* build fat frame (grrr) ... */ \
	pushl	%ecx ;		/* ... actually %ds ... */ \
	pushl	%es ; \
	movl	$KDSEL,%eax ; \
	movl	%ax,%es ; \
	movl	(2+8+0)*4(%esp),%ecx ;	/* ... %ecx from thin frame ... */ \
	movl	%ecx,(2+6)*4(%esp) ;	/* ... to fat frame ... */ \
	movl	(2+8+1)*4(%esp),%eax ;	/* ... cpl from thin frame */ \
	pushl	%eax ; \
	subl	$4,%esp ;	/* junk for unit number */ \
	MEXITCOUNT ; \
	jmp	_doreti

#define	INTR(unit, irq_num, id_num, mask, handler, icu, enable_icus, reg, stray) \
	pushl	$0 ;		/* dumby error code */ \
	pushl	$0 ;		/* dumby trap type */ \
	pushal ; \
	pushl	%ds ;		/* save our data and extra segments ... */ \
	pushl	%es ; \
	movl	$KDSEL,%eax ;	/* ... and reload with kernel's own ... */ \
	movl	%ax,%ds ;	/* ... early for obsolete reasons */ \
	movl	%ax,%es ; \
	movb	_imen + IRQ_BYTE(irq_num),%al ; \
	orb	$IRQ_BIT(irq_num),%al ; \
	movb	%al,_imen + IRQ_BYTE(irq_num) ; \
	FASTER_NOP ; \
	outb	%al,$icu+1 ; \
	enable_icus ; \
	incl	_cnt+V_INTR ;	/* tally interrupts */ \
	movl	_cpl,%eax ; \
	testb	$IRQ_BIT(irq_num),%reg ; \
	jne	2f ; \
1: ; \
	FAKE_MCOUNT(12*4(%esp)) ;	/* XXX late to avoid double count */ \
	incl	_intrcnt_actv + (id_num) * 4 ; \
	movl	_cpl,%eax ; \
	pushl	%eax ; \
	pushl	$unit ; \
	orl	mask,%eax ; \
	movl	%eax,_cpl ; \
	sti ; \
	call	handler ; \
	movb	_imen + IRQ_BYTE(irq_num),%al ; \
	andb	$~IRQ_BIT(irq_num),%al ; \
	movb	%al,_imen + IRQ_BYTE(irq_num) ; \
	FASTER_NOP ; \
	outb	%al,$icu+1 ; \
	MEXITCOUNT ; \
	/* We could usually avoid the following jmp by inlining some of */ \
	/* _doreti, but it's probably better to use less cache. */ \
	jmp	_doreti ; \
; \
	ALIGN_TEXT ; \
2: ; \
	/* XXX skip mcounting here to avoid double count */ \
	movl	$1b,%eax ;	/* register resume address */ \
				/* XXX - someday do it at attach time */ \
	movl	%eax,ihandlers + (irq_num) * 4 ;	\
	orb	$IRQ_BIT(irq_num),_ipending + IRQ_BYTE(irq_num) ; \
	popl	%es ; \
	popl	%ds ; \
	popal ; \
	addl	$4+4,%esp ; \
	iret

/*
 * vector.h has defined a macro 'BUILD_VECTORS' containing a big list of info
 * about vectors, including a submacro 'BUILD_VECTOR' that operates on the
 * info about each vector.  We redefine 'BUILD_VECTOR' to expand the info
 * in different ways.  Here we expand it to a list of interrupt handlers.
 * This order is of course unimportant.  Elsewhere we expand it to inline
 * linear search code for which the order is a little more important and
 * concatenating the code with no holes is very important.
 *
 * XXX - now there is BUILD_FAST_VECTOR as well as BUILD_VECTOR.
 *
 * The info consists of the following items for each vector:
 *
 *	name (identifier):	name of the vector; used to build labels
 *	unit (expression):	unit number to call the device driver with
 *	irq_num (number):	number of the IRQ to handled (0-15)
 *	id_num (number):	uniq numeric id for handler (assigned by config)
 *	mask (blank-ident):	priority mask used
 *	handler (blank-ident):	interrupt handler to call
 *	icu_num (number):	(1 + irq_num / 8) converted for label building
 *	icu_enables (number):	1 for icu_num == 1, 1_AND_2 for icu_num == 2
 *	reg (blank-ident):	al for icu_num == 1, ah for icu_num == 2
 *
 * 'irq_num' is converted in several ways at config time to get around
 * limitations in cpp.  The macros have blanks after commas iff they would
 * not mess up identifiers and numbers.
 */

#undef BUILD_FAST_VECTOR
#define	BUILD_FAST_VECTOR(name, unit, irq_num, id_num, mask, handler, \
			  icu_num, icu_enables, reg) \
	.globl	handler ; \
	.text ; \
	.globl	_V/**/name ; \
	SUPERALIGN_TEXT ; \
_V/**/name: ; \
	FAST_INTR(unit, irq_num,id_num, handler, ENABLE_ICU/**/icu_enables)

#undef BUILD_VECTOR
#define	BUILD_VECTOR(name, unit, irq_num, id_num, mask, handler, \
		     icu_num, icu_enables, reg) \
	.globl	handler ; \
	.text ; \
	.globl	_V/**/name ; \
	SUPERALIGN_TEXT ; \
_V/**/name: ; \
	INTR(unit,irq_num, id_num, mask, handler, IO_ICU/**/icu_num, \
	     ENABLE_ICU/**/icu_enables, reg,)

MCOUNT_LABEL(bintr)
	BUILD_VECTORS

	/* hardware interrupt catcher (IDT 32 - 47) */
	.globl	_isa_strayintr

#define	STRAYINTR(irq_num, icu_num, icu_enables, reg) \
IDTVEC(intr/**/irq_num) ; \
	INTR(irq_num,irq_num,irq_num, _high_imask,  _isa_strayintr, \
		  IO_ICU/**/icu_num, ENABLE_ICU/**/icu_enables, reg,stray)

/*
 * XXX - the mask (1 << 2) == IRQ_SLAVE will be generated for IRQ 2, instead
 * of the mask IRQ2 (defined as IRQ9 == (1 << 9)).  But IRQ 2 "can't happen".
 * In fact, all stray interrupts "can't happen" except for bugs.  The
 * "stray" IRQ 7 is documented behaviour of the 8259.  It happens when there
 * is a glitch on any of its interrupt inputs.  Does it really interrupt when
 * IRQ 7 is masked?
 *
 * XXX - unpend doesn't work for these, it sends them to the real handler.
 *
 * XXX - the race bug during initialization may be because I changed the
 * order of switching from the stray to the real interrupt handler to before
 * enabling interrupts.  The old order looked unsafe but maybe it is OK with
 * the stray interrupt handler installed.  But these handlers only reduce
 * the window of vulnerability - it is still open at the end of
 * isa_configure().
 *
 * XXX - many comments are stale.
 */

	STRAYINTR(0,1,1, al)
	STRAYINTR(1,1,1, al)
	STRAYINTR(2,1,1, al)
	STRAYINTR(3,1,1, al)
	STRAYINTR(4,1,1, al)
	STRAYINTR(5,1,1, al)
	STRAYINTR(6,1,1, al)
	STRAYINTR(7,1,1, al)
	STRAYINTR(8,2,1_AND_2, ah)
	STRAYINTR(9,2,1_AND_2, ah)
	STRAYINTR(10,2,1_AND_2, ah)
	STRAYINTR(11,2,1_AND_2, ah)
	STRAYINTR(12,2,1_AND_2, ah)
	STRAYINTR(13,2,1_AND_2, ah)
	STRAYINTR(14,2,1_AND_2, ah)
	STRAYINTR(15,2,1_AND_2, ah)
#if 0
	INTRSTRAY(255, _highmask, 255) ; call	_isa_strayintr ; INTREXIT2
#endif
MCOUNT_LABEL(eintr)

/*
 * These are the interrupt counters, I moved them here from icu.s so that
 * they are with the name table.  rgrimes
 *
 * There are now lots of counters, this has been redone to work with
 * Bruce Evans intr-0.1 code, which I modified some more to make it all
 * work with vmstat.
 */
	.data
ihandlers:			/* addresses of interrupt handlers */
	.space	NHWI*4		/* actually resumption addresses for HWI's */
	.long	swi_tty, swi_net, 0, 0, 0, 0, 0, 0
	.long	0, 0, 0, 0, 0, 0, swi_clock, swi_ast
imasks:				/* masks for interrupt handlers */
	.space	NHWI*4		/* padding; HWI masks are elsewhere */
	.long	SWI_TTY_MASK, SWI_NET_MASK, 0, 0, 0, 0, 0, 0
	.long	0, 0, 0, 0, 0, 0, SWI_CLOCK_MASK, SWI_AST_MASK

	.globl	_intrcnt
_intrcnt:			/* used by vmstat to calc size of table */
	.globl	_intrcnt_bad7
_intrcnt_bad7:	.space	4	/* glitches on irq 7 */
	.globl	_intrcnt_bad15
_intrcnt_bad15:	.space	4	/* glitches on irq 15 */
	.globl	_intrcnt_stray
_intrcnt_stray:	.space	4	/* total count of stray interrupts */
	.globl	_intrcnt_actv
_intrcnt_actv:	.space	NR_REAL_INT_HANDLERS * 4	/* active interrupts */
	.globl	_eintrcnt
_eintrcnt:			/* used by vmstat to calc size of table */

/*
 * Build the interrupt name table for vmstat
 */

#undef BUILD_FAST_VECTOR
#define BUILD_FAST_VECTOR	BUILD_VECTOR

#undef BUILD_VECTOR
#define	BUILD_VECTOR(name, unit, irq_num, id_num, mask, handler, \
		     icu_num, icu_enables, reg) \
	.ascii	"name irq" ; \
	.asciz	"irq_num"
/*
 * XXX - use the __STRING and __CONCAT macros from <sys/cdefs.h> to stringize
 * and concatenate names above and elsewhere.  Note that __CONCAT doesn't
 * work when nested.
 */

	.text
	.globl	_intrnames, _eintrnames
_intrnames:
	BUILD_VECTOR(bad,,7,,,,,,)
	BUILD_VECTOR(bad,,15,,,,,,)
	BUILD_VECTOR(stray,,,,,,,,)
	BUILD_VECTORS

_eintrnames:
Commit	Line	Data
15637ed4	1	/*
d7136515	2	* from: vector.s, 386BSD 0.1 unknown origin
1c7454b0	3	* $Id: vector.s,v 1.6 1994/01/10 23:15:09 ache Exp $
15637ed4 RG	4	*/
	5
	6	#include "i386/isa/icu.h"
	7	#include "i386/isa/isa.h"
	8	#include "vector.h"
	9
	10	#define ICU_EOI 0x20 /* XXX - define elsewhere */
	11
	12	#define IRQ_BIT(irq_num) (1 << ((irq_num) % 8))
	13	#define IRQ_BYTE(irq_num) ((irq_num) / 8)
	14
1c7454b0 DG	15	#ifdef AUTO_EOI_1
	16	#define ENABLE_ICU1 /* use auto-EOI to reduce i/o */
	17	#else
15637ed4 RG	18	#define ENABLE_ICU1 \
	19	movb $ICU_EOI,%al ; /* as soon as possible send EOI ... */ \
	20	FASTER_NOP ; /* ... ASAP ... */ \
	21	outb %al,$IO_ICU1 /* ... to clear in service bit */
15637ed4 RG	22	#endif
15637ed4 RG	23
1c7454b0 DG	24	#ifdef AUTO_EOI_2
	25	/*
	26	* The data sheet says no auto-EOI on slave, but it sometimes works.
	27	*/
	28	#define ENABLE_ICU1_AND_2 ENABLE_ICU1
	29	#else
15637ed4 RG	30	#define ENABLE_ICU1_AND_2 \
	31	movb $ICU_EOI,%al ; /* as above */ \
	32	FASTER_NOP ; \
	33	outb %al,$IO_ICU2 ; /* but do second icu first */ \
	34	FASTER_NOP ; \
	35	outb %al,$IO_ICU1 /* then first icu */
1c7454b0 DG	36	#endif
	37
	38	#ifdef FAST_INTR_HANDLER_USES_ES
	39	#define ACTUALLY_PUSHED 1
	40	#define MAYBE_MOVW_AX_ES movl %ax,%es
	41	#define MAYBE_POPL_ES popl %es
	42	#define MAYBE_PUSHL_ES pushl %es
	43	#else
	44	/*
	45	* We can usually skip loading %es for fastintr handlers. %es should
	46	* only be used for string instructions, and fastintr handlers shouldn't
	47	* do anything slow enough to justify using a string instruction.
	48	*/
	49	#define ACTUALLY_PUSHED 0
	50	#define MAYBE_MOVW_AX_ES
	51	#define MAYBE_POPL_ES
	52	#define MAYBE_PUSHL_ES
15637ed4 RG	53	#endif
	54
	55	/*
	56	* Macros for interrupt interrupt entry, call to handler, and exit.
	57	*
	58	* XXX - the interrupt frame is set up to look like a trap frame. This is
	59	* usually a waste of time. The only interrupt handlers that want a frame
	60	* are the clock handler (it wants a clock frame), the npx handler (it's
	61	* easier to do right all in assembler). The interrupt return routine
	62	* needs a trap frame for rare AST's (it could easily convert the frame).
	63	* The direct costs of setting up a trap frame are two pushl's (error
	64	* code and trap number), an addl to get rid of these, and pushing and
	65	* popping the call-saved regs %esi, %edi and %ebp twice, The indirect
	66	* costs are making the driver interface nonuniform so unpending of
	67	* interrupts is more complicated and slower (call_driver(unit) would
	68	* be easier than ensuring an interrupt frame for all handlers. Finally,
	69	* there are some struct copies in the npx handler and maybe in the clock
	70	* handler that could be avoided by working more with pointers to frames
	71	* instead of frames.
	72	*
	73	* XXX - should we do a cld on every system entry to avoid the requirement
	74	* for scattered cld's?
	75	*
	76	* Coding notes for *.s:
	77	*
	78	* If possible, avoid operations that involve an operand size override.
	79	* Word-sized operations might be smaller, but the operand size override
	80	* makes them slower on on 486's and no faster on 386's unless perhaps
	81	* the instruction pipeline is depleted. E.g.,
	82	*
	83	* Use movl to seg regs instead of the equivalent but more descriptive
	84	* movw - gas generates an irelevant (slower) operand size override.
	85	*
	86	* Use movl to ordinary regs in preference to movw and especially
	87	* in preference to movz[bw]l. Use unsigned (long) variables with the
	88	* top bits clear instead of unsigned short variables to provide more
	89	* opportunities for movl.
	90	*
	91	* If possible, use byte-sized operations. They are smaller and no slower.
	92	*
	93	* Use (%reg) instead of 0(%reg) - gas generates larger code for the latter.
	94	*
	95	* If the interrupt frame is made more flexible, INTR can push %eax first
	96	* and decide the ipending case with less overhead, e.g., by avoiding
	97	* loading segregs.
	98	*/
	99
	100	#define FAST_INTR(unit, irq_num, id_num, handler, enable_icus) \
	101	pushl %eax ; /* save only call-used registers */ \
	102	pushl %ecx ; \
	103	pushl %edx ; \
	104	pushl %ds ; \
1c7454b0	105	MAYBE_PUSHL_ES ; \
15637ed4 RG	106	movl $KDSEL,%eax ; \
15637ed4 RG	107	movl %ax,%ds ; \
1c7454b0 DG	108	MAYBE_MOVW_AX_ES ; \
1c7454b0 DG	109	FAKE_MCOUNT((4+ACTUALLY_PUSHED)*4(%esp)) ; \
15637ed4 RG	110	pushl $unit ; \
	111	call handler ; /* do the work ASAP */ \
	112	enable_icus ; /* (re)enable ASAP (helps edge trigger?) */ \
	113	addl $4,%esp ; \
	114	incl _cnt+V_INTR ; /* book-keeping can wait */ \
1c7454b0 DG	115	incl _intrcnt_actv + (id_num) * 4 ; \
	116	movl _cpl,%eax ; /* are we unmasking pending HWIs or SWIs? */ \
	117	notl %eax ; \
	118	andl _ipending,%eax ; \
	119	jne 1f ; /* yes, handle them */ \
	120	MEXITCOUNT ; \
	121	MAYBE_POPL_ES ; \
15637ed4	122	popl %ds ; \
1c7454b0 DG	123	popl %edx ; \
	124	popl %ecx ; \
	125	popl %eax ; \
	126	iret ; \
	127	; \
	128	ALIGN_TEXT ; \
	129	1: ; \
	130	movl _cpl,%eax ; \
	131	movl $HWI_MASK\|SWI_MASK,_cpl ; /* limit nesting ... */ \
	132	sti ; /* ... to do this as early as possible */ \
	133	MAYBE_POPL_ES ; /* discard most of thin frame ... */ \
	134	popl %ecx ; /* ... original %ds ... */ \
	135	popl %edx ; \
	136	xchgl %eax,(1+ACTUALLY_PUSHED)4(%esp) ; / orig %eax; save cpl */ \
	137	pushal ; /* build fat frame (grrr) ... */ \
	138	pushl %ecx ; /* ... actually %ds ... */ \
	139	pushl %es ; \
	140	movl $KDSEL,%eax ; \
	141	movl %ax,%es ; \
	142	movl (2+8+0)4(%esp),%ecx ; / ... %ecx from thin frame ... */ \
	143	movl %ecx,(2+6)4(%esp) ; / ... to fat frame ... */ \
	144	movl (2+8+1)4(%esp),%eax ; / ... cpl from thin frame */ \
	145	pushl %eax ; \
	146	subl $4,%esp ; /* junk for unit number */ \
	147	MEXITCOUNT ; \
	148	jmp _doreti
15637ed4 RG	149
15637ed4 RG	150	#define INTR(unit, irq_num, id_num, mask, handler, icu, enable_icus, reg, stray) \
1c7454b0 DG	151	pushl $0 ; /* dumby error code */ \
1c7454b0 DG	152	pushl $0 ; /* dumby trap type */ \
15637ed4	153	pushal ; \
1c7454b0	154	pushl %ds ; /* save our data and extra segments ... */ \
15637ed4 RG	155	pushl %es ; \
15637ed4 RG	156	movl $KDSEL,%eax ; /* ... and reload with kernel's own ... */ \
1c7454b0	157	movl %ax,%ds ; /* ... early for obsolete reasons */ \
15637ed4	158	movl %ax,%es ; \
15637ed4 RG	159	movb _imen + IRQ_BYTE(irq_num),%al ; \
	160	orb $IRQ_BIT(irq_num),%al ; \
	161	movb %al,_imen + IRQ_BYTE(irq_num) ; \
15637ed4 RG	162	FASTER_NOP ; \
	163	outb %al,$icu+1 ; \
	164	enable_icus ; \
	165	incl _cnt+V_INTR ; /* tally interrupts */ \
	166	movl _cpl,%eax ; \
	167	testb $IRQ_BIT(irq_num),%reg ; \
	168	jne 2f ; \
	169	1: ; \
1c7454b0 DG	170	FAKE_MCOUNT(124(%esp)) ; / XXX late to avoid double count */ \
1c7454b0 DG	171	incl _intrcnt_actv + (id_num) * 4 ; \
15637ed4 RG	172	movl _cpl,%eax ; \
	173	pushl %eax ; \
	174	pushl $unit ; \
	175	orl mask,%eax ; \
	176	movl %eax,_cpl ; \
15637ed4 RG	177	sti ; \
	178	call handler ; \
	179	movb _imen + IRQ_BYTE(irq_num),%al ; \
	180	andb $~IRQ_BIT(irq_num),%al ; \
	181	movb %al,_imen + IRQ_BYTE(irq_num) ; \
15637ed4 RG	182	FASTER_NOP ; \
15637ed4 RG	183	outb %al,$icu+1 ; \
1c7454b0 DG	184	MEXITCOUNT ; \
	185	/* We could usually avoid the following jmp by inlining some of */ \
	186	/* _doreti, but it's probably better to use less cache. */ \
	187	jmp _doreti ; \
15637ed4 RG	188	; \
	189	ALIGN_TEXT ; \
	190	2: ; \
1c7454b0	191	/* XXX skip mcounting here to avoid double count */ \
15637ed4 RG	192	movl $1b,%eax ; /* register resume address */ \
15637ed4 RG	193	/* XXX - someday do it at attach time */ \
1c7454b0	194	movl %eax,ihandlers + (irq_num) * 4 ; \
15637ed4	195	orb $IRQ_BIT(irq_num),_ipending + IRQ_BYTE(irq_num) ; \
15637ed4 RG	196	popl %es ; \
	197	popl %ds ; \
	198	popal ; \
	199	addl $4+4,%esp ; \
	200	iret
	201
	202	/*
	203	* vector.h has defined a macro 'BUILD_VECTORS' containing a big list of info
	204	* about vectors, including a submacro 'BUILD_VECTOR' that operates on the
	205	* info about each vector. We redefine 'BUILD_VECTOR' to expand the info
	206	* in different ways. Here we expand it to a list of interrupt handlers.
	207	* This order is of course unimportant. Elsewhere we expand it to inline
	208	* linear search code for which the order is a little more important and
	209	* concatenating the code with no holes is very important.
	210	*
	211	* XXX - now there is BUILD_FAST_VECTOR as well as BUILD_VECTOR.
	212	*
	213	* The info consists of the following items for each vector:
	214	*
	215	* name (identifier): name of the vector; used to build labels
	216	* unit (expression): unit number to call the device driver with
	217	* irq_num (number): number of the IRQ to handled (0-15)
	218	* id_num (number): uniq numeric id for handler (assigned by config)
	219	* mask (blank-ident): priority mask used
	220	* handler (blank-ident): interrupt handler to call
	221	* icu_num (number): (1 + irq_num / 8) converted for label building
	222	* icu_enables (number): 1 for icu_num == 1, 1_AND_2 for icu_num == 2
	223	* reg (blank-ident): al for icu_num == 1, ah for icu_num == 2
	224	*
	225	* 'irq_num' is converted in several ways at config time to get around
	226	* limitations in cpp. The macros have blanks after commas iff they would
	227	* not mess up identifiers and numbers.
	228	*/
	229
	230	#undef BUILD_FAST_VECTOR
	231	#define BUILD_FAST_VECTOR(name, unit, irq_num, id_num, mask, handler, \
	232	icu_num, icu_enables, reg) \
	233	.globl handler ; \
	234	.text ; \
	235	.globl _V/**/name ; \
	236	SUPERALIGN_TEXT ; \
	237	_V/**/name: ; \
1c7454b0	238	FAST_INTR(unit, irq_num,id_num, handler, ENABLE_ICU/**/icu_enables)
15637ed4 RG	239
	240	#undef BUILD_VECTOR
	241	#define BUILD_VECTOR(name, unit, irq_num, id_num, mask, handler, \
	242	icu_num, icu_enables, reg) \
	243	.globl handler ; \
	244	.text ; \
	245	.globl _V/**/name ; \
	246	SUPERALIGN_TEXT ; \
	247	_V/**/name: ; \
1c7454b0	248	INTR(unit,irq_num, id_num, mask, handler, IO_ICU/**/icu_num, \
15637ed4 RG	249	ENABLE_ICU/**/icu_enables, reg,)
15637ed4 RG	250
1c7454b0	251	MCOUNT_LABEL(bintr)
15637ed4 RG	252	BUILD_VECTORS
	253
	254	/* hardware interrupt catcher (IDT 32 - 47) */
	255	.globl _isa_strayintr
	256
	257	#define STRAYINTR(irq_num, icu_num, icu_enables, reg) \
	258	IDTVEC(intr/**/irq_num) ; \
1c7454b0	259	INTR(irq_num,irq_num,irq_num, _high_imask, _isa_strayintr, \
15637ed4 RG	260	IO_ICU//icu_num, ENABLE_ICU//icu_enables, reg,stray)
	261
	262	/*
	263	* XXX - the mask (1 << 2) == IRQ_SLAVE will be generated for IRQ 2, instead
	264	* of the mask IRQ2 (defined as IRQ9 == (1 << 9)). But IRQ 2 "can't happen".
	265	* In fact, all stray interrupts "can't happen" except for bugs. The
	266	* "stray" IRQ 7 is documented behaviour of the 8259. It happens when there
	267	* is a glitch on any of its interrupt inputs. Does it really interrupt when
	268	* IRQ 7 is masked?
	269	*
	270	* XXX - unpend doesn't work for these, it sends them to the real handler.
	271	*
	272	* XXX - the race bug during initialization may be because I changed the
	273	* order of switching from the stray to the real interrupt handler to before
	274	* enabling interrupts. The old order looked unsafe but maybe it is OK with
	275	* the stray interrupt handler installed. But these handlers only reduce
	276	* the window of vulnerability - it is still open at the end of
	277	* isa_configure().
	278	*
	279	* XXX - many comments are stale.
	280	*/
	281
	282	STRAYINTR(0,1,1, al)
	283	STRAYINTR(1,1,1, al)
	284	STRAYINTR(2,1,1, al)
	285	STRAYINTR(3,1,1, al)
	286	STRAYINTR(4,1,1, al)
	287	STRAYINTR(5,1,1, al)
	288	STRAYINTR(6,1,1, al)
1c7454b0	289	STRAYINTR(7,1,1, al)
15637ed4 RG	290	STRAYINTR(8,2,1_AND_2, ah)
	291	STRAYINTR(9,2,1_AND_2, ah)
	292	STRAYINTR(10,2,1_AND_2, ah)
	293	STRAYINTR(11,2,1_AND_2, ah)
	294	STRAYINTR(12,2,1_AND_2, ah)
	295	STRAYINTR(13,2,1_AND_2, ah)
	296	STRAYINTR(14,2,1_AND_2, ah)
	297	STRAYINTR(15,2,1_AND_2, ah)
15637ed4 RG	298	#if 0
	299	INTRSTRAY(255, _highmask, 255) ; call _isa_strayintr ; INTREXIT2
	300	#endif
1c7454b0 DG	301	MCOUNT_LABEL(eintr)
1c7454b0 DG	302
15637ed4 RG	303	/*
	304	* These are the interrupt counters, I moved them here from icu.s so that
	305	* they are with the name table. rgrimes
	306	*
	307	* There are now lots of counters, this has been redone to work with
	308	* Bruce Evans intr-0.1 code, which I modified some more to make it all
	309	* work with vmstat.
	310	*/
	311	.data
1c7454b0 DG	312	ihandlers: /* addresses of interrupt handlers */
	313	.space NHWI4 / actually resumption addresses for HWI's */
	314	.long swi_tty, swi_net, 0, 0, 0, 0, 0, 0
	315	.long 0, 0, 0, 0, 0, 0, swi_clock, swi_ast
	316	imasks: /* masks for interrupt handlers */
	317	.space NHWI4 / padding; HWI masks are elsewhere */
	318	.long SWI_TTY_MASK, SWI_NET_MASK, 0, 0, 0, 0, 0, 0
	319	.long 0, 0, 0, 0, 0, 0, SWI_CLOCK_MASK, SWI_AST_MASK
	320
15637ed4 RG	321	.globl _intrcnt
	322	_intrcnt: /* used by vmstat to calc size of table */
	323	.globl _intrcnt_bad7
	324	_intrcnt_bad7: .space 4 /* glitches on irq 7 */
	325	.globl _intrcnt_bad15
	326	_intrcnt_bad15: .space 4 /* glitches on irq 15 */
	327	.globl _intrcnt_stray
	328	_intrcnt_stray: .space 4 /* total count of stray interrupts */
	329	.globl _intrcnt_actv
	330	_intrcnt_actv: .space NR_REAL_INT_HANDLERS * 4 /* active interrupts */
74c19e61 RG	331	.globl _eintrcnt
74c19e61 RG	332	_eintrcnt: /* used by vmstat to calc size of table */
15637ed4 RG	333
	334	/*
	335	* Build the interrupt name table for vmstat
	336	*/
	337
	338	#undef BUILD_FAST_VECTOR
	339	#define BUILD_FAST_VECTOR BUILD_VECTOR
	340
	341	#undef BUILD_VECTOR
	342	#define BUILD_VECTOR(name, unit, irq_num, id_num, mask, handler, \
	343	icu_num, icu_enables, reg) \
	344	.ascii "name irq" ; \
	345	.asciz "irq_num"
	346	/*
1c7454b0 DG	347	* XXX - use the __STRING and __CONCAT macros from <sys/cdefs.h> to stringize
	348	* and concatenate names above and elsewhere. Note that __CONCAT doesn't
	349	* work when nested.
15637ed4 RG	350	*/
	351
	352	.text
	353	.globl _intrnames, _eintrnames
	354	_intrnames:
	355	BUILD_VECTOR(bad,,7,,,,,,)
	356	BUILD_VECTOR(bad,,15,,,,,,)
	357	BUILD_VECTOR(stray,,,,,,,,)
	358	BUILD_VECTORS
	359
74c19e61	360	_eintrnames: