projects / unix-history / blame
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|---|---|---|
| 42efdbd9 CT |
1 | /* |
| 2 | * Copyright (c) 1992 The Regents of the University of California. | |
| 3 | * All rights reserved. | |
| 4 | * | |
| 5 | * This software was developed by the Computer Systems Engineering group | |
| 6 | * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and | |
| 7 | * contributed to Berkeley. | |
| 8 | * | |
| b480239a KB |
9 | * All advertising materials mentioning features or use of this software |
| 10 | * must display the following acknowledgement: | |
| 11 | * This product includes software developed by the University of | |
| 062bb472 | 12 | * California, Lawrence Berkeley Laboratory. |
| b480239a | 13 | * |
| 42efdbd9 CT |
14 | * %sccs.include.redist.c% |
| 15 | * | |
| feb2ac6b | 16 | * @(#)ctlreg.h 7.4 (Berkeley) %G% |
| 42efdbd9 | 17 | * |
| feb2ac6b | 18 | * from: $Header: ctlreg.h,v 1.6 93/04/27 14:29:07 torek Exp $ |
| 42efdbd9 CT |
19 | */ |
| 20 | ||
| 21 | /* | |
| 22 | * Sun-4 (sort of) and 4c (Campus, i.e., SparcStation) control registers | |
| 23 | * (includes address space definitions and registers in control space). | |
| 24 | * | |
| 25 | * Address space identifiers are 8 bits (0 through 255), but we | |
| 26 | * only use four of them. | |
| 27 | */ | |
| 28 | ||
| 29 | /* 0 unused */ | |
| 30 | /* 1 unused */ | |
| 31 | #define ASI_CONTROL 2 /* cache enable, context reg, etc */ | |
| 32 | #define ASI_SEGMAP 3 /* segment maps (so we can reach each pmeg) */ | |
| 33 | #define ASI_PTE 4 /* PTE space (pmegs) */ | |
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34 | #define ASI_HWFLUSHSEG 5 /* hardware assisted version of FLUSHSEG */ |
| 35 | #define ASI_HWFLUSHPG 6 /* hardware assisted version of FLUSHPG */ | |
| 36 | #define ASI_HWFLUSHCTX 7 /* hardware assisted version of FLUSHCTX */ | |
| 42efdbd9 CT |
37 | #define ASI_USERI 8 /* I-space (user) */ |
| 38 | #define ASI_KERNELI 9 /* I-space (kernel) */ | |
| 39 | #define ASI_USERD 10 /* D-space (user) */ | |
| 40 | #define ASI_KERNELD 11 /* D-space (kernel) */ | |
| 41 | #define ASI_FLUSHSEG 12 /* causes hardware to flush cache segment */ | |
| 42 | #define ASI_FLUSHPG 13 /* causes hardware to flush cache page */ | |
| 43 | #define ASI_FLUSHCTX 14 /* causes hardware to flush cache context */ | |
| 44 | #ifdef SUN4 | |
| 45 | #define ASI_DCACHE 15 /* flush data cache; not used on 4c */ | |
| 46 | #endif | |
| 47 | /* 16 through 255 unused (and probably wrap, but who cares?) */ | |
| 48 | ||
| 49 | /* registers in the control space */ | |
| 50 | #define AC_CONTEXT 0x30000000 /* context register (byte) */ | |
| 51 | #define AC_SYSENABLE 0x40000000 /* system enable register (byte) */ | |
| 52 | #define AC_CACHETAGS 0x80000000 /* cache tag base address */ | |
| 53 | #define AC_SERIAL 0xf0000000 /* special serial port sneakiness */ | |
| 54 | /* AC_SERIAL is not used in the kernel (it is for the PROM) */ | |
| 55 | ||
| 56 | #ifdef SUN4 | |
| 57 | #define AC_DVMA_ENABLE 0x50000000 /* enable user dvma */ | |
| 58 | #define AC_BUS_ERR 0x60000000 /* bus error register */ | |
| 59 | #define AC_DIAG_REG 0x70000000 /* diagnostic reg */ | |
| 60 | #define AC_DVMA_MAP 0xd0000000 /* user dvma map entries */ | |
| 61 | #endif | |
| 62 | ||
| 63 | #ifdef SUN4C | |
| 64 | #define AC_SYNC_ERR 0x60000000 /* sync (memory) error reg */ | |
| 65 | #define AC_SYNC_VA 0x60000004 /* sync error virtual addr */ | |
| 66 | #define AC_ASYNC_ERR 0x60000008 /* async error reg */ | |
| 67 | #define AC_ASYNC_VA 0x6000000c /* async error virtual addr */ | |
| 68 | #define AC_CACHEDATA 0x90000000 /* cached data */ | |
| 69 | ||
| 70 | /* | |
| 71 | * Bits in sync error register. Reading the register clears these; | |
| 72 | * otherwise they accumulate. The error(s) occurred at the virtual | |
| 73 | * address stored in the sync error address register, and may have | |
| 74 | * been due to, e.g., what would usually be called a page fault. | |
| 75 | * Worse, the bits accumulate during instruction prefetch, so | |
| 76 | * various bits can be on that should be off. | |
| 77 | */ | |
| 78 | #define SER_WRITE 0x8000 /* error occurred during write */ | |
| 79 | #define SER_INVAL 0x80 /* PTE had PG_V off */ | |
| 80 | #define SER_PROT 0x40 /* operation violated PTE prot */ | |
| 81 | #define SER_TIMEOUT 0x20 /* bus timeout (non-existent mem) */ | |
| 82 | #define SER_SBUSERR 0x10 /* S-Bus bus error */ | |
| 83 | #define SER_MEMERR 0x08 /* memory ecc/parity error */ | |
| 84 | #define SER_SZERR 0x02 /* size error, whatever that is */ | |
| 85 | #define SER_WATCHDOG 0x01 /* watchdog reset (never see this) */ | |
| 86 | ||
| 87 | #define SER_BITS \ | |
| 88 | "\20\20WRITE\10INVAL\7PROT\6TIMEOUT\5SBUSERR\4MEMERR\2SZERR\1WATCHDOG" | |
| 89 | ||
| 90 | /* | |
| 91 | * Bits in async error register (errors from DVMA or Sun-4 cache | |
| 92 | * writeback). The corresponding bit is also set in the sync error reg. | |
| 93 | * | |
| 94 | * A writeback invalid error means there is a bug in the PTE manager. | |
| 95 | * | |
| 96 | * The word is that the async error register does not work right. | |
| 97 | */ | |
| 98 | #define AER_WBINVAL 0x80 /* writeback found PTE without PG_V */ | |
| 99 | #define AER_TIMEOUT 0x20 /* bus timeout */ | |
| 100 | #define AER_DVMAERR 0x10 /* bus error during DVMA */ | |
| 101 | ||
| 102 | #define AER_BITS "\20\10WBINVAL\6TIMEOUT\5DVMAERR" | |
| 103 | ||
| 104 | #endif /* SUN4C */ | |
| 105 | ||
| 106 | /* | |
| 107 | * Bits in system enable register. | |
| 108 | */ | |
| 109 | #define SYSEN_DVMA 0x20 /* enable dvma */ | |
| 110 | #define SYSEN_CACHE 0x10 /* enable cache */ | |
| 111 | #define SYSEN_RESET 0x04 /* reset the hardware */ |