[unix-history] / usr / src / sys / i386 / isa / icu.h

/*-
 * Copyright (c) 1990 The Regents of the University of California.
 * All rights reserved.
 *
 * This code is derived from software contributed to Berkeley by
 * William Jolitz.
 *
 * %sccs.include.redist.c%
 *
 *	@(#)icu.h	5.6 (Berkeley) %G%
 */

/*
 * AT/386 Interrupt Control constants
 * W. Jolitz 8/89
 */

#ifndef	__ICU__
#define	__ICU__

#ifndef	LOCORE

/*
 * Interrupt "level" mechanism variables, masks, and macros
 */
extern	unsigned short	imen;	/* interrupt mask enable */
extern	unsigned short	cpl;	/* current priority level mask */

extern	unsigned short highmask; /* group of interrupts masked with splhigh() */
extern	unsigned short ttymask; /* group of interrupts masked with spltty() */
extern	unsigned short biomask; /* group of interrupts masked with splbio() */
extern	unsigned short netmask; /* group of interrupts masked with splimp() */

#define	INTREN(s)	imen &= ~(s)
#define	INTRDIS(s)	imen |= (s)
#define	INTRMASK(msk,s)	msk |= (s)

#else

/*
 * Macro's for interrupt level priority masks (used in interrupt vector entry)
 */

/* Mask a group of interrupts atomically */
#define	INTR(unit,mask,offst) \
	pushl	$0 ; \
	pushl	$ T_ASTFLT ; \
	pushal ; \
	push	%ds ; \
	push	%es ; \
	movw	$0x10, %ax ; \
	movw	%ax, %ds ; \
	movw	%ax,%es ; \
	incl	_cnt+V_INTR ; \
	incl	_isa_intr + offst * 4 ; \
	movzwl	_cpl,%eax ; \
	pushl	%eax ; \
	pushl	$ unit ; \
	orw	mask ,%ax ; \
	movw	%ax,_cpl ; \
	orw	_imen,%ax ; \
	NOP ; \
	outb	%al,$ IO_ICU1+1 ; \
	NOP ; \
	movb	%ah,%al ; \
	outb	%al,$ IO_ICU2+1	; \
	NOP	; \
	inb	$0x84,%al ; \
	sti

/* Interrupt vector exit macros */

/* First eight interrupts (ICU1) */
#define	INTREXIT1	\
	movb	$0x20,%al ; \
	outb	%al,$ IO_ICU1 ; \
	jmp	doreti

/* Second eight interrupts (ICU2) */
#define	INTREXIT2	\
	movb	$0x20,%al ; \
	outb	%al,$ IO_ICU1 ; \
	outb	%al,$ IO_ICU2 ; \
	jmp	doreti

#endif

/*
 * Interrupt enable bits -- in order of priority
 */
#define	IRQ0		0x0001		/* highest priority - timer */
#define	IRQ1		0x0002
#define	IRQ_SLAVE	0x0004
#define	IRQ8		0x0100
#define	IRQ9		0x0200
#define	IRQ2		IRQ9
#define	IRQ10		0x0400
#define	IRQ11		0x0800
#define	IRQ12		0x1000
#define	IRQ13		0x2000
#define	IRQ14		0x4000
#define	IRQ15		0x8000
#define	IRQ3		0x0008
#define	IRQ4		0x0010
#define	IRQ5		0x0020
#define	IRQ6		0x0040
#define	IRQ7		0x0080		/* lowest - parallel printer */

/*
 * Interrupt Control offset into Interrupt descriptor table (IDT)
 */
#define	ICU_OFFSET	32		/* 0-31 are processor exceptions */
#define	ICU_LEN		16		/* 32-47 are ISA interrupts */

#endif	__ICU__
Commit	Line	Data
d8b6dae7 WN	1	/*-
	2	* Copyright (c) 1990 The Regents of the University of California.
	3	* All rights reserved.
	4	*
	5	* This code is derived from software contributed to Berkeley by
	6	* William Jolitz.
	7	*
d0d290ad	8	* %sccs.include.redist.c%
d8b6dae7	9	*
d0d290ad	10	* @(#)icu.h 5.6 (Berkeley) %G%
d8b6dae7 WN	11	*/
	12
	13	/*
	14	* AT/386 Interrupt Control constants
	15	* W. Jolitz 8/89
	16	*/
	17
78c0d757 DA	18	#ifndef __ICU__
	19	#define __ICU__
	20
d8b6dae7	21	#ifndef LOCORE
4686adac BJ	22
	23	/*
	24	* Interrupt "level" mechanism variables, masks, and macros
	25	*/
d8b6dae7	26	extern unsigned short imen; /* interrupt mask enable */
4686adac	27	extern unsigned short cpl; /* current priority level mask */
d8b6dae7	28
4686adac BJ	29	extern unsigned short highmask; /* group of interrupts masked with splhigh() */
	30	extern unsigned short ttymask; /* group of interrupts masked with spltty() */
	31	extern unsigned short biomask; /* group of interrupts masked with splbio() */
	32	extern unsigned short netmask; /* group of interrupts masked with splimp() */
78c0d757	33
d8b6dae7 WN	34	#define INTREN(s) imen &= ~(s)
d8b6dae7 WN	35	#define INTRDIS(s) imen \|= (s)
0018230c	36	#define INTRMASK(msk,s) msk \|= (s)
4686adac BJ	37
	38	#else
	39
	40	/*
	41	* Macro's for interrupt level priority masks (used in interrupt vector entry)
	42	*/
	43
4686adac	44	/* Mask a group of interrupts atomically */
d0d290ad	45	#define INTR(unit,mask,offst) \
4686adac BJ	46	pushl $0 ; \
	47	pushl $ T_ASTFLT ; \
	48	pushal ; \
	49	push %ds ; \
	50	push %es ; \
	51	movw $0x10, %ax ; \
	52	movw %ax, %ds ; \
	53	movw %ax,%es ; \
	54	incl _cnt+V_INTR ; \
d0d290ad	55	incl _isa_intr + offst * 4 ; \
4686adac BJ	56	movzwl _cpl,%eax ; \
4686adac BJ	57	pushl %eax ; \
d0d290ad WN	58	pushl $ unit ; \
d0d290ad WN	59	orw mask ,%ax ; \
4686adac BJ	60	movw %ax,_cpl ; \
	61	orw _imen,%ax ; \
	62	NOP ; \
	63	outb %al,$ IO_ICU1+1 ; \
	64	NOP ; \
	65	movb %ah,%al ; \
	66	outb %al,$ IO_ICU2+1 ; \
	67	NOP ; \
d0d290ad	68	inb $0x84,%al ; \
4686adac BJ	69	sti
	70
	71	/* Interrupt vector exit macros */
	72
	73	/* First eight interrupts (ICU1) */
d0d290ad	74	#define INTREXIT1 \
4686adac BJ	75	movb $0x20,%al ; \
	76	outb %al,$ IO_ICU1 ; \
	77	jmp doreti
	78
	79	/* Second eight interrupts (ICU2) */
d0d290ad	80	#define INTREXIT2 \
4686adac BJ	81	movb $0x20,%al ; \
	82	outb %al,$ IO_ICU1 ; \
	83	outb %al,$ IO_ICU2 ; \
	84	jmp doreti
	85
d8b6dae7 WN	86	#endif
d8b6dae7 WN	87
4686adac BJ	88	/*
	89	* Interrupt enable bits -- in order of priority
	90	*/
0018230c BJ	91	#define IRQ0 0x0001 /* highest priority - timer */
	92	#define IRQ1 0x0002
	93	#define IRQ_SLAVE 0x0004
	94	#define IRQ8 0x0100
	95	#define IRQ9 0x0200
	96	#define IRQ2 IRQ9
	97	#define IRQ10 0x0400
	98	#define IRQ11 0x0800
	99	#define IRQ12 0x1000
	100	#define IRQ13 0x2000
	101	#define IRQ14 0x4000
	102	#define IRQ15 0x8000
	103	#define IRQ3 0x0008
	104	#define IRQ4 0x0010
	105	#define IRQ5 0x0020
	106	#define IRQ6 0x0040
	107	#define IRQ7 0x0080 /* lowest - parallel printer */
d8b6dae7	108
4686adac BJ	109	/*
	110	* Interrupt Control offset into Interrupt descriptor table (IDT)
	111	*/
	112	#define ICU_OFFSET 32 /* 0-31 are processor exceptions */
	113	#define ICU_LEN 16 /* 32-47 are ISA interrupts */
	114
78c0d757	115	#endif __ICU__