projects / unix-history / blame
| Commit | Line | Data |
|---|---|---|
| b2ffc3a6 DG |
1 | /* Copyright (c) 1994, Matthew E. Kimmel. Permission is hereby granted |
| 2 | * to use, copy, modify and distribute this software provided that both | |
| 3 | * the copyright notice and this permission notice appear in all copies | |
| 4 | * of the software, derivative works or modified versions, and any | |
| 5 | * portions thereof. | |
| 6 | */ | |
| 7 | /* 3COM Etherlink 3C501 Register Definitions */ | |
| 8 | ||
| 9 | /* I/O Ports */ | |
| 10 | #define EL_RXS 0x6 /* Receive status register */ | |
| 11 | #define EL_RXC 0x6 /* Receive command register */ | |
| 12 | #define EL_TXS 0x7 /* Transmit status register */ | |
| 13 | #define EL_TXC 0x7 /* Transmit command register */ | |
| 14 | #define EL_GPBL 0x8 /* GP buffer ptr low byte */ | |
| 15 | #define EL_GPBH 0x9 /* GP buffer ptr high byte */ | |
| 16 | #define EL_RBL 0xa /* Receive buffer ptr low byte */ | |
| 17 | #define EL_RBC 0xa /* Receive buffer clear */ | |
| 18 | #define EL_RBH 0xb /* Receive buffer ptr high byte */ | |
| 19 | #define EL_EAW 0xc /* Ethernet address window */ | |
| 20 | #define EL_AS 0xe /* Auxillary status register */ | |
| 21 | #define EL_AC 0xe /* Auxillary command register */ | |
| 22 | #define EL_BUF 0xf /* Data buffer */ | |
| 23 | ||
| 24 | /* Receive status register bits */ | |
| 25 | #define EL_RXS_OFLOW 0x01 /* Overflow error */ | |
| 26 | #define EL_RXS_FCS 0x02 /* FCS error */ | |
| 27 | #define EL_RXS_DRIB 0x04 /* Dribble error */ | |
| 28 | #define EL_RXS_SHORT 0x08 /* Short frame */ | |
| 29 | #define EL_RXS_NOFLOW 0x10 /* No overflow */ | |
| 30 | #define EL_RXS_GOOD 0x20 /* Received good frame */ | |
| 31 | #define EL_RXS_STALE 0x80 /* Stale receive status */ | |
| 32 | ||
| 33 | /* Receive command register bits */ | |
| 34 | #define EL_RXC_DISABLE 0x00 /* Receiver disabled */ | |
| 35 | #define EL_RXC_DOFLOW 0x01 /* Detect overflow */ | |
| 36 | #define EL_RXC_DFCS 0x02 /* Detect FCS errs */ | |
| 37 | #define EL_RXC_DDRIB 0x04 /* Detect dribble errors */ | |
| 38 | #define EL_RXC_DSHORT 0x08 /* Detect short frames */ | |
| 39 | #define EL_RXC_DNOFLOW 0x10 /* Detect frames w/o overflow ??? */ | |
| 40 | #define EL_RXC_AGF 0x20 /* Accept Good Frames */ | |
| 41 | #define EL_RXC_PROMISC 0x40 /* Promiscuous mode */ | |
| 42 | #define EL_RXC_ABROAD 0x80 /* Accept address, broadcast */ | |
| 43 | #define EL_RXC_AMULTI 0xc0 /* Accept address, multicast */ | |
| 44 | ||
| 45 | /* Transmit status register bits */ | |
| 46 | #define EL_TXS_UFLOW 0x01 /* Underflow */ | |
| 47 | #define EL_TXS_COLL 0x02 /* Collision */ | |
| 48 | #define EL_TXS_COLL16 0x04 /* Collision 16 */ | |
| 49 | #define EL_TXS_READY 0x08 /* Ready for new frame */ | |
| 50 | ||
| 51 | /* Transmit command register bits */ | |
| 52 | #define EL_TXC_DUFLOW 0x01 /* Detect underflow */ | |
| 53 | #define EL_TXC_DCOLL 0x02 /* Detect collisions */ | |
| 54 | #define EL_TXC_DCOLL16 0x04 /* Detect collision 16 */ | |
| 55 | #define EL_TXC_DSUCCESS 0x08 /* Detect success */ | |
| 56 | ||
| 57 | /* Auxillary status register bits */ | |
| 58 | #define EL_AS_RXBUSY 0x01 /* Receive busy */ | |
| 59 | #define EL_AS_DMADONE 0x10 /* DMA finished */ | |
| 60 | #define EL_AS_TXBUSY 0x80 /* Transmit busy */ | |
| 61 | ||
| 62 | /* Auxillary command register bits */ | |
| 63 | #define EL_AC_HOST 0x00 /* System bus can access buffer */ | |
| 64 | #define EL_AC_IRQE 0x01 /* IRQ enable */ | |
| 65 | #define EL_AC_TXBAD 0x02 /* Transmit frames with bad FCS */ | |
| 66 | #define EL_AC_TXFRX 0x04 /* Transmit followed by receive */ | |
| 67 | #define EL_AC_RX 0x08 /* Receive */ | |
| 68 | #define EL_AC_LB 0x0c /* Loopback */ | |
| 69 | #define EL_AC_DRQ 0x20 /* DMA request */ | |
| 70 | #define EL_AC_RIDE 0x40 /* DRQ and IRQ enabled */ | |
| 71 | #define EL_AC_RESET 0x80 /* Reset */ | |
| 72 | ||
| 73 | /* Packet buffer size */ | |
| 74 | #define EL_BUFSIZ 2048 | |
| 75 | ||
| 76 | #define ETHER_ADDR_LEN 6 |