projects / unix-history / blame
| Commit | Line | Data |
|---|---|---|
| 07f112c7 ZAL |
1 | ; @(#)national.s 1.1 (ucb.elefunt) %G% |
| 2 | ; | |
| 3 | ; subroutines | |
| 4 | ; add_ulp(x) ... return x+ulp | |
| 5 | ; sub_ulp(x) ... return x-ulp | |
| 6 | ; swapENI(i) ... swap inexact enable bit with i | |
| 7 | ; swapINX(i) ... swap inexact flag bit with i | |
| 8 | ; swapRM(i) ... swap rounding mode with i | |
| 9 | ; | |
| 10 | ||
| 11 | ; add_ulp(x): | |
| 12 | ; add one ulp to a floating point number | |
| 13 | .align 2 | |
| 14 | .globl _add_ulp | |
| 15 | _add_ulp: | |
| 16 | movd 4(sp),r0 | |
| 17 | movd 8(sp),r1 | |
| 18 | addd 1,r0 | |
| 19 | addcd 0,r1 | |
| 20 | movd r0,4(sp) | |
| 21 | movd r1,8(sp) | |
| 22 | movl 4(sp),f0 | |
| 23 | ret 0 | |
| 24 | ||
| 25 | ; sub_ulp(x) | |
| 26 | ; subtract one ulp from a floating point number | |
| 27 | .align 2 | |
| 28 | .globl _sub_ulp | |
| 29 | _sub_ulp: | |
| 30 | movd 4(sp),r0 | |
| 31 | movd 8(sp),r1 | |
| 32 | subd 1,r0 | |
| 33 | subcd 0,r1 | |
| 34 | movd r0,4(sp) | |
| 35 | movd r1,8(sp) | |
| 36 | movl 4(sp),f0 | |
| 37 | ret 0 | |
| 38 | ||
| 39 | ; swapENI(i) | |
| 40 | ; swap the inexact enable bit | |
| 41 | .text | |
| 42 | .align 2 | |
| 43 | .globl _swapENI | |
| 44 | _swapENI: | |
| 45 | movd 4(sp),r1 | |
| 46 | sfsr r0 | |
| 47 | movd r0,r2 | |
| 48 | bicd [5],r2 | |
| 49 | andd [0],r1 | |
| 50 | ashd 5,r1 | |
| 51 | ord r1,r2 | |
| 52 | lfsr r2 | |
| 53 | ashd -5,r0 | |
| 54 | andd [0],r0 | |
| 55 | ret 0 | |
| 56 | ||
| 57 | ; swapINX(i) | |
| 58 | ; swap the inexact flag | |
| 59 | .align 2 | |
| 60 | .globl _swapINX | |
| 61 | _swapINX: | |
| 62 | movd 4(sp),r1 | |
| 63 | sfsr r0 | |
| 64 | movd r0,r2 | |
| 65 | bicd [6],r2 | |
| 66 | andd [0],r1 | |
| 67 | ashd 6,r1 | |
| 68 | ord r1,r2 | |
| 69 | lfsr r2 | |
| 70 | ashd -6,r0 | |
| 71 | andd [0],r0 | |
| 72 | ret 0 | |
| 73 | ||
| 74 | ; swapRM(i) | |
| 75 | ; swap the rounding mode | |
| 76 | .align 2 | |
| 77 | .globl _swapRM | |
| 78 | _swapRM: | |
| 79 | movd 4(sp),r1 | |
| 80 | sfsr r0 | |
| 81 | movd r0,r2 | |
| 82 | bicd [7,8],r2 | |
| 83 | andd [0,1],r1 | |
| 84 | ashd 7,r1 | |
| 85 | ord r1,r2 | |
| 86 | lfsr r2 | |
| 87 | ashd -7,r0 | |
| 88 | andd [0,1],r0 | |
| 89 | ret 0 |