Commit | Line | Data |
---|---|---|
4fce3bf9 | 1 | /* if_ilreg.h 4.3 82/11/13 */ |
ac5a9f24 BF |
2 | |
3 | /* | |
4 | * Interlan Ethernet Communications Controller interface | |
5 | */ | |
6 | struct ildevice { | |
7 | short il_csr; /* Command and Status Register */ | |
8 | short il_bar; /* Buffer Address Register */ | |
9 | short il_bcr; /* Byte Count Register */ | |
10 | }; | |
11 | ||
12 | /* | |
13 | * Command and status bits | |
14 | */ | |
e80bb6f4 | 15 | #define IL_EUA 0xc000 /* Extended Unibus Address */ |
ac5a9f24 BF |
16 | #define IL_CMD 0x3f00 /* Command Function Code */ |
17 | #define IL_CDONE 0x0080 /* Command Done */ | |
18 | #define IL_CIE 0x0040 /* Command Interrupt Enable */ | |
19 | #define IL_RDONE 0x0020 /* Receive DMA Done */ | |
20 | #define IL_RIE 0x0010 /* Receive Interrupt Enable */ | |
21 | #define IL_STATUS 0x000f /* Command Status Code */ | |
22 | ||
e80bb6f4 | 23 | #define IL_BITS "\20\10CDONE\7CIE\6RDONE\5RIE" |
ac5a9f24 | 24 | |
e80bb6f4 | 25 | /* command definitions */ |
ac5a9f24 BF |
26 | #define ILC_MLPBAK 0x0100 /* Set Module Interface Loopback Mode */ |
27 | #define ILC_ILPBAK 0x0200 /* Set Internal Loopback Mode */ | |
28 | #define ILC_CLPBAK 0x0300 /* Clear Loopback Mode */ | |
29 | #define ILC_PRMSC 0x0400 /* Set Promiscuous Receive Mode */ | |
30 | #define ILC_CLPRMSC 0x0500 /* Clear Promiscuous Receive Mode */ | |
31 | #define ILC_RCVERR 0x0600 /* Set Receive-On-Error Bit */ | |
32 | #define ILC_CRCVERR 0x0700 /* Clear Receive-On-Error Bit */ | |
33 | #define ILC_OFFLINE 0x0800 /* Go Offline */ | |
34 | #define ILC_ONLINE 0x0900 /* Go Online */ | |
35 | #define ILC_DIAG 0x0a00 /* Run On-board Diagnostics */ | |
4fce3bf9 SL |
36 | #define ILC_ISA 0x0d00 /* Set Insert Source Address Mode */ |
37 | #define ILC_CISA 0x0e00 /* Clear Insert Source Address Mode */ | |
38 | #define ILC_DEFPA 0x0f00 /* Set Physical Address to Default */ | |
39 | #define ILC_ALLMC 0x1000 /* Set Receive All Multicast Packets */ | |
40 | #define ILC_CALLMC 0x1100 /* Clear Receive All Multicast */ | |
ac5a9f24 BF |
41 | #define ILC_STAT 0x1800 /* Report and Reset Statistics */ |
42 | #define ILC_DELAYS 0x1900 /* Report Collision Delay Times */ | |
43 | #define ILC_RCV 0x2000 /* Supply Receive Buffer */ | |
44 | #define ILC_LDXMIT 0x2800 /* Load Transmit Data */ | |
45 | #define ILC_XMIT 0x2900 /* Load Transmit Data and Send */ | |
46 | #define ILC_LDGRPS 0x2a00 /* Load Group Addresses */ | |
47 | #define ILC_RMGRPS 0x2b00 /* Delete Group Addresses */ | |
4fce3bf9 | 48 | #define ILC_LDPA 0x2c00 /* Load Physical Address */ |
ac5a9f24 BF |
49 | #define ILC_FLUSH 0x3000 /* Flush Receive BAR/BCR Queue */ |
50 | #define ILC_RESET 0x3f00 /* Reset */ | |
51 | ||
52 | /* | |
e80bb6f4 | 53 | * Error codes found in the status bits of the csr. |
ac5a9f24 | 54 | */ |
e80bb6f4 SL |
55 | #define ILERR_SUCCESS 0 /* command successful */ |
56 | #define ILERR_RETRIES 1 /* " " with retries */ | |
57 | #define ILERR_BADCMD 2 /* illegal command */ | |
58 | #define ILERR_INVCMD 3 /* invalid command */ | |
59 | #define ILERR_RECVERR 4 /* receiver error */ | |
60 | #define ILERR_BUFSIZ 5 /* buffer size too big */ | |
61 | #define ILERR_FRAMESIZ 6 /* frame size too small */ | |
62 | #define ILERR_COLLISIONS 8 /* excessive collisions */ | |
63 | #define ILERR_BUFALIGNMENT 10 /* buffer not word aligned */ | |
64 | #define ILERR_NXM 15 /* non-existent memory */ | |
65 | ||
66 | #define NILERRS 16 | |
67 | #ifdef ILERRS | |
68 | char *ilerrs[NILERRS] = { | |
69 | "success", /* 0 */ | |
70 | "success with retries", /* 1 */ | |
71 | "illegal command", /* 2 */ | |
72 | "inappropriate command", /* 3 */ | |
73 | "failure", /* 4 */ | |
74 | "buffer size exceeded", /* 5 */ | |
75 | "frame too small", /* 6 */ | |
76 | 0, /* 7 */ | |
77 | "excessive collisions", /* 8 */ | |
78 | 0, /* 9 */ | |
79 | "buffer alignment error", /* 10 */ | |
80 | 0, /* 11 */ | |
81 | 0, /* 12 */ | |
82 | 0, /* 13 */ | |
83 | 0, /* 14 */ | |
84 | "non-existent memory" /* 15 */ | |
ac5a9f24 | 85 | }; |
e80bb6f4 SL |
86 | #endif |
87 | ||
88 | /* | |
89 | * Diagnostics codes. | |
90 | */ | |
91 | #define ILDIAG_SUCCESS 0 /* no problems */ | |
92 | #define ILDIAG_CHKSUMERR 1 /* ROM/RAM checksum error */ | |
93 | #define ILDIAG_DMAERR 2 /* DMA not working */ | |
94 | #define ILDIAG_XMITERR 3 /* xmit circuitry failure */ | |
95 | #define ILDIAG_RECVERR 4 /* rcvr circuitry failure */ | |
96 | #define ILDIAG_LOOPBACK 5 /* loopback test failed */ | |
ac5a9f24 | 97 | |
e80bb6f4 SL |
98 | #define NILDIAGS 6 |
99 | #ifdef ILDIAGS | |
100 | char *ildiag[NILDIAGS] = { | |
101 | "success", /* 0 */ | |
102 | "checksum error", /* 1 */ | |
103 | "NM10 dma error", /* 2 */ | |
104 | "transmitter error", /* 3 */ | |
105 | "receiver error", /* 4 */ | |
106 | "loopback failure", /* 5 */ | |
ac5a9f24 | 107 | }; |
e80bb6f4 SL |
108 | #endif |
109 | ||
110 | /* | |
111 | * Frame status bits, returned in frame status byte | |
112 | * at the top of each received packet. | |
113 | */ | |
114 | #define ILFSTAT_C 0x1 /* CRC error */ | |
115 | #define ILFSTAT_A 0x2 /* alignment error */ | |
116 | #define ILFSTAT_L 0x4 /* 1+ frames lost just before */ |