projects / unix-history / blame
| Commit | Line | Data |
|---|---|---|
| d8b6dae7 WN |
1 | /*- |
| 2 | * Copyright (c) 1990 The Regents of the University of California. | |
| 3 | * All rights reserved. | |
| 4 | * | |
| 5 | * This code is derived from software contributed to Berkeley by | |
| 6 | * William Jolitz. | |
| 7 | * | |
| 8 | * %sccs.include.386.c% | |
| 9 | * | |
| 4686adac | 10 | * @(#)icu.h 5.4 (Berkeley) %G% |
| d8b6dae7 WN |
11 | */ |
| 12 | ||
| 13 | /* | |
| 14 | * AT/386 Interrupt Control constants | |
| 15 | * W. Jolitz 8/89 | |
| 16 | */ | |
| 17 | ||
| 78c0d757 DA |
18 | #ifndef __ICU__ |
| 19 | #define __ICU__ | |
| 20 | ||
| d8b6dae7 | 21 | #ifndef LOCORE |
| 4686adac BJ |
22 | |
| 23 | /* | |
| 24 | * Interrupt "level" mechanism variables, masks, and macros | |
| 25 | */ | |
| d8b6dae7 | 26 | extern unsigned short imen; /* interrupt mask enable */ |
| 4686adac | 27 | extern unsigned short cpl; /* current priority level mask */ |
| d8b6dae7 | 28 | |
| 4686adac BJ |
29 | extern unsigned short highmask; /* group of interrupts masked with splhigh() */ |
| 30 | extern unsigned short ttymask; /* group of interrupts masked with spltty() */ | |
| 31 | extern unsigned short biomask; /* group of interrupts masked with splbio() */ | |
| 32 | extern unsigned short netmask; /* group of interrupts masked with splimp() */ | |
| 78c0d757 | 33 | |
| d8b6dae7 WN |
34 | #define INTREN(s) imen &= ~(s) |
| 35 | #define INTRDIS(s) imen |= (s) | |
| 0018230c | 36 | #define INTRMASK(msk,s) msk |= (s) |
| 4686adac BJ |
37 | |
| 38 | #else | |
| 39 | ||
| 40 | /* | |
| 41 | * Macro's for interrupt level priority masks (used in interrupt vector entry) | |
| 42 | */ | |
| 43 | ||
| 44 | /* Just mask this interrupt only */ | |
| 45 | #define INTR(a) \ | |
| 46 | pushl $0 ; \ | |
| 47 | pushl $ T_ASTFLT ; \ | |
| 48 | pushal ; \ | |
| 49 | push %ds ; \ | |
| 50 | push %es ; \ | |
| 51 | movw $0x10, %ax ; \ | |
| 52 | movw %ax, %ds ; \ | |
| 53 | movw %ax,%es ; \ | |
| 54 | incl _cnt+V_INTR ; \ | |
| 55 | movzwl _cpl,%eax ; \ | |
| 56 | pushl %eax ; \ | |
| 57 | pushl $ a ; \ | |
| 58 | orw $ IRQ/**/a ,%ax ; \ | |
| 59 | movw %ax,_cpl ; \ | |
| 60 | orw _imen,%ax ; \ | |
| 61 | NOP ; \ | |
| 62 | outb %al,$ IO_ICU1+1 ; \ | |
| 63 | NOP ; \ | |
| 64 | movb %ah,%al ; \ | |
| 65 | outb %al,$ IO_ICU2+1 ; \ | |
| 66 | NOP ; \ | |
| 67 | sti | |
| 68 | ||
| 69 | /* Mask a group of interrupts atomically */ | |
| 70 | #define INTRN(a,b) \ | |
| 71 | pushl $0 ; \ | |
| 72 | pushl $ T_ASTFLT ; \ | |
| 73 | pushal ; \ | |
| 74 | push %ds ; \ | |
| 75 | push %es ; \ | |
| 76 | movw $0x10, %ax ; \ | |
| 77 | movw %ax, %ds ; \ | |
| 78 | movw %ax,%es ; \ | |
| 79 | incl _cnt+V_INTR ; \ | |
| 80 | movzwl _cpl,%eax ; \ | |
| 81 | pushl %eax ; \ | |
| 82 | pushl $ a ; \ | |
| 83 | orw $ IRQ/**/a ,%ax ; \ | |
| 84 | orw b ,%ax ; \ | |
| 85 | movw %ax,_cpl ; \ | |
| 86 | orw _imen,%ax ; \ | |
| 87 | NOP ; \ | |
| 88 | outb %al,$ IO_ICU1+1 ; \ | |
| 89 | NOP ; \ | |
| 90 | movb %ah,%al ; \ | |
| 91 | outb %al,$ IO_ICU2+1 ; \ | |
| 92 | NOP ; \ | |
| 93 | sti | |
| 94 | ||
| 95 | /* Interrupt vector exit macros */ | |
| 96 | ||
| 97 | /* First eight interrupts (ICU1) */ | |
| 98 | #define INTREXT1 \ | |
| 99 | movb $0x20,%al ; \ | |
| 100 | outb %al,$ IO_ICU1 ; \ | |
| 101 | jmp doreti | |
| 102 | ||
| 103 | /* Second eight interrupts (ICU2) */ | |
| 104 | #define INTREXT2 \ | |
| 105 | movb $0x20,%al ; \ | |
| 106 | outb %al,$ IO_ICU1 ; \ | |
| 107 | outb %al,$ IO_ICU2 ; \ | |
| 108 | jmp doreti | |
| 109 | ||
| d8b6dae7 WN |
110 | #endif |
| 111 | ||
| 4686adac BJ |
112 | /* |
| 113 | * Interrupt enable bits -- in order of priority | |
| 114 | */ | |
| 0018230c BJ |
115 | #define IRQ0 0x0001 /* highest priority - timer */ |
| 116 | #define IRQ1 0x0002 | |
| 117 | #define IRQ_SLAVE 0x0004 | |
| 118 | #define IRQ8 0x0100 | |
| 119 | #define IRQ9 0x0200 | |
| 120 | #define IRQ2 IRQ9 | |
| 121 | #define IRQ10 0x0400 | |
| 122 | #define IRQ11 0x0800 | |
| 123 | #define IRQ12 0x1000 | |
| 124 | #define IRQ13 0x2000 | |
| 125 | #define IRQ14 0x4000 | |
| 126 | #define IRQ15 0x8000 | |
| 127 | #define IRQ3 0x0008 | |
| 128 | #define IRQ4 0x0010 | |
| 129 | #define IRQ5 0x0020 | |
| 130 | #define IRQ6 0x0040 | |
| 131 | #define IRQ7 0x0080 /* lowest - parallel printer */ | |
| d8b6dae7 | 132 | |
| 4686adac BJ |
133 | /* |
| 134 | * Interrupt Control offset into Interrupt descriptor table (IDT) | |
| 135 | */ | |
| 136 | #define ICU_OFFSET 32 /* 0-31 are processor exceptions */ | |
| 137 | #define ICU_LEN 16 /* 32-47 are ISA interrupts */ | |
| 138 | ||
| 78c0d757 | 139 | #endif __ICU__ |