Commit | Line | Data |
---|---|---|
a8f16919 | 1 | /* mtpr.h 4.5 81/02/25 */ |
03f24a6b BJ |
2 | |
3 | /* | |
4 | * VAX processor register numbers | |
5 | */ | |
6 | ||
bbe0bf68 BJ |
7 | #define KSP 0x0 /* kernel stack pointer */ |
8 | #define ESP 0x1 /* exec stack pointer */ | |
9 | #define SSP 0x2 /* supervisor stack pointer */ | |
10 | #define USP 0x3 /* user stack pointer */ | |
11 | #define ISP 0x4 /* interrupt stack pointer */ | |
12 | #define P0BR 0x8 /* p0 base register */ | |
13 | #define P0LR 0x9 /* p0 length register */ | |
14 | #define P1BR 0xa /* p1 base register */ | |
15 | #define P1LR 0xb /* p1 length register */ | |
16 | #define SBR 0xc /* system segment base register */ | |
17 | #define SLR 0xd /* system segment length register */ | |
18 | #define PCBB 0x10 /* process control block base */ | |
19 | #define SCBB 0x11 /* system control block base */ | |
20 | #define IPL 0x12 /* interrupt priority level */ | |
21 | #define ASTLVL 0x13 /* async. system trap level */ | |
22 | #define SIRR 0x14 /* software interrupt request */ | |
23 | #define SISR 0x15 /* software interrupt summary */ | |
24 | #define ICCS 0x18 /* interval clock control */ | |
25 | #define NICR 0x19 /* next interval count */ | |
26 | #define ICR 0x1a /* interval count */ | |
27 | #define TODR 0x1b /* time of year (day) */ | |
28 | #define RXCS 0x20 /* console receiver control and status */ | |
29 | #define RXDB 0x21 /* console receiver data buffer */ | |
30 | #define TXCS 0x22 /* console transmitter control and status */ | |
31 | #define TXDB 0x23 /* console transmitter data buffer */ | |
32 | #define MAPEN 0x38 /* memory management enable */ | |
33 | #define TBIA 0x39 /* translation buffer invalidate all */ | |
34 | #define TBIS 0x3a /* translation buffer invalidate single */ | |
35 | #define PMR 0x3d /* performance monitor enable */ | |
36 | #define SID 0x3e /* system identification */ | |
03f24a6b | 37 | |
a8f16919 | 38 | #if VAX780 |
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39 | #define ACCS 0x28 /* accelerator control and status */ |
40 | #define ACCR 0x29 /* accelerator maintenance */ | |
41 | #define WCSA 0x2c /* WCS address */ | |
42 | #define WCSD 0x2d /* WCS data */ | |
43 | #define SBIFS 0x30 /* SBI fault and status */ | |
44 | #define SBIS 0x31 /* SBI silo */ | |
45 | #define SBISC 0x32 /* SBI silo comparator */ | |
46 | #define SBIMT 0x33 /* SBI maintenance */ | |
47 | #define SBIER 0x34 /* SBI error register */ | |
48 | #define SBITA 0x35 /* SBI timeout address */ | |
49 | #define SBIQC 0x36 /* SBI quadword clear */ | |
50 | #define MBRK 0x3c /* micro-program breakpoint */ | |
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51 | #endif |
52 | ||
a8f16919 | 53 | #if VAX750 |
bbe0bf68 | 54 | #define MCSR 0x17 /* machine check status register */ |
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55 | #define CSRS 0x1c /* console storage receive status register */ |
56 | #define CSRD 0x1d /* console storage receive data register */ | |
57 | #define CSTS 0x1e /* console storage transmit status register */ | |
58 | #define CSTD 0x1f /* console storage transmit data register */ | |
59 | #define TBDR 0x24 /* translation buffer disable register */ | |
60 | #define CADR 0x25 /* cache disable register */ | |
61 | #define MCESR 0x26 /* machine check error summary register */ | |
62 | #define CAER 0x27 /* cache error */ | |
63 | #define IUR 0x37 /* init unibus register */ | |
64 | #define TB 0x3b /* translation buffer */ | |
65 | #endif |