[unix-history] / usr / src / sys / vax / uba / dz.c

/*	dz.c	4.38	82/05/19	*/

#include "dz.h"
#if NDZ > 0
/*
 *  DZ-11 and DZ32 Driver
 *
 * This driver mimics dh.c; see it for explanation of common code.
 */
#include "bk.h"
#include "../h/param.h"
#include "../h/systm.h"
#include "../h/tty.h"
#include "../h/dir.h"
#include "../h/user.h"
#include "../h/proc.h"
#include "../h/map.h"
#include "../h/pte.h"
#include "../h/buf.h"
#include "../h/vm.h"
#include "../h/ubavar.h"
#include "../h/conf.h"
#include "../h/pdma.h"
#include "../h/bk.h"
#include "../h/file.h"

/*
 * Driver information for auto-configuration stuff.
 */
int	dzprobe(), dzattach(), dzrint();
struct	uba_device *dzinfo[NDZ];
u_short	dzstd[] = { 0 };
struct	uba_driver dzdriver =
	{ dzprobe, 0, dzattach, 0, dzstd, "dz", dzinfo };

#define	NDZLINE 	(NDZ*8)
 
/*
 * Registers and bits
 */

/* bits in dzlpr */
#define	BITS7	0020
#define	BITS8	0030
#define	TWOSB	0040
#define	PENABLE	0100
#define	OPAR	0200

/* bits in dzrbuf */
#define	DZ_PE	010000
#define	DZ_FE	020000
#define	DZ_DO	040000

/* bits in dzcsr */
#define	DZ_32	000001		/* DZ32 mode */
#define	DZ_MIE	000002		/* Modem Interrupt Enable */
#define	DZ_CLR	000020		/* Reset dz */
#define	DZ_MSE	000040		/* Master Scan Enable */
#define	DZ_RIE	000100		/* Receiver Interrupt Enable */
#define DZ_MSC	004000		/* Modem Status Change */
#define	DZ_SAE	010000		/* Silo Alarm Enable */
#define	DZ_TIE	040000		/* Transmit Interrupt Enable */
#define	DZ_IEN	(DZ_32|DZ_MIE|DZ_MSE|DZ_RIE|DZ_TIE|DZ_SAE)

/* flags for modem-control */
#define	DZ_ON	DZ_DTR
#define	DZ_OFF	0

/* bits in dzlcs */
#define DZ_ACK	0100000		/* ACK bit in dzlcs */
#define DZ_RTS	0010000		/* Request To Send */
#define	DZ_ST	0004000		/* Secondary Transmit */
#define	DZ_BRK	0002000		/* Break */
#define DZ_DTR	0001000		/* Data Terminal Ready */
#define	DZ_LE	0000400		/* Line Enable */
#define	DZ_DSR	0000200		/* Data Set Ready */
#define	DZ_RI	0000100		/* Ring Indicate */
#define DZ_CD	0000040		/* Carrier Detect */
#define	DZ_CTS	0000020		/* Clear To Send */
#define	DZ_SR	0000010		/* Secondary Receive */
 
/* bits in dm lsr, copied from dh.c */
#define	DML_DSR		0000400		/* data set ready, not a real DM bit */
#define	DML_RNG		0000200		/* ring */
#define	DML_CAR		0000100		/* carrier detect */
#define	DML_CTS		0000040		/* clear to send */
#define	DML_SR		0000020		/* secondary receive */
#define	DML_ST		0000010		/* secondary transmit */
#define	DML_RTS		0000004		/* request to send */
#define	DML_DTR		0000002		/* data terminal ready */
#define	DML_LE		0000001		/* line enable */

int	dzstart(), dzxint(), dzdma();
int	ttrstrt();
struct	tty dz_tty[NDZLINE];
int	dz_cnt = { NDZLINE };
int	dzact;

struct device {
	short dzcsr;
	short dzrbuf;
	union {
		struct {
			char	dztcr0;
			char	dzdtr0;
			char	dztbuf0;
			char	dzbrk0;
		} dz11;
		struct {
			short	dzlcs0;
			char	dztbuf0;
			char	dzlnen0;
		} dz32;
	} dzun;
};

#define dzlpr	dzrbuf
#define dzmsr	dzun.dz11.dzbrk0
#define dztcr	dzun.dz11.dztcr0
#define dzdtr	dzun.dz11.dzdtr0
#define dztbuf	dzun.dz11.dztbuf0
#define dzlcs	dzun.dz32.dzlcs0
#define	dzbrk	dzmsr
#define dzlnen	dzun.dz32.dzlnen0
#define dzmtsr	dzun.dz32.dztbuf0;

#define dzwait(x)	while (((x)->dzlcs & DZ_ACK) == 0)

/*
 * Software copy of dzbrk since it isn't readable
 */
char	dz_brk[NDZ];
char	dzsoftCAR[NDZ];
char	dz_lnen[NDZ];	/* saved line enable bits for DZ32 */

/*
 * The dz11 doesn't interrupt on carrier transitions, so
 * we have to use a timer to watch it.
 */
char	dz_timer;		/* timer started? */

/*
 * Pdma structures for fast output code
 */
struct	pdma dzpdma[NDZLINE];

char	dz_speeds[] =
	{ 0,020,021,022,023,024,0,025,026,027,030,032,034,036,037,0 };
 
#ifndef PORTSELECTOR
#define	ISPEED	B300
#define	IFLAGS	(EVENP|ODDP|ECHO)
#else
#define	ISPEED	B4800
#define	IFLAGS	(EVENP|ODDP)
#endif

dzprobe(reg)
	caddr_t reg;
{
	register int br, cvec;
	register struct device *dzaddr = (struct device *)reg;

#ifdef lint
	br = 0; cvec = br; br = cvec;
	dzrint(0); dzxint((struct tty *)0);
#endif
	dzaddr->dzcsr = DZ_TIE|DZ_MSE|DZ_32;
	if (dzaddr->dzcsr & DZ_32)
		dzaddr->dzlnen = 1;
	else
		dzaddr->dztcr = 1;		/* enable any line */
	DELAY(100000);
	dzaddr->dzcsr = DZ_CLR|DZ_32;		/* reset everything */
	if (cvec && cvec != 0x200)
		cvec -= 4;
	return (1);
}

dzattach(ui)
	register struct uba_device *ui;
{
	register struct pdma *pdp = &dzpdma[ui->ui_unit*8];
	register struct tty *tp = &dz_tty[ui->ui_unit*8];
	register int cntr;
	extern dzscan();

	for (cntr = 0; cntr < 8; cntr++) {
		pdp->p_addr = (struct device *)ui->ui_addr;
		pdp->p_arg = (int)tp;
		pdp->p_fcn = dzxint;
		pdp++, tp++;
	}
	dzsoftCAR[ui->ui_unit] = ui->ui_flags;
	if (dz_timer == 0) {
		dz_timer++;
		timeout(dzscan, (caddr_t)0, hz);
	}
}

/*ARGSUSED*/
dzopen(dev, flag)
	dev_t dev;
{
	register struct tty *tp;
	register int unit;
 
	unit = minor(dev);
	if (unit >= dz_cnt || dzpdma[unit].p_addr == 0) {
		u.u_error = ENXIO;
		return;
	}
	tp = &dz_tty[unit];
	tp->t_addr = (caddr_t)&dzpdma[unit];
	tp->t_oproc = dzstart;
	tp->t_state |= TS_WOPEN;
	if ((tp->t_state & TS_ISOPEN) == 0) {
		ttychars(tp);
		tp->t_ospeed = tp->t_ispeed = ISPEED;
		tp->t_flags = IFLAGS;
		/* tp->t_state |= TS_HUPCLS; */
		dzparam(unit);
	} else if (tp->t_state&TS_XCLUDE && u.u_uid != 0) {
		u.u_error = EBUSY;
		return;
	}
	(void) dzmctl(dev, DZ_ON, DMSET);
	(void) spl5();
	while ((tp->t_state & TS_CARR_ON) == 0) {
		tp->t_state |= TS_WOPEN;
		sleep((caddr_t)&tp->t_rawq, TTIPRI);
	}
	(void) spl0();
	(*linesw[tp->t_line].l_open)(dev, tp);
}
 
/*ARGSUSED*/
dzclose(dev, flag)
	dev_t dev;
{
	register struct tty *tp;
	register int unit;
	register struct device *dzaddr;
	int dz;
 
	unit = minor(dev);
	dz = unit >> 3;
	tp = &dz_tty[unit];
	(*linesw[tp->t_line].l_close)(tp);
	dzaddr = dzpdma[unit].p_addr;
	if (dzaddr->dzcsr&DZ_32)
		(void) dzmctl(dev, DZ_BRK, DMBIC);
	else
		dzaddr->dzbrk = (dz_brk[dz] &= ~(1 << (unit&07)));
	if ((tp->t_state&(TS_HUPCLS|TS_WOPEN)) || (tp->t_state&TS_ISOPEN) == 0)
		(void) dzmctl(dev, DZ_OFF, DMSET);
	ttyclose(tp);
}
 
dzread(dev)
	dev_t dev;
{
	register struct tty *tp;
 
	tp = &dz_tty[minor(dev)];
	(*linesw[tp->t_line].l_read)(tp);
}
 
dzwrite(dev)
	dev_t dev;
{
	register struct tty *tp;
 
	tp = &dz_tty[minor(dev)];
	(*linesw[tp->t_line].l_write)(tp);
}
 
/*ARGSUSED*/
dzrint(dz)
	int dz;
{
	register struct tty *tp;
	register int c;
	register struct device *dzaddr;
	register struct tty *tp0;
	register int unit;
	int overrun = 0;
 
	if ((dzact & (1<<dz)) == 0)
		return;
	unit = dz * 8;
	dzaddr = dzpdma[unit].p_addr;
	tp0 = &dz_tty[unit];
	dzaddr->dzcsr &= ~(DZ_RIE|DZ_MIE);	/* the manual says this song */
	dzaddr->dzcsr |= DZ_RIE|DZ_MIE;		/*   and dance is necessary */
	while (dzaddr->dzcsr & DZ_MSC) {	/* DZ32 modem change interrupt */
		c = dzaddr->dzmtsr;
		tp = tp0 + (c&7);
		if (tp >= &dz_tty[dz_cnt])
			break;
		dzaddr->dzlcs = c&7;	/* get status of modem lines */
		dzwait(dzaddr);		/* wait for them */
		if (c & DZ_CD)		/* carrier status change? */
		if (dzaddr->dzlcs & DZ_CD) {	/* carrier up? */
			if ((tp->t_state&TS_CARR_ON) == 0) {
				wakeup((caddr_t)&tp->t_rawq);
				tp->t_state |= TS_CARR_ON;
			}
		} else {	/* no carrier */
			if (tp->t_state&TS_CARR_ON) {
				gsignal(tp->t_pgrp, SIGHUP);
				gsignal(tp->t_pgrp, SIGCONT);
				dzaddr->dzlcs = DZ_ACK|(c&7);
				flushtty(tp, FREAD|FWRITE);
			}
			tp->t_state &= ~TS_CARR_ON;
		}
	}
	while ((c = dzaddr->dzrbuf) < 0) {	/* char present */
		tp = tp0 + ((c>>8)&07);
		if (tp >= &dz_tty[dz_cnt])
			continue;
		if ((tp->t_state & TS_ISOPEN) == 0) {
			wakeup((caddr_t)&tp->t_rawq);
#ifdef PORTSELECTOR
			if ((tp->t_state&TS_WOPEN) == 0)
#endif
			continue;
		}
		if (c&DZ_FE)
			if (tp->t_flags & RAW)
				c = 0;
			else
				c = tun.t_intrc;
		if (c&DZ_DO && overrun == 0) {
			/* printf("dz%d,%d: silo overflow\n", dz, (c>>8)&7); */
			overrun = 1;
		}
		if (c&DZ_PE)	
			if (((tp->t_flags & (EVENP|ODDP)) == EVENP)
			  || ((tp->t_flags & (EVENP|ODDP)) == ODDP))
				continue;
#if NBK > 0
		if (tp->t_line == NETLDISC) {
			c &= 0177;
			BKINPUT(c, tp);
		} else
#endif
			(*linesw[tp->t_line].l_rint)(c, tp);
	}
}
 
/*ARGSUSED*/
dzioctl(dev, cmd, addr, flag)
	dev_t dev;
	caddr_t addr;
{
	register struct tty *tp;
	register int unit = minor(dev);
	register int dz = unit >> 3;
	register struct device *dzaddr;
	int temp;
 
	tp = &dz_tty[unit];
	cmd = (*linesw[tp->t_line].l_ioctl)(tp, cmd, addr);
	if (cmd == 0)
		return;
	if (ttioctl(tp, cmd, addr, flag)) {
		if (cmd==TIOCSETP || cmd==TIOCSETN)
			dzparam(unit);
	} else switch(cmd) {

	case TIOCSBRK:
		dzaddr = ((struct pdma *)(tp->t_addr))->p_addr;
		if (dzaddr->dzcsr&DZ_32)
			(void) dzmctl(dev, DZ_BRK, DMBIS);
		else
			dzaddr->dzbrk = (dz_brk[dz] |= 1 << (unit&07));
		break;
	case TIOCCBRK:
		dzaddr = ((struct pdma *)(tp->t_addr))->p_addr;
		if (dzaddr->dzcsr&DZ_32)
			(void) dzmctl(dev, DZ_BRK, DMBIC);
		else
			dzaddr->dzbrk = (dz_brk[dz] &= ~(1 << (unit&07)));
		break;
	case TIOCSDTR:
		(void) dzmctl(dev, DZ_DTR|DZ_RTS, DMBIS);
		break;
	case TIOCCDTR:
		(void) dzmctl(dev, DZ_DTR|DZ_RTS, DMBIC);
		break;
	case TIOCMSET:
		if (copyin(addr, (caddr_t) &temp, sizeof(temp)))
			u.u_error = EFAULT;
		else
			(void) dzmctl(dev, dmtodz(temp), DMSET);
		break;
	case TIOCMBIS:
		if (copyin(addr, (caddr_t) &temp, sizeof(temp)))
			u.u_error = EFAULT;
		else
			(void) dzmctl(dev, dmtodz(temp), DMBIS);
		break;
	case TIOCMBIC:
		if (copyin(addr, (caddr_t) &temp, sizeof(temp)))
			u.u_error = EFAULT;
		else
			(void) dzmctl(dev, dmtodz(temp), DMBIC);
		break;
	case TIOCMGET:
		temp = dztodm(dzmctl(dev, 0, DMGET));
		if (copyout((caddr_t) &temp, addr, sizeof(temp)))
			u.u_error = EFAULT;
		break;
	default:
		u.u_error = ENOTTY;
	}
}

dmtodz(bits)
	register int bits;
{
	register int b;

	b = (bits >>1) & 0370;
	if (bits & DML_ST) b |= DZ_ST;
	if (bits & DML_RTS) b |= DZ_RTS;
	if (bits & DML_DTR) b |= DZ_DTR;
	if (bits & DML_LE) b |= DZ_LE;
	return(b);
}

dztodm(bits)
	register int bits;
{
	register int b;

	b = (bits << 1) & 0360;
	if (bits & DZ_DSR) b |= DML_DSR;
	if (bits & DZ_DTR) b |= DML_DTR;
	if (bits & DZ_ST) b |= DML_ST;
	if (bits & DZ_RTS) b |= DML_RTS;
	return(b);
}
 
dzparam(unit)
	register int unit;
{
	register struct tty *tp;
	register struct device *dzaddr;
	register int lpr;
 
	tp = &dz_tty[unit];
	dzaddr = dzpdma[unit].p_addr;
	dzaddr->dzcsr = DZ_IEN;
	dzact |= (1<<(unit>>3));
	if (tp->t_ispeed == 0) {
		(void) dzmctl(unit, DZ_OFF, DMSET);	/* hang up line */
		return;
	}
	lpr = (dz_speeds[tp->t_ispeed]<<8) | (unit & 07);
	if ((tp->t_local&LLITOUT) || (tp->t_flags&RAW))
		lpr |= BITS8;
	else
		lpr |= (BITS7|PENABLE);
	if ((tp->t_flags & EVENP) == 0)
		lpr |= OPAR;
	if (tp->t_ispeed == B110)
		lpr |= TWOSB;
	dzaddr->dzlpr = lpr;
}
 
dzxint(tp)
	register struct tty *tp;
{
	register struct pdma *dp;
	register s, dz, unit;
 
	s = spl5();		/* block pdma interrupts */
	dp = (struct pdma *)tp->t_addr;
	tp->t_state &= ~TS_BUSY;
	if (tp->t_state & TS_FLUSH)
		tp->t_state &= ~TS_FLUSH;
	else {
		ndflush(&tp->t_outq, dp->p_mem-tp->t_outq.c_cf);
		dp->p_end = dp->p_mem = tp->t_outq.c_cf;
	}
	if (tp->t_line)
		(*linesw[tp->t_line].l_start)(tp);
	else
		dzstart(tp);
	dz = minor(tp->t_dev) >> 3;
	unit = minor(tp->t_dev) & 7;
	if (tp->t_outq.c_cc == 0 || (tp->t_state&TS_BUSY)==0)
		if (dp->p_addr->dzcsr & DZ_32)
			dp->p_addr->dzlnen = (dz_lnen[dz] &= ~(1<<unit));
		else
			dp->p_addr->dztcr &= ~(1<<unit);
	splx(s);
}

dzstart(tp)
	register struct tty *tp;
{
	register struct pdma *dp;
	register struct device *dzaddr;
	register int cc;
	int s, dz, unit;
 
	dp = (struct pdma *)tp->t_addr;
	dzaddr = dp->p_addr;
	s = spl5();
	if (tp->t_state & (TS_TIMEOUT|TS_BUSY|TS_TTSTOP))
		goto out;
	if (tp->t_outq.c_cc <= TTLOWAT(tp)) {
		if (tp->t_state&TS_ASLEEP) {
			tp->t_state &= ~TS_ASLEEP;
			wakeup((caddr_t)&tp->t_outq);
		}
		if (tp->t_wsel) {
			selwakeup(tp->t_wsel, tp->t_state & TS_WCOLL);
			tp->t_wsel = 0;
			tp->t_state &= ~TS_WCOLL;
		}
	}
	if (tp->t_outq.c_cc == 0)
		goto out;
	if ((tp->t_flags&RAW) || (tp->t_local&LLITOUT))
		cc = ndqb(&tp->t_outq, 0);
	else {
		cc = ndqb(&tp->t_outq, 0200);
		if (cc == 0) {
			cc = getc(&tp->t_outq);
			timeout(ttrstrt, (caddr_t)tp, (cc&0x7f) + 6);
			tp->t_state |= TS_TIMEOUT;
			goto out;
		}
	}
	tp->t_state |= TS_BUSY;
	dp->p_end = dp->p_mem = tp->t_outq.c_cf;
	dp->p_end += cc;
	dz = minor(tp->t_dev) >> 3;
	unit = minor(tp->t_dev) & 7;
	if (dzaddr->dzcsr & DZ_32)
		dzaddr->dzlnen = (dz_lnen[dz] |= (1<<unit));
	else
		dzaddr->dztcr |= (1<<unit);
out:
	splx(s);
}
 
/*
 * Stop output on a line.
 */
/*ARGSUSED*/
dzstop(tp, flag)
	register struct tty *tp;
{
	register struct pdma *dp;
	register int s;

	dp = (struct pdma *)tp->t_addr;
	s = spl5();
	if (tp->t_state & TS_BUSY) {
		dp->p_end = dp->p_mem;
		if ((tp->t_state&TS_TTSTOP)==0)
			tp->t_state |= TS_FLUSH;
	}
	splx(s);
}
 
dzmctl(dev, bits, how)
	dev_t dev;
	int bits, how;
{
	register struct device *dzaddr;
	register int unit, mbits;
	int b, s;

	unit = minor(dev);
	b = 1<<(unit&7);
	dzaddr = dzpdma[unit].p_addr;
	s = spl5();
	if (dzaddr->dzcsr & DZ_32) {
		dzwait(dzaddr)
		DELAY(100);		/* IS 100 TOO MUCH? */
		dzaddr->dzlcs = unit&7;
		DELAY(100);
		dzwait(dzaddr)
		DELAY(100);
		mbits = dzaddr->dzlcs;
		mbits &= 0177770;
	} else {
		mbits = (dzaddr->dzdtr & b) ? DZ_DTR : 0;
		mbits |= (dzaddr->dzmsr & b) ? DZ_CD : 0;
		mbits |= (dzaddr->dztbuf & b) ? DZ_RI : 0;
	}
	switch (how) {
	case DMSET:
		mbits = bits;
		break;

	case DMBIS:
		mbits |= bits;
		break;

	case DMBIC:
		mbits &= ~bits;
		break;

	case DMGET:
		(void) splx(s);
		return(mbits);
	}
	if (dzaddr->dzcsr & DZ_32) {
		mbits |= DZ_ACK|(unit&7);
		dzaddr->dzlcs = mbits;
	} else {
		if (mbits & DZ_DTR)
			dzaddr->dzdtr |= b;
		else
			dzaddr->dzdtr &= ~b;
	}
	(void) splx(s);
	return(mbits);
}
 
dzscan()
{
	register i;
	register struct device *dzaddr;
	register bit;
	register struct tty *tp;
	register car;
 
	for (i = 0; i < dz_cnt ; i++) {
		dzaddr = dzpdma[i].p_addr;
		if (dzaddr == 0)
			continue;
		tp = &dz_tty[i];
		bit = 1<<(i&07);
		car = 0;
		if (dzsoftCAR[i>>3]&bit)
			car = 1;
		else if (dzaddr->dzcsr & DZ_32) {
			dzaddr->dzlcs = i&07;
			dzwait(dzaddr);
			car = dzaddr->dzlcs & DZ_CD;
		} else
			car = dzaddr->dzmsr&bit;
		if (car) {
			/* carrier present */
			if ((tp->t_state & TS_CARR_ON) == 0) {
				wakeup((caddr_t)&tp->t_rawq);
				tp->t_state |= TS_CARR_ON;
			}
		} else {
			if ((tp->t_state&TS_CARR_ON) &&
			    (tp->t_local&LNOHANG)==0) {
				/* carrier lost */
				if (tp->t_state&TS_ISOPEN) {
					gsignal(tp->t_pgrp, SIGHUP);
					gsignal(tp->t_pgrp, SIGCONT);
					dzaddr->dzdtr &= ~bit;
					flushtty(tp, FREAD|FWRITE);
				}
				tp->t_state &= ~TS_CARR_ON;
			}
		}
	}
	timeout(dzscan, (caddr_t)0, 2*hz);
}

dztimer()
{
	int dz;

	for (dz = 0; dz < NDZ; dz++)
		dzrint(dz);
}

/*
 * Reset state of driver if UBA reset was necessary.
 * Reset parameters and restart transmission on open lines.
 */
dzreset(uban)
	int uban;
{
	register int unit;
	register struct tty *tp;
	register struct uba_device *ui;

	for (unit = 0; unit < NDZLINE; unit++) {
		ui = dzinfo[unit >> 3];
		if (ui == 0 || ui->ui_ubanum != uban || ui->ui_alive == 0)
			continue;
		if (unit%8 == 0)
			printf(" dz%d", unit>>3);
		tp = &dz_tty[unit];
		if (tp->t_state & (TS_ISOPEN|TS_WOPEN)) {
			dzparam(unit);
			(void) dzmctl(unit, DZ_ON, DMSET);
			tp->t_state &= ~TS_BUSY;
			dzstart(tp);
		}
	}
	dztimer();
}
#endif
Commit	Line	Data
4f5daa2a	1	/* dz.c 4.38 82/05/19 */
5074fa57	2
66b4fb09	3	#include "dz.h"
a3cb8f60	4	#if NDZ > 0
5074fa57	5	/*
bea90e0b	6	* DZ-11 and DZ32 Driver
7e00c42b BJ	7	*
7e00c42b BJ	8	* This driver mimics dh.c; see it for explanation of common code.
5074fa57	9	*/
e2c4935e	10	#include "bk.h"
5074fa57 BJ	11	#include "../h/param.h"
	12	#include "../h/systm.h"
	13	#include "../h/tty.h"
	14	#include "../h/dir.h"
	15	#include "../h/user.h"
668cc26d	16	#include "../h/proc.h"
5074fa57 BJ	17	#include "../h/map.h"
5074fa57 BJ	18	#include "../h/pte.h"
3f3a34c3	19	#include "../h/buf.h"
7e286c72	20	#include "../h/vm.h"
6a1a96ff	21	#include "../h/ubavar.h"
5074fa57 BJ	22	#include "../h/conf.h"
5074fa57 BJ	23	#include "../h/pdma.h"
771d8988	24	#include "../h/bk.h"
cc343d94	25	#include "../h/file.h"
d3ebf5ee	26
7e00c42b BJ	27	/*
	28	* Driver information for auto-configuration stuff.
	29	*/
71236e46	30	int dzprobe(), dzattach(), dzrint();
6a1a96ff	31	struct uba_device *dzinfo[NDZ];
3f3a34c3	32	u_short dzstd[] = { 0 };
3f3a34c3	33	struct uba_driver dzdriver =
71236e46	34	{ dzprobe, 0, dzattach, 0, dzstd, "dz", dzinfo };
3f3a34c3	35
a3cb8f60	36	#define NDZLINE (NDZ*8)
5074fa57	37
7e00c42b BJ	38	/*
	39	* Registers and bits
	40	*/
	41
bea90e0b BJ	42	/* bits in dzlpr */
	43	#define BITS7 0020
	44	#define BITS8 0030
	45	#define TWOSB 0040
88d5b764 BJ	46	#define PENABLE 0100
88d5b764 BJ	47	#define OPAR 0200
5074fa57	48
bea90e0b	49	/* bits in dzrbuf */
7e00c42b BJ	50	#define DZ_PE 010000
	51	#define DZ_FE 020000
	52	#define DZ_DO 040000
	53
bea90e0b BJ	54	/* bits in dzcsr */
	55	#define DZ_32 000001 /* DZ32 mode */
	56	#define DZ_MIE 000002 /* Modem Interrupt Enable */
	57	#define DZ_CLR 000020 /* Reset dz */
	58	#define DZ_MSE 000040 /* Master Scan Enable */
	59	#define DZ_RIE 000100 /* Receiver Interrupt Enable */
	60	#define DZ_MSC 004000 /* Modem Status Change */
7e00c42b BJ	61	#define DZ_SAE 010000 /* Silo Alarm Enable */
7e00c42b BJ	62	#define DZ_TIE 040000 /* Transmit Interrupt Enable */
bea90e0b	63	#define DZ_IEN (DZ_32\|DZ_MIE\|DZ_MSE\|DZ_RIE\|DZ_TIE\|DZ_SAE)
7e00c42b	64
bea90e0b BJ	65	/* flags for modem-control */
bea90e0b BJ	66	#define DZ_ON DZ_DTR
7e00c42b	67	#define DZ_OFF 0
bea90e0b BJ	68
	69	/* bits in dzlcs */
	70	#define DZ_ACK 0100000 /* ACK bit in dzlcs */
	71	#define DZ_RTS 0010000 /* Request To Send */
	72	#define DZ_ST 0004000 /* Secondary Transmit */
	73	#define DZ_BRK 0002000 /* Break */
	74	#define DZ_DTR 0001000 /* Data Terminal Ready */
	75	#define DZ_LE 0000400 /* Line Enable */
	76	#define DZ_DSR 0000200 /* Data Set Ready */
	77	#define DZ_RI 0000100 /* Ring Indicate */
	78	#define DZ_CD 0000040 /* Carrier Detect */
	79	#define DZ_CTS 0000020 /* Clear To Send */
	80	#define DZ_SR 0000010 /* Secondary Receive */
5074fa57	81
bea90e0b BJ	82	/* bits in dm lsr, copied from dh.c */
	83	#define DML_DSR 0000400 /* data set ready, not a real DM bit */
	84	#define DML_RNG 0000200 /* ring */
	85	#define DML_CAR 0000100 /* carrier detect */
	86	#define DML_CTS 0000040 /* clear to send */
	87	#define DML_SR 0000020 /* secondary receive */
	88	#define DML_ST 0000010 /* secondary transmit */
	89	#define DML_RTS 0000004 /* request to send */
	90	#define DML_DTR 0000002 /* data terminal ready */
	91	#define DML_LE 0000001 /* line enable */
	92
7e00c42b	93	int dzstart(), dzxint(), dzdma();
771d8988	94	int ttrstrt();
a3cb8f60 BJ	95	struct tty dz_tty[NDZLINE];
a3cb8f60 BJ	96	int dz_cnt = { NDZLINE };
9dca4f86	97	int dzact;
5074fa57 BJ	98
5074fa57 BJ	99	struct device {
bea90e0b BJ	100	short dzcsr;
	101	short dzrbuf;
	102	union {
	103	struct {
	104	char dztcr0;
	105	char dzdtr0;
	106	char dztbuf0;
	107	char dzbrk0;
	108	} dz11;
	109	struct {
	110	short dzlcs0;
	111	char dztbuf0;
	112	char dzlnen0;
	113	} dz32;
	114	} dzun;
5074fa57	115	};
bea90e0b BJ	116
	117	#define dzlpr dzrbuf
	118	#define dzmsr dzun.dz11.dzbrk0
	119	#define dztcr dzun.dz11.dztcr0
	120	#define dzdtr dzun.dz11.dzdtr0
	121	#define dztbuf dzun.dz11.dztbuf0
	122	#define dzlcs dzun.dz32.dzlcs0
	123	#define dzbrk dzmsr
	124	#define dzlnen dzun.dz32.dzlnen0
	125	#define dzmtsr dzun.dz32.dztbuf0;
	126
	127	#define dzwait(x) while (((x)->dzlcs & DZ_ACK) == 0)
	128
7e00c42b BJ	129	/*
	130	* Software copy of dzbrk since it isn't readable
	131	*/
a3cb8f60 BJ	132	char dz_brk[NDZ];
a3cb8f60 BJ	133	char dzsoftCAR[NDZ];
bea90e0b	134	char dz_lnen[NDZ]; /* saved line enable bits for DZ32 */
5074fa57	135
7e00c42b	136	/*
bea90e0b	137	* The dz11 doesn't interrupt on carrier transitions, so
7e00c42b BJ	138	* we have to use a timer to watch it.
	139	*/
	140	char dz_timer; /* timer started? */
	141
	142	/*
	143	* Pdma structures for fast output code
	144	*/
a3cb8f60	145	struct pdma dzpdma[NDZLINE];
7e00c42b	146
3f3a34c3	147	char dz_speeds[] =
57644725	148	{ 0,020,021,022,023,024,0,025,026,027,030,032,034,036,037,0 };
5074fa57	149
df07bd9e SL	150	#ifndef PORTSELECTOR
	151	#define ISPEED B300
	152	#define IFLAGS (EVENP\|ODDP\|ECHO)
	153	#else
	154	#define ISPEED B4800
	155	#define IFLAGS (EVENP\|ODDP)
	156	#endif
	157
71236e46	158	dzprobe(reg)
3f3a34c3 BJ	159	caddr_t reg;
3f3a34c3 BJ	160	{
88d5b764 BJ	161	register int br, cvec;
88d5b764 BJ	162	register struct device dzaddr = (struct device )reg;
3f3a34c3	163
71236e46	164	#ifdef lint
a0eab615	165	br = 0; cvec = br; br = cvec;
89b8a44c	166	dzrint(0); dzxint((struct tty *)0);
71236e46	167	#endif
bea90e0b BJ	168	dzaddr->dzcsr = DZ_TIE\|DZ_MSE\|DZ_32;
	169	if (dzaddr->dzcsr & DZ_32)
	170	dzaddr->dzlnen = 1;
	171	else
	172	dzaddr->dztcr = 1; /* enable any line */
88d5b764	173	DELAY(100000);
bea90e0b	174	dzaddr->dzcsr = DZ_CLR\|DZ_32; /* reset everything */
88d5b764 BJ	175	if (cvec && cvec != 0x200)
	176	cvec -= 4;
	177	return (1);
3f3a34c3 BJ	178	}
3f3a34c3 BJ	179
71236e46	180	dzattach(ui)
6a1a96ff	181	register struct uba_device *ui;
3f3a34c3 BJ	182	{
	183	register struct pdma pdp = &dzpdma[ui->ui_unit8];
	184	register struct tty tp = &dz_tty[ui->ui_unit8];
71236e46	185	register int cntr;
a3cb8f60	186	extern dzscan();
3f3a34c3	187
71236e46 BJ	188	for (cntr = 0; cntr < 8; cntr++) {
71236e46 BJ	189	pdp->p_addr = (struct device *)ui->ui_addr;
3f3a34c3 BJ	190	pdp->p_arg = (int)tp;
	191	pdp->p_fcn = dzxint;
	192	pdp++, tp++;
	193	}
7e286c72	194	dzsoftCAR[ui->ui_unit] = ui->ui_flags;
be2b272c BJ	195	if (dz_timer == 0) {
be2b272c BJ	196	dz_timer++;
7780575a	197	timeout(dzscan, (caddr_t)0, hz);
be2b272c	198	}
3f3a34c3 BJ	199	}
3f3a34c3 BJ	200
5074fa57	201	/ARGSUSED/
3f3a34c3 BJ	202	dzopen(dev, flag)
3f3a34c3 BJ	203	dev_t dev;
5074fa57 BJ	204	{
5074fa57 BJ	205	register struct tty *tp;
3f3a34c3	206	register int unit;
5074fa57	207
3f3a34c3 BJ	208	unit = minor(dev);
3f3a34c3 BJ	209	if (unit >= dz_cnt \|\| dzpdma[unit].p_addr == 0) {
5074fa57 BJ	210	u.u_error = ENXIO;
	211	return;
	212	}
3f3a34c3 BJ	213	tp = &dz_tty[unit];
3f3a34c3 BJ	214	tp->t_addr = (caddr_t)&dzpdma[unit];
5074fa57	215	tp->t_oproc = dzstart;
941944c9 BJ	216	tp->t_state \|= TS_WOPEN;
941944c9 BJ	217	if ((tp->t_state & TS_ISOPEN) == 0) {
5074fa57	218	ttychars(tp);
df07bd9e SL	219	tp->t_ospeed = tp->t_ispeed = ISPEED;
df07bd9e SL	220	tp->t_flags = IFLAGS;
941944c9	221	/* tp->t_state \|= TS_HUPCLS; */
3f3a34c3	222	dzparam(unit);
941944c9	223	} else if (tp->t_state&TS_XCLUDE && u.u_uid != 0) {
5074fa57 BJ	224	u.u_error = EBUSY;
	225	return;
	226	}
668cc26d	227	(void) dzmctl(dev, DZ_ON, DMSET);
771d8988	228	(void) spl5();
941944c9 BJ	229	while ((tp->t_state & TS_CARR_ON) == 0) {
941944c9 BJ	230	tp->t_state \|= TS_WOPEN;
5074fa57 BJ	231	sleep((caddr_t)&tp->t_rawq, TTIPRI);
5074fa57 BJ	232	}
771d8988	233	(void) spl0();
3f3a34c3	234	(*linesw[tp->t_line].l_open)(dev, tp);
5074fa57 BJ	235	}
5074fa57 BJ	236
3f3a34c3 BJ	237	/ARGSUSED/
	238	dzclose(dev, flag)
	239	dev_t dev;
5074fa57 BJ	240	{
5074fa57 BJ	241	register struct tty *tp;
3f3a34c3	242	register int unit;
bea90e0b	243	register struct device *dzaddr;
fa627691	244	int dz;
5074fa57	245
3f3a34c3 BJ	246	unit = minor(dev);
	247	dz = unit >> 3;
	248	tp = &dz_tty[unit];
5074fa57	249	(*linesw[tp->t_line].l_close)(tp);
bea90e0b BJ	250	dzaddr = dzpdma[unit].p_addr;
bea90e0b BJ	251	if (dzaddr->dzcsr&DZ_32)
668cc26d	252	(void) dzmctl(dev, DZ_BRK, DMBIC);
bea90e0b BJ	253	else
bea90e0b BJ	254	dzaddr->dzbrk = (dz_brk[dz] &= ~(1 << (unit&07)));
4f5daa2a	255	if ((tp->t_state&(TS_HUPCLS\|TS_WOPEN)) \|\| (tp->t_state&TS_ISOPEN) == 0)
668cc26d	256	(void) dzmctl(dev, DZ_OFF, DMSET);
5074fa57 BJ	257	ttyclose(tp);
	258	}
	259
3f3a34c3 BJ	260	dzread(dev)
3f3a34c3 BJ	261	dev_t dev;
5074fa57 BJ	262	{
	263	register struct tty *tp;
	264
3f3a34c3	265	tp = &dz_tty[minor(dev)];
5074fa57 BJ	266	(*linesw[tp->t_line].l_read)(tp);
	267	}
	268
3f3a34c3 BJ	269	dzwrite(dev)
3f3a34c3 BJ	270	dev_t dev;
5074fa57 BJ	271	{
	272	register struct tty *tp;
	273
3f3a34c3	274	tp = &dz_tty[minor(dev)];
5074fa57 BJ	275	(*linesw[tp->t_line].l_write)(tp);
	276	}
	277
9dca4f86	278	/ARGSUSED/
3f3a34c3 BJ	279	dzrint(dz)
3f3a34c3 BJ	280	int dz;
5074fa57 BJ	281	{
	282	register struct tty *tp;
	283	register int c;
	284	register struct device *dzaddr;
9dca4f86	285	register struct tty *tp0;
3f3a34c3	286	register int unit;
b19fe459	287	int overrun = 0;
5074fa57	288
88d5b764 BJ	289	if ((dzact & (1<<dz)) == 0)
	290	return;
	291	unit = dz * 8;
	292	dzaddr = dzpdma[unit].p_addr;
	293	tp0 = &dz_tty[unit];
bea90e0b BJ	294	dzaddr->dzcsr &= ~(DZ_RIE\|DZ_MIE); /* the manual says this song */
	295	dzaddr->dzcsr \|= DZ_RIE\|DZ_MIE; /* and dance is necessary */
	296	while (dzaddr->dzcsr & DZ_MSC) { /* DZ32 modem change interrupt */
	297	c = dzaddr->dzmtsr;
	298	tp = tp0 + (c&7);
	299	if (tp >= &dz_tty[dz_cnt])
	300	break;
	301	dzaddr->dzlcs = c&7; /* get status of modem lines */
	302	dzwait(dzaddr); /* wait for them */
	303	if (c & DZ_CD) /* carrier status change? */
	304	if (dzaddr->dzlcs & DZ_CD) { /* carrier up? */
	305	if ((tp->t_state&TS_CARR_ON) == 0) {
	306	wakeup((caddr_t)&tp->t_rawq);
	307	tp->t_state \|= TS_CARR_ON;
	308	}
	309	} else { /* no carrier */
	310	if (tp->t_state&TS_CARR_ON) {
	311	gsignal(tp->t_pgrp, SIGHUP);
	312	gsignal(tp->t_pgrp, SIGCONT);
	313	dzaddr->dzlcs = DZ_ACK\|(c&7);
	314	flushtty(tp, FREAD\|FWRITE);
	315	}
	316	tp->t_state &= ~TS_CARR_ON;
	317	}
	318	}
88d5b764 BJ	319	while ((c = dzaddr->dzrbuf) < 0) { /* char present */
	320	tp = tp0 + ((c>>8)&07);
	321	if (tp >= &dz_tty[dz_cnt])
	322	continue;
941944c9	323	if ((tp->t_state & TS_ISOPEN) == 0) {
88d5b764	324	wakeup((caddr_t)&tp->t_rawq);
df07bd9e SL	325	#ifdef PORTSELECTOR
	326	if ((tp->t_state&TS_WOPEN) == 0)
	327	#endif
5074fa57	328	continue;
9dca4f86	329	}
7e00c42b	330	if (c&DZ_FE)
88d5b764	331	if (tp->t_flags & RAW)
7e00c42b	332	c = 0;
88d5b764 BJ	333	else
88d5b764 BJ	334	c = tun.t_intrc;
b19fe459	335	if (c&DZ_DO && overrun == 0) {
bea90e0b	336	/* printf("dz%d,%d: silo overflow\n", dz, (c>>8)&7); */
b19fe459 BJ	337	overrun = 1;
b19fe459 BJ	338	}
7e00c42b	339	if (c&DZ_PE)
88d5b764 BJ	340	if (((tp->t_flags & (EVENP\|ODDP)) == EVENP)
	341	\|\| ((tp->t_flags & (EVENP\|ODDP)) == ODDP))
	342	continue;
e2c4935e	343	#if NBK > 0
88d5b764 BJ	344	if (tp->t_line == NETLDISC) {
	345	c &= 0177;
	346	BKINPUT(c, tp);
	347	} else
e2c4935e	348	#endif
88d5b764	349	(*linesw[tp->t_line].l_rint)(c, tp);
5074fa57 BJ	350	}
	351	}
	352
	353	/ARGSUSED/
	354	dzioctl(dev, cmd, addr, flag)
3f3a34c3 BJ	355	dev_t dev;
3f3a34c3 BJ	356	caddr_t addr;
5074fa57 BJ	357	{
5074fa57 BJ	358	register struct tty *tp;
3f3a34c3 BJ	359	register int unit = minor(dev);
3f3a34c3 BJ	360	register int dz = unit >> 3;
bea90e0b BJ	361	register struct device *dzaddr;
bea90e0b BJ	362	int temp;
5074fa57	363
3f3a34c3	364	tp = &dz_tty[unit];
771d8988 BJ	365	cmd = (*linesw[tp->t_line].l_ioctl)(tp, cmd, addr);
	366	if (cmd == 0)
	367	return;
c3277147	368	if (ttioctl(tp, cmd, addr, flag)) {
5074fa57	369	if (cmd==TIOCSETP \|\| cmd==TIOCSETN)
3f3a34c3	370	dzparam(unit);
dc44829a	371	} else switch(cmd) {
3f3a34c3	372
dc44829a	373	case TIOCSBRK:
bea90e0b BJ	374	dzaddr = ((struct pdma *)(tp->t_addr))->p_addr;
bea90e0b BJ	375	if (dzaddr->dzcsr&DZ_32)
668cc26d	376	(void) dzmctl(dev, DZ_BRK, DMBIS);
bea90e0b BJ	377	else
bea90e0b BJ	378	dzaddr->dzbrk = (dz_brk[dz] \|= 1 << (unit&07));
dc44829a BJ	379	break;
dc44829a BJ	380	case TIOCCBRK:
bea90e0b BJ	381	dzaddr = ((struct pdma *)(tp->t_addr))->p_addr;
bea90e0b BJ	382	if (dzaddr->dzcsr&DZ_32)
668cc26d	383	(void) dzmctl(dev, DZ_BRK, DMBIC);
bea90e0b BJ	384	else
bea90e0b BJ	385	dzaddr->dzbrk = (dz_brk[dz] &= ~(1 << (unit&07)));
dc44829a BJ	386	break;
dc44829a BJ	387	case TIOCSDTR:
668cc26d	388	(void) dzmctl(dev, DZ_DTR\|DZ_RTS, DMBIS);
dc44829a BJ	389	break;
dc44829a BJ	390	case TIOCCDTR:
668cc26d	391	(void) dzmctl(dev, DZ_DTR\|DZ_RTS, DMBIC);
bea90e0b BJ	392	break;
	393	case TIOCMSET:
	394	if (copyin(addr, (caddr_t) &temp, sizeof(temp)))
	395	u.u_error = EFAULT;
	396	else
668cc26d	397	(void) dzmctl(dev, dmtodz(temp), DMSET);
bea90e0b BJ	398	break;
	399	case TIOCMBIS:
	400	if (copyin(addr, (caddr_t) &temp, sizeof(temp)))
	401	u.u_error = EFAULT;
	402	else
668cc26d	403	(void) dzmctl(dev, dmtodz(temp), DMBIS);
bea90e0b BJ	404	break;
	405	case TIOCMBIC:
	406	if (copyin(addr, (caddr_t) &temp, sizeof(temp)))
	407	u.u_error = EFAULT;
	408	else
668cc26d	409	(void) dzmctl(dev, dmtodz(temp), DMBIC);
bea90e0b BJ	410	break;
	411	case TIOCMGET:
	412	temp = dztodm(dzmctl(dev, 0, DMGET));
	413	if (copyout((caddr_t) &temp, addr, sizeof(temp)))
	414	u.u_error = EFAULT;
dc44829a BJ	415	break;
dc44829a BJ	416	default:
5074fa57	417	u.u_error = ENOTTY;
dc44829a	418	}
5074fa57	419	}
bea90e0b BJ	420
	421	dmtodz(bits)
	422	register int bits;
	423	{
	424	register int b;
	425
	426	b = (bits >>1) & 0370;
	427	if (bits & DML_ST) b \|= DZ_ST;
	428	if (bits & DML_RTS) b \|= DZ_RTS;
	429	if (bits & DML_DTR) b \|= DZ_DTR;
	430	if (bits & DML_LE) b \|= DZ_LE;
	431	return(b);
	432	}
	433
	434	dztodm(bits)
	435	register int bits;
	436	{
	437	register int b;
	438
	439	b = (bits << 1) & 0360;
	440	if (bits & DZ_DSR) b \|= DML_DSR;
	441	if (bits & DZ_DTR) b \|= DML_DTR;
	442	if (bits & DZ_ST) b \|= DML_ST;
	443	if (bits & DZ_RTS) b \|= DML_RTS;
	444	return(b);
	445	}
5074fa57	446
3f3a34c3 BJ	447	dzparam(unit)
3f3a34c3 BJ	448	register int unit;
5074fa57 BJ	449	{
	450	register struct tty *tp;
	451	register struct device *dzaddr;
3f3a34c3	452	register int lpr;
5074fa57	453
3f3a34c3 BJ	454	tp = &dz_tty[unit];
3f3a34c3 BJ	455	dzaddr = dzpdma[unit].p_addr;
5074fa57	456	dzaddr->dzcsr = DZ_IEN;
3f3a34c3	457	dzact \|= (1<<(unit>>3));
5074fa57	458	if (tp->t_ispeed == 0) {
668cc26d	459	(void) dzmctl(unit, DZ_OFF, DMSET); /* hang up line */
5074fa57 BJ	460	return;
5074fa57 BJ	461	}
3f3a34c3	462	lpr = (dz_speeds[tp->t_ispeed]<<8) \| (unit & 07);
be5b7974	463	if ((tp->t_local&LLITOUT) \|\| (tp->t_flags&RAW))
5074fa57 BJ	464	lpr \|= BITS8;
	465	else
	466	lpr \|= (BITS7\|PENABLE);
	467	if ((tp->t_flags & EVENP) == 0)
	468	lpr \|= OPAR;
7e00c42b BJ	469	if (tp->t_ispeed == B110)
7e00c42b BJ	470	lpr \|= TWOSB;
5074fa57 BJ	471	dzaddr->dzlpr = lpr;
	472	}
	473
	474	dzxint(tp)
3f3a34c3	475	register struct tty *tp;
5074fa57 BJ	476	{
5074fa57 BJ	477	register struct pdma *dp;
bea90e0b	478	register s, dz, unit;
5074fa57	479
7e00c42b	480	s = spl5(); /* block pdma interrupts */
3f3a34c3	481	dp = (struct pdma *)tp->t_addr;
941944c9 BJ	482	tp->t_state &= ~TS_BUSY;
	483	if (tp->t_state & TS_FLUSH)
	484	tp->t_state &= ~TS_FLUSH;
bea90e0b	485	else {
46014098	486	ndflush(&tp->t_outq, dp->p_mem-tp->t_outq.c_cf);
bea90e0b BJ	487	dp->p_end = dp->p_mem = tp->t_outq.c_cf;
bea90e0b BJ	488	}
5074fa57 BJ	489	if (tp->t_line)
	490	(*linesw[tp->t_line].l_start)(tp);
	491	else
	492	dzstart(tp);
bea90e0b BJ	493	dz = minor(tp->t_dev) >> 3;
bea90e0b BJ	494	unit = minor(tp->t_dev) & 7;
941944c9	495	if (tp->t_outq.c_cc == 0 \|\| (tp->t_state&TS_BUSY)==0)
bea90e0b BJ	496	if (dp->p_addr->dzcsr & DZ_32)
	497	dp->p_addr->dzlnen = (dz_lnen[dz] &= ~(1<<unit));
	498	else
	499	dp->p_addr->dztcr &= ~(1<<unit);
d3ebf5ee	500	splx(s);
5074fa57 BJ	501	}
	502
	503	dzstart(tp)
3f3a34c3	504	register struct tty *tp;
5074fa57 BJ	505	{
	506	register struct pdma *dp;
	507	register struct device *dzaddr;
3f3a34c3	508	register int cc;
bea90e0b	509	int s, dz, unit;
5074fa57	510
3f3a34c3	511	dp = (struct pdma *)tp->t_addr;
5074fa57	512	dzaddr = dp->p_addr;
3f3a34c3	513	s = spl5();
941944c9	514	if (tp->t_state & (TS_TIMEOUT\|TS_BUSY\|TS_TTSTOP))
5074fa57	515	goto out;
941944c9 BJ	516	if (tp->t_outq.c_cc <= TTLOWAT(tp)) {
	517	if (tp->t_state&TS_ASLEEP) {
	518	tp->t_state &= ~TS_ASLEEP;
	519	wakeup((caddr_t)&tp->t_outq);
	520	}
	521	if (tp->t_wsel) {
	522	selwakeup(tp->t_wsel, tp->t_state & TS_WCOLL);
	523	tp->t_wsel = 0;
	524	tp->t_state &= ~TS_WCOLL;
	525	}
5074fa57 BJ	526	}
	527	if (tp->t_outq.c_cc == 0)
	528	goto out;
bea90e0b	529	if ((tp->t_flags&RAW) \|\| (tp->t_local&LLITOUT))
5074fa57 BJ	530	cc = ndqb(&tp->t_outq, 0);
	531	else {
	532	cc = ndqb(&tp->t_outq, 0200);
	533	if (cc == 0) {
	534	cc = getc(&tp->t_outq);
7e00c42b	535	timeout(ttrstrt, (caddr_t)tp, (cc&0x7f) + 6);
941944c9	536	tp->t_state \|= TS_TIMEOUT;
5074fa57 BJ	537	goto out;
	538	}
	539	}
941944c9	540	tp->t_state \|= TS_BUSY;
5074fa57 BJ	541	dp->p_end = dp->p_mem = tp->t_outq.c_cf;
5074fa57 BJ	542	dp->p_end += cc;
bea90e0b BJ	543	dz = minor(tp->t_dev) >> 3;
	544	unit = minor(tp->t_dev) & 7;
	545	if (dzaddr->dzcsr & DZ_32)
	546	dzaddr->dzlnen = (dz_lnen[dz] \|= (1<<unit));
	547	else
	548	dzaddr->dztcr \|= (1<<unit);
3f3a34c3 BJ	549	out:
3f3a34c3 BJ	550	splx(s);
5074fa57 BJ	551	}
	552
	553	/*
	554	* Stop output on a line.
5074fa57 BJ	555	*/
	556	/ARGSUSED/
	557	dzstop(tp, flag)
3f3a34c3	558	register struct tty *tp;
5074fa57 BJ	559	{
	560	register struct pdma *dp;
	561	register int s;
	562
3f3a34c3	563	dp = (struct pdma *)tp->t_addr;
88d5b764	564	s = spl5();
941944c9	565	if (tp->t_state & TS_BUSY) {
5074fa57	566	dp->p_end = dp->p_mem;
941944c9 BJ	567	if ((tp->t_state&TS_TTSTOP)==0)
941944c9 BJ	568	tp->t_state \|= TS_FLUSH;
5074fa57 BJ	569	}
	570	splx(s);
	571	}
	572
bea90e0b BJ	573	dzmctl(dev, bits, how)
	574	dev_t dev;
	575	int bits, how;
5074fa57 BJ	576	{
5074fa57 BJ	577	register struct device *dzaddr;
bea90e0b BJ	578	register int unit, mbits;
	579	int b, s;
	580
	581	unit = minor(dev);
	582	b = 1<<(unit&7);
3f3a34c3	583	dzaddr = dzpdma[unit].p_addr;
bea90e0b BJ	584	s = spl5();
	585	if (dzaddr->dzcsr & DZ_32) {
	586	dzwait(dzaddr)
	587	DELAY(100); /* IS 100 TOO MUCH? */
	588	dzaddr->dzlcs = unit&7;
	589	DELAY(100);
	590	dzwait(dzaddr)
	591	DELAY(100);
	592	mbits = dzaddr->dzlcs;
	593	mbits &= 0177770;
	594	} else {
	595	mbits = (dzaddr->dzdtr & b) ? DZ_DTR : 0;
	596	mbits \|= (dzaddr->dzmsr & b) ? DZ_CD : 0;
	597	mbits \|= (dzaddr->dztbuf & b) ? DZ_RI : 0;
	598	}
	599	switch (how) {
	600	case DMSET:
	601	mbits = bits;
	602	break;
	603
	604	case DMBIS:
	605	mbits \|= bits;
	606	break;
	607
	608	case DMBIC:
	609	mbits &= ~bits;
	610	break;
	611
	612	case DMGET:
	613	(void) splx(s);
	614	return(mbits);
	615	}
	616	if (dzaddr->dzcsr & DZ_32) {
	617	mbits \|= DZ_ACK\|(unit&7);
	618	dzaddr->dzlcs = mbits;
	619	} else {
	620	if (mbits & DZ_DTR)
	621	dzaddr->dzdtr \|= b;
	622	else
	623	dzaddr->dzdtr &= ~b;
	624	}
	625	(void) splx(s);
	626	return(mbits);
5074fa57 BJ	627	}
	628
	629	dzscan()
	630	{
	631	register i;
	632	register struct device *dzaddr;
	633	register bit;
	634	register struct tty *tp;
bea90e0b	635	register car;
5074fa57 BJ	636
	637	for (i = 0; i < dz_cnt ; i++) {
	638	dzaddr = dzpdma[i].p_addr;
be2b272c BJ	639	if (dzaddr == 0)
be2b272c BJ	640	continue;
5074fa57 BJ	641	tp = &dz_tty[i];
5074fa57 BJ	642	bit = 1<<(i&07);
bea90e0b BJ	643	car = 0;
	644	if (dzsoftCAR[i>>3]&bit)
	645	car = 1;
	646	else if (dzaddr->dzcsr & DZ_32) {
	647	dzaddr->dzlcs = i&07;
	648	dzwait(dzaddr);
	649	car = dzaddr->dzlcs & DZ_CD;
	650	} else
	651	car = dzaddr->dzmsr&bit;
	652	if (car) {
5074fa57	653	/* carrier present */
941944c9	654	if ((tp->t_state & TS_CARR_ON) == 0) {
5074fa57	655	wakeup((caddr_t)&tp->t_rawq);
941944c9	656	tp->t_state \|= TS_CARR_ON;
5074fa57 BJ	657	}
5074fa57 BJ	658	} else {
941944c9	659	if ((tp->t_state&TS_CARR_ON) &&
7e00c42b	660	(tp->t_local&LNOHANG)==0) {
5074fa57	661	/* carrier lost */
941944c9	662	if (tp->t_state&TS_ISOPEN) {
dc44829a	663	gsignal(tp->t_pgrp, SIGHUP);
160cf9ed	664	gsignal(tp->t_pgrp, SIGCONT);
dc44829a	665	dzaddr->dzdtr &= ~bit;
cc343d94	666	flushtty(tp, FREAD\|FWRITE);
dc44829a	667	}
941944c9	668	tp->t_state &= ~TS_CARR_ON;
5074fa57	669	}
5074fa57 BJ	670	}
5074fa57 BJ	671	}
7780575a	672	timeout(dzscan, (caddr_t)0, 2*hz);
5074fa57	673	}
9dca4f86 BJ	674
	675	dztimer()
	676	{
88d5b764	677	int dz;
9dca4f86	678
a3cb8f60	679	for (dz = 0; dz < NDZ; dz++)
88d5b764	680	dzrint(dz);
9dca4f86	681	}
46014098 BJ	682
	683	/*
	684	* Reset state of driver if UBA reset was necessary.
0072a3c2	685	* Reset parameters and restart transmission on open lines.
46014098	686	*/
3f3a34c3	687	dzreset(uban)
5aa9d5ea	688	int uban;
46014098	689	{
3f3a34c3	690	register int unit;
46014098	691	register struct tty *tp;
6a1a96ff	692	register struct uba_device *ui;
46014098	693
a3cb8f60	694	for (unit = 0; unit < NDZLINE; unit++) {
5aa9d5ea RE	695	ui = dzinfo[unit >> 3];
	696	if (ui == 0 \|\| ui->ui_ubanum != uban \|\| ui->ui_alive == 0)
	697	continue;
b19fe459 BJ	698	if (unit%8 == 0)
b19fe459 BJ	699	printf(" dz%d", unit>>3);
3f3a34c3	700	tp = &dz_tty[unit];
941944c9	701	if (tp->t_state & (TS_ISOPEN\|TS_WOPEN)) {
3f3a34c3	702	dzparam(unit);
668cc26d	703	(void) dzmctl(unit, DZ_ON, DMSET);
941944c9	704	tp->t_state &= ~TS_BUSY;
0072a3c2	705	dzstart(tp);
46014098 BJ	706	}
	707	}
	708	dztimer();
46014098	709	}
a5cc519e	710	#endif