merge of 4.1b and 4.1c
[unix-history] / usr / src / sys / vax / uba / uba.c
CommitLineData
ca24e030 1/* uba.c 4.56 82/10/23 */
c14fd247
BJ
2
3#include "../h/param.h"
3f3a34c3 4#include "../h/systm.h"
c14fd247
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5#include "../h/map.h"
6#include "../h/pte.h"
c14fd247 7#include "../h/buf.h"
b7333467 8#include "../h/vm.h"
c14fd247
BJ
9#include "../h/dir.h"
10#include "../h/user.h"
11#include "../h/proc.h"
2e74ef16 12#include "../h/conf.h"
b7333467 13#include "../h/dk.h"
5d30e870 14#include "../h/kernel.h"
b7333467 15
896962b1
BJ
16#include "../vax/cpu.h"
17#include "../vax/mtpr.h"
18#include "../vax/nexus.h"
19#include "../vaxuba/ubareg.h"
20#include "../vaxuba/ubavar.h"
21
5af3f3f7
BJ
22#if VAX780
23char ubasr_bits[] = UBASR_BITS;
24#endif
25
b7333467
BJ
26/*
27 * Do transfer on device argument. The controller
28 * and uba involved are implied by the device.
29 * We queue for resource wait in the uba code if necessary.
30 * We return 1 if the transfer was started, 0 if it was not.
31 * If you call this routine with the head of the queue for a
32 * UBA, it will automatically remove the device from the UBA
33 * queue before it returns. If some other device is given
34 * as argument, it will be added to the request queue if the
35 * request cannot be started immediately. This means that
36 * passing a device which is on the queue but not at the head
37 * of the request queue is likely to be a disaster.
38 */
39ubago(ui)
5ab42896 40 register struct uba_device *ui;
b7333467 41{
5ab42896 42 register struct uba_ctlr *um = ui->ui_mi;
b7333467
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43 register struct uba_hd *uh;
44 register int s, unit;
45
46 uh = &uba_hd[um->um_ubanum];
47 s = spl6();
28ca05a9 48 if (um->um_driver->ud_xclu && uh->uh_users > 0 || uh->uh_xclu)
0801d37f 49 goto rwait;
b7333467
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50 um->um_ubinfo = ubasetup(um->um_ubanum, um->um_tab.b_actf->b_actf,
51 UBA_NEEDBDP|UBA_CANTWAIT);
0801d37f
BJ
52 if (um->um_ubinfo == 0)
53 goto rwait;
0801d37f 54 uh->uh_users++;
28ca05a9 55 if (um->um_driver->ud_xclu)
0801d37f 56 uh->uh_xclu = 1;
b7333467
BJ
57 splx(s);
58 if (ui->ui_dk >= 0) {
59 unit = ui->ui_dk;
60 dk_busy |= 1<<unit;
cc7ff771
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61 dk_xfer[unit]++;
62 dk_wds[unit] += um->um_tab.b_actf->b_actf->b_bcount>>6;
b7333467
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63 }
64 if (uh->uh_actf == ui)
65 uh->uh_actf = ui->ui_forw;
66 (*um->um_driver->ud_dgo)(um);
b7333467 67 return (1);
0801d37f
BJ
68rwait:
69 if (uh->uh_actf != ui) {
70 ui->ui_forw = NULL;
71 if (uh->uh_actf == NULL)
72 uh->uh_actf = ui;
73 else
74 uh->uh_actl->ui_forw = ui;
75 uh->uh_actl = ui;
76 }
77 splx(s);
78 return (0);
79}
80
81ubadone(um)
5ab42896 82 register struct uba_ctlr *um;
0801d37f
BJ
83{
84 register struct uba_hd *uh = &uba_hd[um->um_ubanum];
85
28ca05a9 86 if (um->um_driver->ud_xclu)
0801d37f
BJ
87 uh->uh_xclu = 0;
88 uh->uh_users--;
0801d37f 89 ubarelse(um->um_ubanum, &um->um_ubinfo);
b7333467 90}
c14fd247
BJ
91
92/*
3f3a34c3
BJ
93 * Allocate and setup UBA map registers, and bdp's
94 * Flags says whether bdp is needed, whether the caller can't
95 * wait (e.g. if the caller is at interrupt level).
c14fd247 96 *
b7333467 97 * Return value:
c14fd247
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98 * Bits 0-8 Byte offset
99 * Bits 9-17 Start map reg. no.
100 * Bits 18-27 No. mapping reg's
101 * Bits 28-31 BDP no.
102 */
3f3a34c3
BJ
103ubasetup(uban, bp, flags)
104 struct buf *bp;
c14fd247 105{
3f3a34c3 106 register struct uba_hd *uh = &uba_hd[uban];
bc3a8383 107 register int temp;
c14fd247
BJ
108 int npf, reg, bdp;
109 unsigned v;
110 register struct pte *pte, *io;
111 struct proc *rp;
112 int a, o, ubinfo;
113
10f66600
SL
114#if VAX730
115 if (cpu == VAX_730)
a3812a04
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116 flags &= ~UBA_NEEDBDP;
117#endif
c14fd247
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118 v = btop(bp->b_un.b_addr);
119 o = (int)bp->b_un.b_addr & PGOFSET;
120 npf = btoc(bp->b_bcount + o) + 1;
121 a = spl6();
5d30e870 122 while ((reg = rmalloc(uh->uh_map, (long)npf)) == 0) {
dd56673b
BJ
123 if (flags & UBA_CANTWAIT) {
124 splx(a);
3f3a34c3 125 return (0);
dd56673b 126 }
3f3a34c3
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127 uh->uh_mrwant++;
128 sleep((caddr_t)uh->uh_map, PSWP);
c14fd247 129 }
c14fd247 130 bdp = 0;
3f3a34c3
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131 if (flags & UBA_NEEDBDP) {
132 while ((bdp = ffs(uh->uh_bdpfree)) == 0) {
133 if (flags & UBA_CANTWAIT) {
5d30e870 134 rmfree(uh->uh_map, (long)npf, (long)reg);
dd56673b 135 splx(a);
3f3a34c3
BJ
136 return (0);
137 }
138 uh->uh_bdpwant++;
139 sleep((caddr_t)uh->uh_map, PSWP);
c14fd247 140 }
658110d5 141 uh->uh_bdpfree &= ~(1 << (bdp-1));
64614526
BJ
142 } else if (flags & UBA_HAVEBDP)
143 bdp = (flags >> 28) & 0xf;
c14fd247 144 splx(a);
658110d5 145 reg--;
c14fd247 146 ubinfo = (bdp << 28) | (npf << 18) | (reg << 9) | o;
5ab42896 147 temp = (bdp << 21) | UBAMR_MRV;
c14fd247 148 if (bdp && (o & 01))
5ab42896 149 temp |= UBAMR_BO;
309cfbf4
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150 rp = bp->b_flags&B_DIRTY ? &proc[2] : bp->b_proc;
151 if ((bp->b_flags & B_PHYS) == 0)
da1392b6 152 pte = &Sysmap[btop(((int)bp->b_un.b_addr)&0x7fffffff)];
309cfbf4
BJ
153 else if (bp->b_flags & B_UAREA)
154 pte = &rp->p_addr[v];
155 else if (bp->b_flags & B_PAGET)
156 pte = &Usrptmap[btokmx((struct pte *)bp->b_un.b_addr)];
157 else
158 pte = vtopte(rp, v);
159 io = &uh->uh_uba->uba_map[reg];
160 while (--npf != 0) {
161 if (pte->pg_pfnum == 0)
162 panic("uba zero uentry");
163 *(int *)io++ = pte++->pg_pfnum | temp;
c14fd247
BJ
164 }
165 *(int *)io++ = 0;
166 return (ubinfo);
167}
168
c14fd247 169/*
b7333467 170 * Non buffer setup interface... set up a buffer and call ubasetup.
c14fd247 171 */
3f3a34c3 172uballoc(uban, addr, bcnt, flags)
a0eab615 173 int uban;
c14fd247 174 caddr_t addr;
a0eab615 175 int bcnt, flags;
c14fd247 176{
89e0f717 177 struct buf ubabuf;
c14fd247 178
c14fd247
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179 ubabuf.b_un.b_addr = addr;
180 ubabuf.b_flags = B_BUSY;
181 ubabuf.b_bcount = bcnt;
89e0f717 182 /* that's all the fields ubasetup() needs */
3f3a34c3 183 return (ubasetup(uban, &ubabuf, flags));
c14fd247
BJ
184}
185
b28deaf8 186/*
b7333467
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187 * Release resources on uba uban, and then unblock resource waiters.
188 * The map register parameter is by value since we need to block
189 * against uba resets on 11/780's.
b28deaf8 190 */
3f3a34c3 191ubarelse(uban, amr)
b28deaf8 192 int *amr;
c14fd247 193{
3f3a34c3 194 register struct uba_hd *uh = &uba_hd[uban];
b7333467 195 register int bdp, reg, npf, s;
b28deaf8 196 int mr;
c14fd247 197
b7333467
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198 /*
199 * Carefully see if we should release the space, since
200 * it may be released asynchronously at uba reset time.
201 */
202 s = spl6();
b28deaf8
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203 mr = *amr;
204 if (mr == 0) {
b7333467
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205 /*
206 * A ubareset() occurred before we got around
207 * to releasing the space... no need to bother.
208 */
209 splx(s);
b28deaf8
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210 return;
211 }
88149598 212 *amr = 0;
b7333467 213 splx(s); /* let interrupts in, we're safe for a while */
c14fd247
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214 bdp = (mr >> 28) & 0x0f;
215 if (bdp) {
27bf6b55 216 switch (cpu) {
5aa9d5ea
RE
217#if VAX780
218 case VAX_780:
5ab42896 219 uh->uh_uba->uba_dpr[bdp] |= UBADPR_BNE;
5aa9d5ea
RE
220 break;
221#endif
222#if VAX750
223 case VAX_750:
5ab42896
BJ
224 uh->uh_uba->uba_dpr[bdp] |=
225 UBADPR_PURGE|UBADPR_NXM|UBADPR_UCE;
5aa9d5ea
RE
226 break;
227#endif
228 }
b7333467 229 uh->uh_bdpfree |= 1 << (bdp-1); /* atomic */
3f3a34c3
BJ
230 if (uh->uh_bdpwant) {
231 uh->uh_bdpwant = 0;
232 wakeup((caddr_t)uh->uh_map);
c14fd247
BJ
233 }
234 }
b7333467
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235 /*
236 * Put back the registers in the resource map.
237 * The map code must not be reentered, so we do this
238 * at high ipl.
239 */
c14fd247
BJ
240 npf = (mr >> 18) & 0x3ff;
241 reg = ((mr >> 9) & 0x1ff) + 1;
b7333467 242 s = spl6();
5d30e870 243 rmfree(uh->uh_map, (long)npf, (long)reg);
b7333467
BJ
244 splx(s);
245
246 /*
247 * Wakeup sleepers for map registers,
248 * and also, if there are processes blocked in dgo(),
249 * give them a chance at the UNIBUS.
250 */
3f3a34c3
BJ
251 if (uh->uh_mrwant) {
252 uh->uh_mrwant = 0;
253 wakeup((caddr_t)uh->uh_map);
c14fd247 254 }
b7333467
BJ
255 while (uh->uh_actf && ubago(uh->uh_actf))
256 ;
c14fd247
BJ
257}
258
27bf6b55 259ubapurge(um)
5ab42896 260 register struct uba_ctlr *um;
27bf6b55
BJ
261{
262 register struct uba_hd *uh = um->um_hd;
263 register int bdp = (um->um_ubinfo >> 28) & 0x0f;
264
265 switch (cpu) {
266#if VAX780
267 case VAX_780:
5ab42896 268 uh->uh_uba->uba_dpr[bdp] |= UBADPR_BNE;
27bf6b55
BJ
269 break;
270#endif
271#if VAX750
272 case VAX_750:
5ab42896 273 uh->uh_uba->uba_dpr[bdp] |= UBADPR_PURGE|UBADPR_NXM|UBADPR_UCE;
27bf6b55
BJ
274 break;
275#endif
276 }
277}
278
9305c2b9
BJ
279ubainitmaps(uhp)
280 register struct uba_hd *uhp;
281{
282
5d30e870 283 rminit(uhp->uh_map, (long)NUBMREG, (long)1, "uba", UAMSIZ);
9305c2b9
BJ
284 switch (cpu) {
285#if VAX780
286 case VAX_780:
287 uhp->uh_bdpfree = (1<<NBDP780) - 1;
288 break;
289#endif
290#if VAX750
291 case VAX_750:
292 uhp->uh_bdpfree = (1<<NBDP750) - 1;
293 break;
294#endif
10f66600
SL
295#if VAX730
296 case VAX_730:
9305c2b9
BJ
297 break;
298#endif
299 }
300}
301
b7333467
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302/*
303 * Generate a reset on uba number uban. Then
304 * call each device in the character device table,
305 * giving it a chance to clean up so as to be able to continue.
306 */
3f3a34c3 307ubareset(uban)
b7333467 308 int uban;
2e74ef16 309{
2e74ef16 310 register struct cdevsw *cdp;
a3cb8f60 311 register struct uba_hd *uh = &uba_hd[uban];
49c84d3f 312 int s;
2e74ef16 313
4ea0bfc4 314 s = spl6();
a3cb8f60
BJ
315 uh->uh_users = 0;
316 uh->uh_zvcnt = 0;
317 uh->uh_xclu = 0;
a3cb8f60
BJ
318 uh->uh_actf = uh->uh_actl = 0;
319 uh->uh_bdpwant = 0;
320 uh->uh_mrwant = 0;
9305c2b9 321 ubainitmaps(uh);
a3cb8f60
BJ
322 wakeup((caddr_t)&uh->uh_bdpwant);
323 wakeup((caddr_t)&uh->uh_mrwant);
5ab42896
BJ
324 printf("uba%d: reset", uban);
325 ubainit(uh->uh_uba);
2e74ef16 326 for (cdp = cdevsw; cdp->d_open; cdp++)
3f3a34c3 327 (*cdp->d_reset)(uban);
4c3f4cb1
BJ
328#ifdef INET
329 ifubareset(uban);
330#endif
2e74ef16 331 printf("\n");
4ea0bfc4 332 splx(s);
2e74ef16 333}
3f3a34c3 334
b7333467
BJ
335/*
336 * Init a uba. This is called with a pointer
337 * rather than a virtual address since it is called
338 * by code which runs with memory mapping disabled.
339 * In these cases we really don't need the interrupts
340 * enabled, but since we run with ipl high, we don't care
341 * if they are, they will never happen anyways.
342 */
5aa9d5ea
RE
343ubainit(uba)
344 register struct uba_regs *uba;
3f3a34c3
BJ
345{
346
5ab42896
BJ
347 switch (cpu) {
348#if VAX780
d2f165e5 349 case VAX_780:
5ab42896
BJ
350 uba->uba_cr = UBACR_ADINIT;
351 uba->uba_cr = UBACR_IFS|UBACR_BRIE|UBACR_USEFIE|UBACR_SUEFIE;
352 while ((uba->uba_cnfgr & UBACNFGR_UBIC) == 0)
353 ;
354 break;
355#endif
356#if VAX750
d2f165e5 357 case VAX_750:
a3812a04 358#endif
10f66600
SL
359#if VAX730
360 case VAX_730:
fed9edca 361#endif
10f66600 362#if defined(VAX750) || defined(VAX730)
fed9edca
BJ
363 mtpr(IUR, 0);
364 /* give devices time to recover from power fail */
365/* THIS IS PROBABLY UNNECESSARY */
366 DELAY(500000);
367/* END PROBABLY UNNECESSARY */
5ab42896
BJ
368 break;
369#endif
370 }
3f3a34c3
BJ
371}
372
39d536e6 373#ifdef VAX780
3e04ba6a
BJ
374int ubawedgecnt = 10;
375int ubacrazy = 500;
b7333467
BJ
376/*
377 * This routine is called by the locore code to
378 * process a UBA error on an 11/780. The arguments are passed
379 * on the stack, and value-result (through some trickery).
380 * In particular, the uvec argument is used for further
381 * uba processing so the result aspect of it is very important.
382 * It must not be declared register.
383 */
5aa9d5ea 384/*ARGSUSED*/
3f3a34c3
BJ
385ubaerror(uban, uh, xx, uvec, uba)
386 register int uban;
387 register struct uba_hd *uh;
388 int uvec;
389 register struct uba_regs *uba;
390{
391 register sr, s;
392
393 if (uvec == 0) {
394 uh->uh_zvcnt++;
395 if (uh->uh_zvcnt > 250000) {
5af3f3f7 396 printf("uba%d: too many zero vectors\n");
3f3a34c3
BJ
397 ubareset(uban);
398 }
399 uvec = 0;
400 return;
401 }
402 if (uba->uba_cnfgr & NEX_CFGFLT) {
5af3f3f7
BJ
403 printf("uba%d: sbi fault sr=%b cnfgr=%b\n",
404 uban, uba->uba_sr, ubasr_bits,
d2f165e5 405 uba->uba_cnfgr, NEXFLT_BITS);
3f3a34c3
BJ
406 ubareset(uban);
407 uvec = 0;
408 return;
409 }
410 sr = uba->uba_sr;
411 s = spl7();
ec28fe15
BJ
412 printf("uba%d: uba error sr=%b fmer=%x fubar=%o\n",
413 uban, uba->uba_sr, ubasr_bits, uba->uba_fmer, 4*uba->uba_fubar);
3f3a34c3
BJ
414 splx(s);
415 uba->uba_sr = sr;
5ab42896 416 uvec &= UBABRRVR_DIV;
3e04ba6a
BJ
417 if (++uh->uh_errcnt % ubawedgecnt == 0) {
418 if (uh->uh_errcnt > ubacrazy)
419 panic("uba crazy");
420 printf("ERROR LIMIT ");
421 ubareset(uban);
422 uvec = 0;
423 return;
424 }
3f3a34c3
BJ
425 return;
426}
427#endif
1c1f6ecf
BF
428
429/*
430 * This routine is called by a driver for a device with on-board Unibus
431 * memory. It removes the memory block from the Unibus resource map
432 * and clears the map registers for the block.
433 *
434 * Arguments are the Unibus number, the Unibus address of the memory
a26646de
BF
435 * block, its size in blocks of 512 bytes, and a flag indicating whether
436 * to allocate the unibus space form the resource map or whether it already
437 * has been.
1c1f6ecf 438 *
a26646de 439 * Returns > 0 if successful, 0 if not.
1c1f6ecf 440 */
bc3a8383
BJ
441ubamem(uban, addr, size, doalloc)
442 int uban, addr, size, doalloc;
1c1f6ecf
BF
443{
444 register struct uba_hd *uh = &uba_hd[uban];
445 register int *m;
446 register int i, a, s;
447
bc3a8383 448 if (doalloc) {
a26646de
BF
449 s = spl6();
450 a = rmget(uh->uh_map, size, (addr>>9)+1); /* starts at ONE! */
451 splx(s);
452 } else
453 a = (addr>>9)+1;
1c1f6ecf 454 if (a) {
a26646de 455 m = (int *) &uh->uh_uba->uba_map[a-1];
1c1f6ecf
BF
456 for (i=0; i<size; i++)
457 *m++ = 0; /* All off, especially 'valid' */
a26646de
BF
458#if VAX780
459 if (cpu == VAX_780) { /* map disable */
460 i = (addr+size*512+8191)/8192;
461 uh->uh_uba->uba_cr |= i<<26;
462 }
463#endif
1c1f6ecf
BF
464 }
465 return(a);
466}
8e61f556
SL
467
468/*
469 * Map a virtual address into users address space. Actually all we
470 * do is turn on the user mode write protection bits for the particular
471 * page of memory involved.
472 */
473maptouser(vaddress)
474 caddr_t vaddress;
475{
476
477 Sysmap[(((unsigned)(vaddress))-0x80000000) >> 9].pg_prot = (PG_UW>>27);
478}
479
480unmaptouser(vaddress)
481 caddr_t vaddress;
482{
483
484 Sysmap[(((unsigned)(vaddress))-0x80000000) >> 9].pg_prot = (PG_KW>>27);
485}