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[unix-history] / sys / i386 / doc / ata / ata-11
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DG		 111. Timing
2
311.1 Deskewing
4
5The host shall provide cable deskewing for all signals originating from the
6controller. The drive shall provide cable deskewing for all signals
7originating at the host.
8
911.2 Symbols
10
11Certain symbols are used in the timing diagrams. These symbols and their
12respective definitions are listed below.
13
14 / or \ - signal transition (asserted or negated) *
15 < or > - data transition (asserted or negated)
16 XXXXXX - undefined but not necessarily released
17 . . . - the "other" condition if a signal is shown with no change
18 #n - used to number the sequence in which events occur e.g. #a, #b
19 _ _ __
20__/_ _/ - a degree of uncertainty as to when a signal may be asserted
21
22__ _ _
23 \_ _\__ - a degree of uncertainty as to when a signal may be negated
24
25.. T - Nominal Clock Period
26..
27 * All signals are shown with the Asserted condition facing to the top of
28 the page. The negated condition is shown towards the bottom of the page
29 relative to the asserted condition.
30
31..Within each figure the timing terms i.e. tA, tB etc are repeated. There is
32..no continuity of definition of tA from one figure to another.
33..
3411.3 Terms
35
36The interface uses a mixture of negative and positive signals for control and
37data. The terms asserted and negated are used for consistency and are
38independent of electrical characteristics.
39
40In all timing diagrams, the lower line indicates negated, and the upper line
41indicates asserted e.g. the following illustrates the representation of a
42signal named TEST going from negated to asserted and back to negated, based on
43the polarity of the signal.
44
45 Assert Negate
46 | |
47 Bit Setting=1 |__________|
48 Bit Setting=0 TEST _____/ \_______
49
50 Assert Negate
51 | |
52 Bit Setting=0 |__________|
53 Bit Setting=1 TEST- _____/ \_______
54
55.. Processor I/O Write, 16 Bit:
5611.4 Data Transfers
57
58Figure 11-1 defines the relationships between the interface signals for both
5916-bit and 8-bit data transfers.
60
61 |<------------ t0 -------------------->|
62 __________________________________________ |
63 Address Valid *1 ...../ \________
64 |<-t1->| ->| t9 |<-
65 ->|t7|<- |<----------- t2 ------------->| ->|t8|<-
66 | | |______________________________| | |_____
67 DIOR-/DIOW- ____________/ \_______/
68 | | |_ _ _ _ _ _ _ _ _ _ _____________ |
69 Write Data Valid *2__________/_ _ _ _ _ _ _ _ _ _/ \__________
70 | | | |<--t3---->| |
71 | | | ->|t4|<- |
72 | | |_ _ _ _ _ _ _ _ _ _ _ ___________ |
73 Read Data Valid *2__________/_ _ _ _ _ _ _ _ _ _ _/ | \__________
74 | | | |<--t5-->| | |
75 | | | ->|t6|<- |
76 | | | | | |
77 | |__________________________________________|
78 IOCS16- ________/ \_____
79
80 *1 Drive Address consists of signals CS1FX-, CS3FX- and DA2-0
81 *2 Data consists of DD0-15 (16-bit) or DD0-7 (8-bit)
82
83 +------------------------------------------+-------+-------+-------+
84 | PIO | Mode 0| Mode 1| Mode 2|
85 | Timing Parameters | nsec | nsec | nsec |
86 +----+------------------------------------------+-------+-------+-------+
87 | t0 | Cycle Time (Min) | 600 | 383 | 240 |
88 | t1 | Address Valid to DIOR-/DIOW- Setup (Min) | 70 | 50 | 30 |
89 | t2 | DIOR-/DIOW- 16-bit (Min) | 165 | 125 | 100 |
90 | | Pulse Width 8-bit (Min) | 290 | 290 | 290 |
91 | t3 | DIOW- Data Setup (Min) | 60 | 45 | 30 |
92 | t4 | DIOW- Data Hold (Min) | 30 | 20 | 15 |
93 | t5 | DIOR- Data Setup (Min) | 50 | 35 | 20 |
94 | t6 | DIOR- Data Hold (Min) | 5 | 5 | 5 |
95 | t7 | Addr Valid to IOCS16- Assertion (Max) | 90 | 50 | 40 |
96 | t8 | Addr Valid to IOCS16- Negation (Max) | 60 | 45 | 30 |
97 | t9 | DIOR-/DIOW- to Address Valid Hold (Min) | 20 | 15 | 10 |
98 +----+------------------------------------------+-------+-------+-------+
99..rm102
100.. NOTE: These are minimum acceptable interface timing requirements.
101
102 FIGURE 11-1: PIO DATA TRANSFER TO/FROM DRIVE
103
104 ___________________________________
105 DIOR-/DIOW- __________/ \______________
106 |
107 |<- tA ->|<--- tB ---->|
108 ___________________| |_____________________
109 IORDY \___________________/
110
111 Label Description Min Max Units
112
113 tA IORDY Setup time - 35 nsecs
114 tB IORDY Pulse Width - 1,250 nsecs
115
116 WARNING: The use of IORDY for data transfers is a system integration issue
117 which requires control of both ends of the cable.
118
119 FIGURE 11-2: IORDY TIMING REQUIRMENTS
120
121 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
122
123 |<----------------------- t0 ---------------------->|
124 ____________ _______
125 DMARQ ___/ \______________________________________/ |
126 |<- tC ->| |
127 |_____________________________________________ |___
128 DMACK- _______/ \_____/
129 |<--- tI --->|________________|<----- tJ -----| |
130 DIOR-/DIOW- ____________________/ \_________________________
131 | | | |
132 | |<------ tD ---->| |
133 Read | ______________ |
134 DD0-15 -------------------------------<______________>----------------
135 | |<-- tE -->| |<- tF ->| |
136 Write | _________________________ |
137 DD0-15 --------------------------<_________________________>-----------
138 | | | | |
139 | |<-- tG -->|<-- tH -->| |
140
141 +----------------------------------+-------+-------+-------+
142 | DMA | Mode 0| Mode 1| Mode 2|
143 | Timing Parameters | nsec | nsec | nsec |
144 +----+----------------------------------+-------+-------+-------+
145 | t0 | Cycle Time (Min) | 960 | 480 | 240 |
146 | tC | DMACK to DMREQ Delay (Max) | 200 | 100 | 80 |
147 | tD | DIOR-/DIOW- 16-bit (Min) | 480 | 240 | 120 |
148 | tE | DIOR- Data Setup (Min) | 250 | 150 | 50 |
149 | tF | DIOR- Data Hold (Min) | 5 | 5 | 5 |
150 | tG | DIOW- Data Setup (Min) | 250 | 100 | 35 |
151 | tH | DIOW- Data Hold (Min) | 50 | 30 | 20 |
152 | tI | DMACK to DIOR-/DIOW- Setup (Min) | 0 | 0 | 0 |
153 | tJ | DIOR-/DIOW- to DMACK Hold (Min) | 0 | 0 | 0 |
154 +----+----------------------------------+-------+-------+-------+
155
156 FIGURE 11-3: DMA DATA TRANSFER
157
15811.5 Power On and Hard Reset
159
160 ______
161 RESET- _____/ \_____________________________________________________
162 |<-tM->|
163 | | Drive 0
164 _ _ _ _ _ _ _ _______ _ _ _ _ _ _ _ _ _ _ _ _ _|
165 BSY _ _ _ _ _ _ _/ \_ _ _ _ _ *1 _ _ _ _ _ _\________________
166 ->|tN|<-
167 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
168 DASP- _ _ _ _ _ _ _ _\_______/_ _ _ _ *2 _ _ _ _ _ _ _ _ _ _\=== *3 ==
169 ->| tP |<- | |_ _ _ __________
170 Control Registers_______________________________________/_ _ _ /
171 | | |
172 | | | Drive 1
173 _ _ _ _ _ _ _ _ _________________________________|
174 BSY _ _ _ _ _ _ _ _/ \________________
175 _ _ _ _ _ _ _ _ _ _ ______ _ _ _ _ _
176 PDIAG- _ _ _ _ _ _ _ _ _ _\____________________________/ \_ _ _ _ _
177 | | | |<----------- tQ -------->|
178 _ _ _ _ _ _ _ _ _ _________________________ _ _ _
179 DASP- _ _ _ _ _ _ _ _ _\_____/ \ _ _ _\=== *3 ==
180 |<- tR ->|<------------ tS -------------->|
181 _ _ _ __________
182 Control Registers_______________________________________/_ _ _ /
183
184 *1 Drive 0 can set BSY=0 if Drive 1 not present
185 *2 Drive 0 can use DASP- to indicate it is active if Drive 1 is not
186 present
187 *3 DASP- can be asserted to indicate that the drive is active
188 +-------------------+------------+
189 | Label | Units |
190 +-------------------+------------+
191 | tM (Min) | 25 usec |
192 | tN (Max) | 400 nsec |
193 | tP (Max) | 1 msec |
194 | tQ (Max) | 30 secs |
195 | tR Drive 0 (Max) | 450 msec |
196 | tR Drive 1 (Max) | 400 msec |
197 | tS (Max) | 30.5 secs |
198 +-------------------+------------+
199
200 FIGURE 11-4 RESET SEQUENCE
201
Continuous source code history from original PDP-7 UNIX to FreeBSD 2, the first fully unencumbered FreeBSD release.