Commit | Line | Data |
---|---|---|
5ab036bb | 1 | /* ubareg.h 4.8 81/02/19 */ |
1cb3d36a BJ |
2 | |
3 | /* | |
15b39647 | 4 | * UNIBUS adaptor |
1cb3d36a | 5 | */ |
ca89a8ee BJ |
6 | #if VAX750 |
7 | #define UBA750 ((struct uba_regs *)0xf30000) | |
8 | #define UMEM750 ((u_short *)0xfc0000) | |
9 | #endif | |
1cb3d36a | 10 | |
10a50234 | 11 | #if VAX780 |
1cb3d36a BJ |
12 | /* |
13 | * UBA registers | |
14 | */ | |
1cb3d36a BJ |
15 | struct uba_regs |
16 | { | |
17 | int uba_cnfgr; | |
18 | int uba_cr; | |
19 | int uba_sr; | |
20 | int uba_dcr; | |
21 | int uba_fmer; | |
22 | int uba_fubar; | |
23 | int pad1[2]; | |
24 | int uba_brsvr[4]; | |
25 | int uba_brrvr[4]; | |
26 | int uba_dpr[16]; | |
27 | int pad2[480]; | |
28 | struct pte uba_map[496]; | |
10a50234 BJ |
29 | int pad3[16]; |
30 | }; | |
31 | ||
32 | /* UBA control register, UBACR */ | |
33 | #define UBA_MRD16 0x40000000 /* map reg disable bit 4 */ | |
34 | #define UBA_MRD8 0x20000000 /* map reg disable bit 3 */ | |
35 | #define UBA_MRD4 0x10000000 /* map reg disable bit 2 */ | |
36 | #define UBA_MRD2 0x08000000 /* map reg disable bit 1 */ | |
37 | #define UBA_MRD1 0x04000000 /* map reg disable bit 0 */ | |
38 | #define UBA_IFS 0x00000040 /* interrupt field switch */ | |
39 | #define UBA_BRIE 0x00000020 /* BR interrupt enable */ | |
40 | #define UBA_USEFIE 0x00000010 /* UNIBUS to SBI error field IE */ | |
41 | #define UBA_SUEFIE 0x00000008 /* SBI to UNIBUS error field IE */ | |
42 | #define UBA_CNFIE 0x00000004 /* configuration IE */ | |
43 | #define UBA_UPF 0x00000002 /* UNIBUS power fail */ | |
44 | #define UBA_ADINIT 0x00000001 /* adapter init */ | |
45 | ||
46 | /* UBA status register, UASR */ | |
47 | #define UBA_BR7FULL 0x08000000 /* BR7 receive vector reg full */ | |
48 | #define UBA_BR6FULL 0x04000000 /* BR6 receive vector reg full */ | |
49 | #define UBA_BR5FULL 0x02000000 /* BR5 receive vector reg full */ | |
50 | #define UBA_BR4FULL 0x01000000 /* BR4 receive vector reg full */ | |
51 | #define UBA_RDTO 0x00000400 /* UNIBUS to SBI read data timeout */ | |
52 | #define UBA_RDS 0x00000200 /* read data substitute */ | |
53 | #define UBA_CRD 0x00000100 /* corrected read data */ | |
54 | #define UBA_CXTER 0x00000080 /* command transmit error */ | |
55 | #define UBA_CXTMO 0x00000040 /* command transmit timeout */ | |
56 | #define UBA_DPPE 0x00000020 /* data path parity error */ | |
57 | #define UBA_IVMR 0x00000010 /* invalid map register */ | |
58 | #define UBA_MRPF 0x00000008 /* map register parity failure */ | |
59 | #define UBA_LEB 0x00000004 /* lost error */ | |
60 | #define UBA_UBSTO 0x00000002 /* UNIBUS select timeout */ | |
61 | #define UBA_UBSSTO 0x00000001 /* UNIBUS slave sync timeout */ | |
62 | ||
63 | /* BR receive vector register, BRRVR */ | |
64 | #define UBA_AIRI 0x80000000 /* adapter interrupt request */ | |
65 | #define UBA_DIV 0x0000ffff /* device interrupt vector field */ | |
66 | #endif | |
67 | ||
68 | /* data path register, DPR */ | |
69 | #if VAX780 | |
70 | #define UBA_BNE 0x80000000 /* buffer not empty - purge */ | |
71 | #define UBA_BTE 0x40000000 /* buffer transfer error */ | |
72 | #define UBA_DPF 0x20000000 /* DP function (RO) */ | |
73 | #define UBA_BS 0x007f0000 /* buffer state field */ | |
74 | #define UBA_BUBA 0x0000ffff /* buffered UNIBUS address */ | |
75 | #endif | |
76 | #if VAX750 | |
77 | #define UBA_ERROR 0x20000000 | |
78 | #define UBA_NXM 0x40000000 | |
79 | #define UBA_UCE 0x20000000 | |
80 | #define UBA_PURGE 0x00000001 | |
81 | #endif | |
82 | ||
83 | /* map register, MR */ | |
84 | #define UBA_MRV 0x80000000 /* map register valid */ | |
85 | #define UBA_BO 0x02000000 /* byte offset bit */ | |
86 | #define UBA_DPDB 0x01e00000 /* data path designator field */ | |
87 | #define UBA_SBIPFN 0x000fffff /* SBI page address field */ | |
88 | ||
89 | #define UBA_DPSHIFT 21 /* shift to data path designator */ | |
90 | ||
91 | /* | |
ca89a8ee BJ |
92 | * Each UNIBUS mass storage controller has uba_minfo structure, |
93 | * and a uba_dinfo structure (as below) for each attached drive. | |
10a50234 | 94 | */ |
15b39647 | 95 | struct uba_minfo { |
ca89a8ee BJ |
96 | struct uba_driver *um_driver; |
97 | short um_ctlr; /* controller index in driver */ | |
10a50234 BJ |
98 | short um_ubanum; /* the uba it is on */ |
99 | short um_alive; /* controller exists */ | |
ca89a8ee | 100 | int (**um_intr)(); /* interrupt handler(s) */ |
10a50234 | 101 | caddr_t um_addr; /* address of device in i/o space */ |
ca89a8ee | 102 | struct uba_hd *um_hd; |
15b39647 BJ |
103 | int um_cmd; /* communication to dgo() */ |
104 | int um_ubinfo; /* save unibus registers, etc */ | |
ca89a8ee | 105 | struct buf um_tab; /* queue for this controller */ |
1cb3d36a | 106 | }; |
10a50234 | 107 | /* |
ca89a8ee BJ |
108 | * Each UNIBUS device has a uba_dinfo structure. |
109 | * If a controller has many drives attached, then there will | |
110 | * be several uba_dinfo structures associated with a single uba_minfo | |
10a50234 BJ |
111 | * structure. |
112 | */ | |
15b39647 | 113 | struct uba_dinfo { |
10a50234 | 114 | struct uba_driver *ui_driver; |
10a50234 | 115 | short ui_unit; /* unit number on the system */ |
ca89a8ee | 116 | short ui_ctlr; /* mass ctlr number; -1 if none */ |
10a50234 BJ |
117 | short ui_ubanum; /* the uba it is on */ |
118 | short ui_slave; /* slave on controller */ | |
119 | int (**ui_intr)(); /* interrupt handler(s) */ | |
120 | caddr_t ui_addr; /* address of device in i/o space */ | |
15b39647 BJ |
121 | short ui_dk; /* if init 1 set to number for iostat */ |
122 | short ui_flags; /* param to device init. */ | |
10a50234 BJ |
123 | short ui_alive; /* device exists */ |
124 | short ui_type; /* driver specific type information */ | |
10a50234 | 125 | caddr_t ui_physaddr; /* phys addr, for standalone (dump) code */ |
15b39647 | 126 | struct uba_dinfo *ui_forw; |
10a50234 BJ |
127 | /* if the driver isn't also a controller, this is the controller it is on */ |
128 | struct uba_minfo *ui_mi; | |
129 | struct uba_hd *ui_hd; | |
130 | }; | |
131 | ||
132 | #define NUBA780 4 | |
133 | #define NUBA750 1 | |
134 | #if VAX780 | |
135 | #define MAXNUBA 4 | |
136 | #else | |
137 | #define MAXNUBA 1 | |
138 | #endif | |
466a1b4c | 139 | |
10a50234 | 140 | /* |
ca89a8ee BJ |
141 | * This structure exists per-uba. |
142 | * | |
143 | * N.B.: THE SIZE AND SHAPE OF THIS STRUCTURE IS KNOWN IN uba.m. | |
10a50234 BJ |
144 | */ |
145 | struct uba_hd { | |
146 | int uh_active; /* bit per device transferring */ | |
147 | struct uba_regs *uh_uba; /* virt addr of uba */ | |
148 | struct uba_regs *uh_physuba; /* phys addr of uba */ | |
149 | int (**uh_vec)(); /* interrupt vector */ | |
15b39647 BJ |
150 | struct uba_dinfo *uh_actf; /* head of queue to transfer */ |
151 | struct uba_dinfo *uh_actl; /* tail of queue to transfer */ | |
10a50234 BJ |
152 | short uh_mrwant; /* someone is waiting for map reg */ |
153 | short uh_bdpwant; /* someone awaits bdp's */ | |
154 | int uh_bdpfree; /* free bdp's */ | |
155 | int uh_hangcnt; /* number of ticks hung */ | |
156 | int uh_zvcnt; /* number of 0 vectors */ | |
ca89a8ee BJ |
157 | #define UAMSIZ 50 |
158 | struct map *uh_map; | |
10a50234 | 159 | } uba_hd[MAXNUBA]; |
10a50234 | 160 | /* |
ca89a8ee | 161 | * Each UNIBUS driver defines entries for a set of routines |
10a50234 BJ |
162 | * as well as an array of types which are acceptable to it. |
163 | */ | |
164 | struct uba_driver { | |
165 | int (*ud_cntrlr)(); /* see if a driver is really there */ | |
166 | int (*ud_slave)(); /* see if a slave is there; init */ | |
167 | int (*ud_dgo)(); /* routine to stuff driver regs */ | |
168 | /* dgo is called back by the unibus (usu ubaalloc), when the bus is ready */ | |
10a50234 BJ |
169 | short ud_needexcl; /* need exclusive use of uba (rk07) */ |
170 | u_short *ud_addr; /* device csr addresses */ | |
15b39647 | 171 | char *ud_dname; /* name of a device */ |
ca89a8ee | 172 | struct uba_dinfo **ud_dinfo; /* backpointers to ubdinit structs */ |
15b39647 | 173 | char *ud_mname; /* name of a controller */ |
ca89a8ee | 174 | struct uba_minfo **ud_minfo; /* backpointers to ubminit structs */ |
466a1b4c BJ |
175 | }; |
176 | ||
10a50234 BJ |
177 | /* |
178 | * unibus maps | |
179 | */ | |
180 | #define NBDP780 15 | |
181 | #define NBDP750 3 | |
182 | #define MAXNBDP 15 | |
183 | ||
184 | #define NUBMREG 496 | |
185 | ||
186 | /* | |
187 | * flags to uba map/bdp allocation routines | |
188 | */ | |
189 | #define UBA_NEEDBDP 1 /* transfer needs a bdp */ | |
190 | #define UBA_CANTWAIT 2 /* don't block me */ | |
191 | #define UBA_NEED16 3 /* need 16 bit addresses only */ | |
15b39647 BJ |
192 | |
193 | /* | |
194 | * UNIBUS related kernel variables | |
195 | */ | |
196 | #ifdef KERNEL | |
197 | extern struct uba_minfo ubminit[]; | |
198 | extern struct uba_dinfo ubdinit[]; | |
199 | int numuba; | |
200 | extern struct pte UMEMmap[MAXNUBA][16]; | |
201 | extern char umem[MAXNUBA][16*NBPG]; | |
202 | extern int (*UNIvec[])(); | |
203 | #if VAX780 | |
204 | extern Xua0int(), Xua1int(), Xua2int(), Xua3int(); | |
205 | #endif | |
206 | #endif |