projects / unix-history / blame
| Commit | Line | Data |
|---|---|---|
| f7395c69 SL |
1 | /* if_cssreg.h 4.1 82/07/20 */ |
| 2 | ||
| 3 | /* | |
| 4 | * DEC/CSS IMP11-A ARPAnet interface | |
| 5 | */ | |
| 6 | ||
| 7 | struct cssdma { | |
| 8 | short wc; /* word count */ | |
| 9 | u_short ba; /* bus address (low 16 bits) */ | |
| 10 | short csr; /* status register */ | |
| 11 | short db; /* data buffer*/ | |
| 12 | }; | |
| 13 | ||
| 14 | struct cssdevice { | |
| 15 | struct cssdma css_output; /* transmit DR11-B */ | |
| 16 | struct cssdma css_hole; /* unclever gap */ | |
| 17 | struct cssdma css_input; /* receive DR11-B */ | |
| 18 | }; | |
| 19 | ||
| 20 | #define css_icsr css_input.csr | |
| 21 | #define css_iba css_input.ba | |
| 22 | #define css_iwc css_input.wc | |
| 23 | #define css_ocsr css_output.csr | |
| 24 | #define css_oba css_output.ba | |
| 25 | #define css_owc css_output.wc | |
| 26 | ||
| 27 | /* | |
| 28 | * Bits Common to both input and out CSR's | |
| 29 | */ | |
| 30 | #define CSS_ERR 0x8000 /* error present */ | |
| 31 | #define CSS_NXM 0x4000 /* non-existant memory */ | |
| 32 | #define CSS_ATTN 0x2000 /* attention */ | |
| 33 | #define CSS_MAINT 0x1000 /* maintenance mode */ | |
| 34 | #define CSS_CYCLE 0x0100 /* force bus cycle */ | |
| 35 | #define CSS_RDY 0x0080 /* ready */ | |
| 36 | #define CSS_IE 0x0040 /* interrupt enable */ | |
| 37 | #define CSS_XA 0x0030 /* extended address bits */ | |
| 38 | #define CSS_CLR 0x0020 /* clear status (reset) */ | |
| 39 | #define CSS_GO 0x0001 /* start operation */ | |
| 40 | ||
| 41 | /* | |
| 42 | * Input Control Status Register | |
| 43 | */ | |
| 44 | #define IN_EOM 0x0800 /* end-of-message recieved */ | |
| 45 | #define IN_IMPNR 0x0400 /* IMP not ready */ | |
| 46 | #define IN_RLE 0x0200 /* ready line error */ | |
| 47 | #define IN_WEN 0x0008 /* write enable */ | |
| 48 | #define IN_HRDY 0x0004 /* host ready */ | |
| 49 | ||
| 50 | #define CSS_INBITS \ | |
| 51 | "\20\20ERR\17NXM\16ATTN\15MAINT\14EOM\13IMPNR\12RLE\11CYCLE\10RDY\7IE\6XBA17\5XBA16\4WE\3HRDY\2CLR\1GO" | |
| 52 | ||
| 53 | ||
| 54 | /* | |
| 55 | * Output Control Status Register | |
| 56 | */ | |
| 57 | #define OUT_TXEC 0x0008 /* tx error clear */ | |
| 58 | #define OUT_ENLB 0x0004 /* enable last bit */ | |
| 59 | ||
| 60 | #define CSS_OUTBITS \ | |
| 61 | "\20\20ERR\17NXM\16ATTN\15MAINT\11CYCLE\10RDY\7IE\6XBA17\5XBA16\4TXEC\3ENLB\2CLR\1GO" |