Commit | Line | Data |
---|---|---|
70351527 | 1 | /* ikreg.h 1.2 86/12/11 */ |
1287b07c SL |
2 | |
3 | /* | |
4 | * IKON DR-11W register definitions. | |
5 | */ | |
70351527 SL |
6 | struct ikdevice { |
7 | u_short ik_csr; /* control status register */ | |
8 | u_short ik_data; /* data in/out register */ | |
9 | u_char ik_mod; /* address modifier */ | |
10 | u_char ik_vec; /* interrupt vector */ | |
11 | u_short ik_pulse; /* pulse commands (w) */ | |
12 | u_short ik_fill[5]; | |
13 | u_short ik_balo; /* low word of dma beginning address (w) */ | |
14 | u_short ik_wc; /* dma word count */ | |
15 | u_short ik_calo; /* low word of dma current address (r) */ | |
16 | u_short ik_fill1; | |
17 | u_short ik_bahi; /* high word of dma beginning address (w) */ | |
18 | u_short ik_fill2; | |
19 | u_short ik_cahi; /* high word of dma current address (r) */ | |
1287b07c SL |
20 | }; |
21 | ||
22 | /* | |
23 | * CSR control definitions (write-only). | |
24 | */ | |
70351527 SL |
25 | #define IKCSR_GO 0x0001 /* start dma */ |
26 | #define IKCSR_FNC1 0x0002 /* function bit 1 */ | |
27 | #define IKCSR_FNC2 0x0004 /* function bit 2 */ | |
28 | #define IKCSR_FNC3 0x0008 /* function bit 3 */ | |
1287b07c | 29 | /* bits 4-5 are unused */ |
70351527 | 30 | #define IKCSR_IENA 0x0040 /* enable/disable interrupts */ |
1287b07c | 31 | /* bit 7 is unused */ |
70351527 | 32 | #define IKCSR_CYCLE 0x0100 /* force dma to cycle */ |
1287b07c | 33 | /* bits 9-11 are unused */ |
70351527 SL |
34 | #define IKCSR_MCLR 0x1000 /* master clear board */ |
35 | #define IKCSR_RPERR 0x2000 /* reset parity error */ | |
36 | #define IKCSR_RATTF 0x4000 /* reset attention */ | |
37 | #define IKCSR_RDMAF 0x8000 /* reset dma completion */ | |
1287b07c SL |
38 | |
39 | /* | |
40 | * CSR status definitions (read-only). | |
41 | */ | |
70351527 | 42 | #define IKCSR_DEV 0x0001 /* device flag (0 = 10083, 1 = 10077) */ |
1287b07c | 43 | /* bits 1-3 reflect the function latch state */ |
70351527 SL |
44 | #define IKCSR_TIMO 0x0010 /* bus timeout during dma */ |
45 | #define IKCSR_BERR 0x0020 /* bus error during dma */ | |
1287b07c | 46 | /* bit 6 reflects interrupt enable state */ |
70351527 | 47 | #define IKCSR_READY 0x0080 /* device ready for next command */ |
1287b07c | 48 | /* bit 8 should be 0 */ |
70351527 SL |
49 | #define IKCSR_STATC 0x0200 /* status bit C */ |
50 | #define IKCSR_STATB 0x0400 /* status bit B */ | |
51 | #define IKCSR_STATA 0x0800 /* status bit A */ | |
52 | #define IKCSR_PERR 0x1000 /* parity error during pi/o or dma */ | |
53 | #define IKCSR_ATTN 0x2000 /* current state of attention bit */ | |
54 | #define IKCSR_ATTF 0x4000 /* latched attention t-f transition */ | |
55 | #define IKCSR_DMAF 0x8000 /* dma completed or terminated */ | |
1287b07c SL |
56 | |
57 | #define IKCSR_BITS \ | |
58 | "\020\1DEV\2FNC1\3FNC2\4FNC3\5TIMO\6BERR\7IENA\10READY\12STATC\13STATB\14STATA\ | |
59 | \15PERR\16ATTN\17ATTF\20DMAF" | |
60 | ||
1287b07c SL |
61 | /* |
62 | * Pulse command register definitions (write-only). | |
63 | */ | |
70351527 SL |
64 | #define IKPULSE_GO 0x0001 /* enable dma */ |
65 | #define IKPULSE_FNC2 0x0004 /* pulse function bit 1 */ | |
66 | #define IKPULSE_RIENA 0x0020 /* reset IKCSR_IENA */ | |
67 | #define IKPULSE_SIENA 0x0040 /* set IKCSR_IENA */ | |
68 | #define IKPULSE_CYCL 0x0100 /* force dma to cycle */ | |
69 | #define IKPULSE_MCLR 0x1000 /* initialize interface */ | |
70 | #define IKPULSE_RPERR 0x2000 /* reset IKCSR_PERR */ | |
71 | #define IKPULSE_RATTF 0x4000 /* reset IKCSR_ATTF */ | |
72 | #define IKPULSE_RDMAF 0x8000 /* reset IKCSR_DMAF */ |