[unix-history] / usr / src / sys / vax / uba / qdreg.h

/*
 * Copyright (c) 1982, 1986 Regents of the University of California.
 * All rights reserved.  The Berkeley software License Agreement
 * specifies the terms and conditions for redistribution.
 *
 * 		@(#)qdreg.h	1.5  Berkeley  %G%
 */

/************************************************************************
 *									*
 *			Copyright (c) 1985, 1986 by			*
 *		Digital Equipment Corporation, Maynard, MA		*
 *			All rights reserved.				*
 *									*
 *   This software is furnished under a license and may be used and	*
 *   copied  only  in accordance with the terms of such license and	*
 *   with the  inclusion  of  the  above  copyright  notice.   This	*
 *   software  or  any	other copies thereof may not be provided or	*
 *   otherwise made available to any other person.  No title to and	*
 *   ownership of the software is hereby transferred.			*
 *									*
 *   The information in this software is subject to change  without	*
 *   notice  and should not be construed as a commitment by Digital	*
 *   Equipment Corporation.						*
 *									*
 *   Digital assumes no responsibility for the use  or	reliability	*
 *   of its software on equipment which is not supplied by Digital.	*
 *									*
 ************************************************************************/

/* Dragon ADDER reg map */
/* ADDER register bit definitions */
/* Y_SCROLL_CONSTANT */

#define SCROLL_ERASE		0x2000
#define ADDER_SCROLL_DOWN	0x1000

/* ADDER status and interrupt enable registers [1], [2], [3] */

#define DISABLE 		0x0000
#define PAUSE_COMPLETE		0x0001
#define FRAME_SYNC		0x0002
#define INIT_COMPLETE		0x0004
#define RASTEROP_COMPLETE	0x0008

#define ADDRESS_COMPLETE	0x0010
#define RX_READY		0x0020
#define TX_READY		0x0040
#define ID_SCROLL_READY 	0x0080

#define TOP_CLIP		0x0100
#define BOTTOM_CLIP		0x0200
#define LEFT_CLIP		0x0400
#define RIGHT_CLIP		0x0800
#define NO_CLIP 		0x1000
#define VSYNC			0x2000

/* ADDER command register [8], [10] */

#define OCR_zero		0x0000
#define Z_BLOCK0		0x0000
#define OCRA			0x0000
#define OCRB			0x0004
#define RASTEROP		0x02c0
#define PBT			0x03c0
#define BTPZ			0x0bb0
#define PTBZ			0x07a0
#define DTE			0x0400
#define S1E			0x0800
#define S2E			0x1000
#define VIPER_Z_LOAD		0x01A0
#define ID_LOAD 		0x0100
#define CANCEL			0x0000
#define LF_R1			0x0000
#define LF_R2			0x0010
#define LF_R3			0x0020
#define LF_R4			0x0030

/* ADDER rasterop mode register [9] */

#define NORMAL			0x0000
#define LINEAR_PATTERN		0x0002
#define X_FILL			0x0003
#define Y_FILL			0x0007
#define BASELINE		0x0008
#define HOLE_ENABLE		0x0010
#define SRC_1_INDEX_ENABLE	0x0020
#define DST_INDEX_ENABLE	0x0040
#define DST_WRITE_ENABLE	0x0080

/* ADDER source 2 size register */

#define NO_TILE 		0x0080

/* External registers base addresses */

#define CS_UPDATE_MASK		0x0060
#define CS_SCROLL_MASK		0x0040

/* VIPER registers */

#define RESOLUTION_MODE 	0x0080
#define MEMORY_BUS_WIDTH	0x0081
#define PLANE_ADDRESS		0x0083
#define LU_FUNCTION_R1		0x0084
#define LU_FUNCTION_R2		0x0085
#define LU_FUNCTION_R3		0x0086
#define LU_FUNCTION_R4		0x0087
#define MASK_1			0x0088
#define MASK_2			0x0089
#define SOURCE			0x008a
#define SOURCE_Z		0x0000
#define BACKGROUND_COLOR	0x008e
#define BACKGROUND_COLOR_Z	0x000C
#define FOREGROUND_COLOR	0x008f
#define FOREGROUND_COLOR_Z	0x0004
#define SRC1_OCR_A		0x0090
#define SRC2_OCR_A		0x0091
#define DST_OCR_A		0x0092
#define SRC1_OCR_B		0x0094
#define SRC2_OCR_B		0x0095
#define DST_OCR_B		0x0096

/* VIPER scroll registers */

#define SCROLL_CONSTANT 	0x0082
#define SCROLL_FILL		0x008b
#define SCROLL_FILL_Z		0x0008
#define LEFT_SCROLL_MASK	0x008c
#define RIGHT_SCROLL_MASK	0x008d

/* VIPER register bit definitions */

#define EXT_NONE		0x0000
#define EXT_SOURCE		0x0001
#define EXT_M1_M2		0x0002
#define INT_NONE		0x0000
#define INT_SOURCE		0x0004
#define INT_M1_M2		0x0008
#define ID			0x0010
#define NO_ID			0x0000
#define WAIT			0x0020
#define NO_WAIT 		0x0000
#define BAR_SHIFT_DELAY 	WAIT
#define NO_BAR_SHIFT_DELAY	NO_WAIT


/* VIPER logical function unit codes */

#define LF_ZEROS		0x0000
#define LF_D_XOR_S		0x0006
#define LF_SOURCE		0x000A
#define LF_D_OR_S		0x000E
#define LF_ONES 		0x000F
#define INV_M1_M2		0x0030
#define FULL_SRC_RESOLUTION	0X00C0 /* makes second pass like first pass */

/* VIPER scroll register [2] */

#define SCROLL_DISABLE		0x0040
#define SCROLL_ENABLE		0x0020
#define VIPER_LEFT		0x0000
#define VIPER_RIGHT		0x0010
#define VIPER_UP		0x0040
#define VIPER_DOWN		0x0000

/* Adder scroll register */

#define ADDER_UP		0x0000
#define ADDER_DOWN		0x1000

/* Misc scroll definitions */

#define UP		0
#define DOWN		1
#define LEFT		2
#define RIGHT		3
#define NODIR		4
#define SCROLL_VMAX	31
#define SCROLL_HMAX	15
#define NEW		2
#define OLD		1
#define BUSY		1
#define DRAG		1
#define SCROLL		0

/* miscellaneous defines */

#define ALL_PLANES	0xffffffff
#define UNITY		0x1fff		 /* Adder scale factor */
#define MAX_SCREEN_X	1024
#define MAX_SCREEN_Y	864
#define FONT_HEIGHT	32

	struct adder {

	    /* adder control registers */

	    u_short register_address;	/* ADDER reg pntr for use by DGA */
	    u_short request_enable;	/* DMA request enables */
	    u_short interrupt_enable;	/* interrupt enables */
	    u_short status;		/* ADDER status bits */
	    u_short reserved1;		/* test function only */
	    u_short spare1;		/* spare address (what else?) */

	    u_short reserved2;		/* test function only */
	    u_short id_data;		/* data path to I/D bus */
	    u_short command;		/* ADDER chip command register */
	    u_short rasterop_mode;	/* sets rasterop execution modes */
	    u_short cmd;		/* duplicate path to above cmd reg */
	    u_short reserved3;		/* test function only */

	    /* scroll registers */

	    u_short ID_scroll_data;	/* I/D bus scroll data */
	    u_short ID_scroll_command;	/* I/D bus scroll command */
	    u_short scroll_x_min;	/* X scroll min - left boundary */
	    u_short scroll_x_max;	/* X scroll max - right boundary */
	    u_short scroll_y_min;	/* Y scroll min - upper boundary */
	    u_short scroll_y_max;	/* Y scroll max - lower boundary */
	    u_short pause;		/* Y coord to set stat when scanned */
	    u_short y_offset_pending;	/* vertical scroll control */
	    u_short y_scroll_constant;

	    /* update control registers */

	    u_short x_index_pending;	/* x pending index */
	    u_short y_index_pending;	/* y pending index */
	    u_short x_index_new;	/* new x index */
	    u_short y_index_new;		/* new y index */
	    u_short x_index_old;		/* old x index */
	    u_short y_index_old;		/* old y index */
	    u_short x_clip_min; 	/* left clipping boundary */
	    u_short x_clip_max; 	/* right clipping boundary */
	    u_short y_clip_min; 	/* upper clipping boundary */
	    u_short y_clip_max; 	/* lower clipping boundary */
	    u_short spare2;		/* spare address (another!) */

	    /* rasterop control registers */

	    u_short source_1_dx;	/* source #1 x vector */
	    u_short source_1_dy;	/* source #1 y vector*/
	    u_short source_1_x; 	/* source #1 x origin */
	    u_short source_1_y; 	/* source #1 y origin */
	    u_short destination_x;	/* destination x origin */
	    u_short destination_y;	/* destination y origin */
	    u_short fast_dest_dx;	/* destination x fast vector */
	    u_short fast_dest_dy;	/* destination y fast vector */
	    u_short slow_dest_dx;	/* destination x slow vector */
	    u_short slow_dest_dy;	/* destination y slow vector */
	    u_short fast_scale; 	/* scale factor for fast vector */
	    u_short slow_scale; 	/* scale factor for slow vector */
	    u_short source_2_x; 	/* source #2 x origin */
	    u_short source_2_y; 	/* source #2 y origin */
	    u_short source_2_size;	/* source #2 height & width */
	    u_short error_1;		/* error regs (?) */
	    u_short error_2;

	    /* screen format control registers */

	    u_short y_scan_count_0;	/* y scan counts for vert timing */
	    u_short y_scan_count_1;
	    u_short y_scan_count_2;
	    u_short y_scan_count_3;
	    u_short x_scan_conf;	/* x scan configuration */
	    u_short x_limit;
	    u_short y_limit;
	    u_short x_scan_count_0;	/* x scan count for horiz timing */
	    u_short x_scan_count_1;
	    u_short x_scan_count_2;
	    u_short x_scan_count_3;
	    u_short x_scan_count_4;
	    u_short x_scan_count_5;
	    u_short x_scan_count_6;
	    u_short sync_phase_adj;	/* sync phase (horiz sync count) */
	};

/*---------------------
* DUART definitions */

	/* command definitions */

#define EN_RCV		0x01
#define DIS_RCV 	0x02
#define EN_XMT		0x04
#define DIS_XMT 	0x08
#define RESET_M 	0x10
#define RESET_RCV	0x20
#define RESET_XMT	0x30
#define RESET_ERR	0x40
#define RESET_BD	0x50
#define START_BREAK	0x60
#define STOP_BREAK	0x70

	/* interupt bit definitions */

#define EI_XMT_A	0x01
#define EI_RCV_A	0x02
#define EI_XMT_B	0x10
#define EI_RCV_B	0x20

#define XMT_RDY_A	0x01
#define RCV_RDY_A	0x02
#define XMT_RDY_B	0x10
#define RCV_RDY_B	0x20

	/* status register bit defintions */

#define RCV_RDY 	0x01
#define FIFO_FULL	0x02
#define XMT_RDY 	0x04
#define XMT_EMT 	0x08
#define OVER_ERR	0x10
#define ERR_PARITY	0x20
#define FRAME_ERR	0x40
#define RCVD_BREAK	0x80


	struct duart {

	    /* channel A - LK201 */

	    short modeA;		/* ch.A mode reg (read/write) */
	    short statusA;		/* ch.A status reg (read) */
#define clkselA statusA 		/* ch.A clock slect reg (write) */
	    short cmdA; 		/* ch.A command reg (write) */
	    short dataA;		/* rcv/xmt data ch.A (read/write) */
	    short inchng;		/* input change state reg (read) */
#define auxctl inchng			/* auxiliary control reg (write) */
	    short istatus;		/* interrupt status reg (read) */
#define imask istatus			/* interrupt mask reg (write) */
	    short CThi; 		/* counter/timer hi byte (read) */
#define CTRhi CThi			/* counter/timer hi reg (write) */
	    short CTlo; 		/* counter/timer lo byte (read) */
#define CTRlo CTlo			/* counter/timer lo reg (write) */

	    /* channel B - pointing device */

	    short modeB;		/* ch.B mode reg (read/write) */
	    short statusB;		/* ch.B status reg (read) */
#define clkselB statusB 		/* ch.B clock select reg (write) */
	    short cmdB; 		/* ch.B command reg (write) */
	    short dataB;		/* ch.B rcv/xmt data (read/write) */
	    short rsrvd;
	    short inport;		/* input port (read) */
#define outconf inport			/* output port config reg (write) */
	    short strctr;		/* start counter command (read) */
#define setbits setctr			/* output bits set command (write) */
	    short stpctr;		/* stop counter command (read) */
#define resetbits stpctr		/* output bits reset cmd (write) */

};
Commit	Line	Data
f8184c15	1	/*
1882115b MT	2	* Copyright (c) 1982, 1986 Regents of the University of California.
	3	* All rights reserved. The Berkeley software License Agreement
	4	* specifies the terms and conditions for redistribution.
	5	*
64058888	6	* @(#)qdreg.h 1.5 Berkeley %G%
f8184c15	7	*/
1882115b	8
f8184c15 MT	9	/************************************************************************
	10	* *
	11	* Copyright (c) 1985, 1986 by *
	12	* Digital Equipment Corporation, Maynard, MA *
	13	* All rights reserved. *
	14	* *
	15	* This software is furnished under a license and may be used and *
	16	* copied only in accordance with the terms of such license and *
	17	* with the inclusion of the above copyright notice. This *
	18	* software or any other copies thereof may not be provided or *
	19	* otherwise made available to any other person. No title to and *
	20	* ownership of the software is hereby transferred. *
	21	* *
	22	* The information in this software is subject to change without *
	23	* notice and should not be construed as a commitment by Digital *
	24	* Equipment Corporation. *
	25	* *
	26	* Digital assumes no responsibility for the use or reliability *
	27	* of its software on equipment which is not supplied by Digital. *
	28	* *
	29	************************************************************************/
	30
f8184c15 MT	31	/* Dragon ADDER reg map */
	32	/* ADDER register bit definitions */
	33	/* Y_SCROLL_CONSTANT */
	34
	35	#define SCROLL_ERASE 0x2000
	36	#define ADDER_SCROLL_DOWN 0x1000
	37
	38	/* ADDER status and interrupt enable registers [1], [2], [3] */
	39
	40	#define DISABLE 0x0000
	41	#define PAUSE_COMPLETE 0x0001
	42	#define FRAME_SYNC 0x0002
	43	#define INIT_COMPLETE 0x0004
	44	#define RASTEROP_COMPLETE 0x0008
	45
	46	#define ADDRESS_COMPLETE 0x0010
	47	#define RX_READY 0x0020
	48	#define TX_READY 0x0040
	49	#define ID_SCROLL_READY 0x0080
	50
	51	#define TOP_CLIP 0x0100
	52	#define BOTTOM_CLIP 0x0200
	53	#define LEFT_CLIP 0x0400
	54	#define RIGHT_CLIP 0x0800
	55	#define NO_CLIP 0x1000
	56	#define VSYNC 0x2000
	57
	58	/* ADDER command register [8], [10] */
	59
	60	#define OCR_zero 0x0000
	61	#define Z_BLOCK0 0x0000
	62	#define OCRA 0x0000
	63	#define OCRB 0x0004
	64	#define RASTEROP 0x02c0
	65	#define PBT 0x03c0
	66	#define BTPZ 0x0bb0
	67	#define PTBZ 0x07a0
	68	#define DTE 0x0400
	69	#define S1E 0x0800
	70	#define S2E 0x1000
	71	#define VIPER_Z_LOAD 0x01A0
	72	#define ID_LOAD 0x0100
	73	#define CANCEL 0x0000
	74	#define LF_R1 0x0000
	75	#define LF_R2 0x0010
	76	#define LF_R3 0x0020
	77	#define LF_R4 0x0030
	78
	79	/* ADDER rasterop mode register [9] */
	80
	81	#define NORMAL 0x0000
	82	#define LINEAR_PATTERN 0x0002
	83	#define X_FILL 0x0003
	84	#define Y_FILL 0x0007
	85	#define BASELINE 0x0008
	86	#define HOLE_ENABLE 0x0010
	87	#define SRC_1_INDEX_ENABLE 0x0020
	88	#define DST_INDEX_ENABLE 0x0040
	89	#define DST_WRITE_ENABLE 0x0080
	90
	91	/* ADDER source 2 size register */
	92
	93	#define NO_TILE 0x0080
	94
95	/* External registers base addresses */
96
97	#define CS_UPDATE_MASK 0x0060
98	#define CS_SCROLL_MASK 0x0040
99
100	/* VIPER registers */
101
102	#define RESOLUTION_MODE 0x0080
103	#define MEMORY_BUS_WIDTH 0x0081
104	#define PLANE_ADDRESS 0x0083
105	#define LU_FUNCTION_R1 0x0084
106	#define LU_FUNCTION_R2 0x0085
107	#define LU_FUNCTION_R3 0x0086
108	#define LU_FUNCTION_R4 0x0087
109	#define MASK_1 0x0088
110	#define MASK_2 0x0089
111	#define SOURCE 0x008a
112	#define SOURCE_Z 0x0000
113	#define BACKGROUND_COLOR 0x008e
114	#define BACKGROUND_COLOR_Z 0x000C
115	#define FOREGROUND_COLOR 0x008f
116	#define FOREGROUND_COLOR_Z 0x0004
117	#define SRC1_OCR_A 0x0090
118	#define SRC2_OCR_A 0x0091
119	#define DST_OCR_A 0x0092
120	#define SRC1_OCR_B 0x0094
121	#define SRC2_OCR_B 0x0095
122	#define DST_OCR_B 0x0096
123
124	/* VIPER scroll registers */
125
126	#define SCROLL_CONSTANT 0x0082
127	#define SCROLL_FILL 0x008b
128	#define SCROLL_FILL_Z 0x0008
129	#define LEFT_SCROLL_MASK 0x008c
130	#define RIGHT_SCROLL_MASK 0x008d
131
132	/* VIPER register bit definitions */
133
134	#define EXT_NONE 0x0000
135	#define EXT_SOURCE 0x0001
136	#define EXT_M1_M2 0x0002
137	#define INT_NONE 0x0000
138	#define INT_SOURCE 0x0004
139	#define INT_M1_M2 0x0008
140	#define ID 0x0010
141	#define NO_ID 0x0000
142	#define WAIT 0x0020
143	#define NO_WAIT 0x0000
144	#define BAR_SHIFT_DELAY WAIT
145	#define NO_BAR_SHIFT_DELAY NO_WAIT
146
147
148	/* VIPER logical function unit codes */
149
150	#define LF_ZEROS 0x0000
151	#define LF_D_XOR_S 0x0006
152	#define LF_SOURCE 0x000A
153	#define LF_D_OR_S 0x000E
154	#define LF_ONES 0x000F
155	#define INV_M1_M2 0x0030
156	#define FULL_SRC_RESOLUTION 0X00C0 /* makes second pass like first pass */
157
158	/* VIPER scroll register [2] */
159
160	#define SCROLL_DISABLE 0x0040
161	#define SCROLL_ENABLE 0x0020
162	#define VIPER_LEFT 0x0000
163	#define VIPER_RIGHT 0x0010
164	#define VIPER_UP 0x0040
165	#define VIPER_DOWN 0x0000
166
167	/* Adder scroll register */
168
169	#define ADDER_UP 0x0000
170	#define ADDER_DOWN 0x1000
171
172	/* Misc scroll definitions */
173
174	#define UP 0
175	#define DOWN 1
176	#define LEFT 2
177	#define RIGHT 3
178	#define NODIR 4
179	#define SCROLL_VMAX 31
180	#define SCROLL_HMAX 15
181	#define NEW 2
182	#define OLD 1
183	#define BUSY 1
184	#define DRAG 1
185	#define SCROLL 0
186
187	/* miscellaneous defines */
188
189	#define ALL_PLANES 0xffffffff
190	#define UNITY 0x1fff /* Adder scale factor */
191	#define MAX_SCREEN_X 1024
192	#define MAX_SCREEN_Y 864
193	#define FONT_HEIGHT 32
194
195	struct adder {
196
197	/* adder control registers */
198
199	u_short register_address; /* ADDER reg pntr for use by DGA */
200	u_short request_enable; /* DMA request enables */
201	u_short interrupt_enable; /* interrupt enables */
202	u_short status; /* ADDER status bits */
203	u_short reserved1; /* test function only */
204	u_short spare1; /* spare address (what else?) */
205
206	u_short reserved2; /* test function only */
207	u_short id_data; /* data path to I/D bus */
208	u_short command; /* ADDER chip command register */
209	u_short rasterop_mode; /* sets rasterop execution modes */
210	u_short cmd; /* duplicate path to above cmd reg */
211	u_short reserved3; /* test function only */
212
213	/* scroll registers */
214
215	u_short ID_scroll_data; /* I/D bus scroll data */
216	u_short ID_scroll_command; /* I/D bus scroll command */
217	u_short scroll_x_min; /* X scroll min - left boundary */
218	u_short scroll_x_max; /* X scroll max - right boundary */
219	u_short scroll_y_min; /* Y scroll min - upper boundary */
220	u_short scroll_y_max; /* Y scroll max - lower boundary */
221	u_short pause; /* Y coord to set stat when scanned */
222	u_short y_offset_pending; /* vertical scroll control */
223	u_short y_scroll_constant;
224
225	/* update control registers */
226
227	u_short x_index_pending; /* x pending index */
228	u_short y_index_pending; /* y pending index */
229	u_short x_index_new; /* new x index */
230	u_short y_index_new; /* new y index */
231	u_short x_index_old; /* old x index */
232	u_short y_index_old; /* old y index */
233	u_short x_clip_min; /* left clipping boundary */
234	u_short x_clip_max; /* right clipping boundary */
235	u_short y_clip_min; /* upper clipping boundary */
236	u_short y_clip_max; /* lower clipping boundary */
237	u_short spare2; /* spare address (another!) */
238
239	/* rasterop control registers */
240
241	u_short source_1_dx; /* source #1 x vector */
242	u_short source_1_dy; /* source #1 y vector*/
243	u_short source_1_x; /* source #1 x origin */
244	u_short source_1_y; /* source #1 y origin */
245	u_short destination_x; /* destination x origin */
246	u_short destination_y; /* destination y origin */
247	u_short fast_dest_dx; /* destination x fast vector */
248	u_short fast_dest_dy; /* destination y fast vector */
249	u_short slow_dest_dx; /* destination x slow vector */
250	u_short slow_dest_dy; /* destination y slow vector */
251	u_short fast_scale; /* scale factor for fast vector */
252	u_short slow_scale; /* scale factor for slow vector */
253	u_short source_2_x; /* source #2 x origin */
254	u_short source_2_y; /* source #2 y origin */
255	u_short source_2_size; /* source #2 height & width */
256	u_short error_1; /* error regs (?) */
257	u_short error_2;
258
259	/* screen format control registers */
260
261	u_short y_scan_count_0; /* y scan counts for vert timing */
262	u_short y_scan_count_1;
263	u_short y_scan_count_2;
264	u_short y_scan_count_3;
265	u_short x_scan_conf; /* x scan configuration */
266	u_short x_limit;
267	u_short y_limit;
268	u_short x_scan_count_0; /* x scan count for horiz timing */
269	u_short x_scan_count_1;
270	u_short x_scan_count_2;
271	u_short x_scan_count_3;
272	u_short x_scan_count_4;
273	u_short x_scan_count_5;
274	u_short x_scan_count_6;
275	u_short sync_phase_adj; /* sync phase (horiz sync count) */
276	};
277
278	/*---------------------
279	* DUART definitions */
280
281	/* command definitions */
282
283	#define EN_RCV 0x01
284	#define DIS_RCV 0x02
285	#define EN_XMT 0x04
286	#define DIS_XMT 0x08
287	#define RESET_M 0x10
288	#define RESET_RCV 0x20
289	#define RESET_XMT 0x30
290	#define RESET_ERR 0x40
291	#define RESET_BD 0x50
292	#define START_BREAK 0x60
293	#define STOP_BREAK 0x70
294
295	/* interupt bit definitions */
296
297	#define EI_XMT_A 0x01
298	#define EI_RCV_A 0x02
299	#define EI_XMT_B 0x10
300	#define EI_RCV_B 0x20
301
302	#define XMT_RDY_A 0x01
303	#define RCV_RDY_A 0x02
304	#define XMT_RDY_B 0x10
305	#define RCV_RDY_B 0x20
306
307	/* status register bit defintions */
308
309	#define RCV_RDY 0x01
310	#define FIFO_FULL 0x02
311	#define XMT_RDY 0x04
312	#define XMT_EMT 0x08
313	#define OVER_ERR 0x10
314	#define ERR_PARITY 0x20
315	#define FRAME_ERR 0x40
316	#define RCVD_BREAK 0x80
317
318
319	struct duart {
320
321	/* channel A - LK201 */
322
323	short modeA; /* ch.A mode reg (read/write) */
324	short statusA; /* ch.A status reg (read) */
325	#define clkselA statusA /* ch.A clock slect reg (write) */
326	short cmdA; /* ch.A command reg (write) */
327	short dataA; /* rcv/xmt data ch.A (read/write) */
328	short inchng; /* input change state reg (read) */
329	#define auxctl inchng /* auxiliary control reg (write) */
330	short istatus; /* interrupt status reg (read) */
331	#define imask istatus /* interrupt mask reg (write) */
332	short CThi; /* counter/timer hi byte (read) */
333	#define CTRhi CThi /* counter/timer hi reg (write) */
334	short CTlo; /* counter/timer lo byte (read) */
335	#define CTRlo CTlo /* counter/timer lo reg (write) */
336
337	/* channel B - pointing device */
338
339	short modeB; /* ch.B mode reg (read/write) */
340	short statusB; /* ch.B status reg (read) */
341	#define clkselB statusB /* ch.B clock select reg (write) */
342	short cmdB; /* ch.B command reg (write) */
343	short dataB; /* ch.B rcv/xmt data (read/write) */
344	short rsrvd;
345	short inport; /* input port (read) */
346	#define outconf inport /* output port config reg (write) */
347	short strctr; /* start counter command (read) */
348	#define setbits setctr /* output bits set command (write) */
349	short stpctr; /* stop counter command (read) */
350	#define resetbits stpctr /* output bits reset cmd (write) */
351
f8184c15	352	};