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60f56dfc KM |
1 | /* |
2 | * Copyright (c) 1982, 1990 The Regents of the University of California. | |
3 | * All rights reserved. | |
4 | * | |
5 | * %sccs.include.redist.c% | |
6 | * | |
38a01dbe | 7 | * @(#)dmareg.h 7.5 (Berkeley) %G% |
60f56dfc KM |
8 | */ |
9 | ||
38a01dbe | 10 | #include <hp/dev/iotypes.h> /* XXX */ |
9acfa6cd | 11 | |
60f56dfc KM |
12 | /* |
13 | * Hardware layout for the 98620[ABC]: | |
14 | * 98620A (old 320s?): byte/word DMA in up to 64K chunks | |
15 | * 98620B (320s only): 98620A with programmable IPL | |
16 | * 98620C (all others): byte/word/longword DMA in up to 4Gb chunks | |
17 | */ | |
60f56dfc KM |
18 | |
19 | struct dmaBdevice { | |
20 | v_char *dmaB_addr; | |
21 | vu_short dmaB_count; | |
22 | vu_short dmaB_cmd; | |
23 | #define dmaB_stat dmaB_cmd | |
24 | }; | |
25 | ||
26 | struct dmadevice { | |
27 | v_char *dma_addr; | |
28 | vu_int dma_count; | |
29 | vu_short dma_cmd; | |
30 | vu_short dma_stat; | |
31 | }; | |
32 | ||
33 | struct dmareg { | |
34 | struct dmaBdevice dma_Bchan0; | |
35 | struct dmaBdevice dma_Bchan1; | |
36 | /* the rest are 98620C specific */ | |
37 | v_char dma_id[4]; | |
38 | vu_char dma_cr; | |
39 | char dma_pad1[0xEB]; | |
40 | struct dmadevice dma_chan0; | |
41 | char dma_pad2[0xF4]; | |
42 | struct dmadevice dma_chan1; | |
43 | }; | |
44 | ||
45 | #define NDMA 2 | |
46 | ||
47 | /* intr level must be >= level of any device using dma. i.e., splbio */ | |
48 | #define DMAINTLVL 5 | |
49 | ||
50 | /* addresses */ | |
10f6a42c | 51 | #define DMA_BASE IIOV(0x500000) |
60f56dfc KM |
52 | |
53 | /* command bits */ | |
54 | #define DMA_ENAB 0x0001 | |
55 | #define DMA_WORD 0x0002 | |
56 | #define DMA_WRT 0x0004 | |
57 | #define DMA_PRI 0x0008 | |
58 | #define DMA_IPL(x) (((x) - 3) << 4) | |
59 | #define DMA_LWORD 0x0100 | |
60 | #define DMA_START 0x8000 | |
61 | ||
62 | /* status bits */ | |
63 | #define DMA_ARMED 0x01 | |
64 | #define DMA_INTR 0x02 | |
65 | #define DMA_ACC 0x04 | |
66 | #define DMA_HALT 0x08 | |
67 | #define DMA_BERR 0x10 | |
68 | #define DMA_ALIGN 0x20 | |
69 | #define DMA_WRAP 0x40 | |
70 | ||
71 | #ifdef KERNEL | |
72 | /* | |
73 | * Macros to attempt to hide the HW differences between the 98620B DMA | |
74 | * board and the 1TQ4-0401 DMA chip (68020C "board"). The latter | |
75 | * includes emulation registers for the former but you need to access | |
76 | * the "native-mode" registers directly in order to do 32-bit DMA. | |
77 | * | |
78 | * DMA_CLEAR: Clear interrupt on DMA board. We just use the | |
79 | * emulation registers on the 98620C as that is easiest. | |
80 | * DMA_STAT: Read status register. Again, we always read the | |
81 | * emulation register. Someday we might want to | |
82 | * look at the 98620C status to get the extended bits. | |
83 | * DMA_ARM: Load address, count and kick-off DMA. | |
84 | */ | |
85 | #define DMA_CLEAR(dc) { v_int dmaclr = (int)dc->sc_Bhwaddr->dmaB_addr; } | |
86 | #define DMA_STAT(dc) dc->sc_Bhwaddr->dmaB_stat | |
87 | ||
88 | #if defined(HP320) | |
0e1872ad | 89 | #define DMA_ARM(dc) \ |
60f56dfc KM |
90 | if (dc->sc_type == DMA_B) { \ |
91 | register struct dmaBdevice *dma = dc->sc_Bhwaddr; \ | |
0e1872ad KM |
92 | dma->dmaB_addr = dc->sc_cur->dc_addr; \ |
93 | dma->dmaB_count = dc->sc_cur->dc_count - 1; \ | |
60f56dfc KM |
94 | dma->dmaB_cmd = dc->sc_cmd; \ |
95 | } else { \ | |
96 | register struct dmadevice *dma = dc->sc_hwaddr; \ | |
0e1872ad KM |
97 | dma->dma_addr = dc->sc_cur->dc_addr; \ |
98 | dma->dma_count = dc->sc_cur->dc_count - 1; \ | |
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99 | dma->dma_cmd = dc->sc_cmd; \ |
100 | } | |
101 | #else | |
0e1872ad | 102 | #define DMA_ARM(dc) \ |
60f56dfc KM |
103 | { \ |
104 | register struct dmadevice *dma = dc->sc_hwaddr; \ | |
0e1872ad KM |
105 | dma->dma_addr = dc->sc_cur->dc_addr; \ |
106 | dma->dma_count = dc->sc_cur->dc_count - 1; \ | |
60f56dfc KM |
107 | dma->dma_cmd = dc->sc_cmd; \ |
108 | } | |
109 | #endif | |
110 | #endif |