Commit | Line | Data |
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592df170 MT |
1 | #ifndef DEBUG |
2 | #define DEBUG | |
3 | #endif | |
60f56dfc KM |
4 | /* |
5 | * Copyright (c) 1990 The Regents of the University of California. | |
6 | * All rights reserved. | |
7 | * | |
8 | * This code is derived from software contributed to Berkeley by | |
9 | * Van Jacobson of Lawrence Berkeley Laboratory. | |
10 | * | |
11 | * %sccs.include.redist.c% | |
12 | * | |
38a01dbe | 13 | * @(#)scsi.c 7.8 (Berkeley) %G% |
60f56dfc KM |
14 | */ |
15 | ||
16 | /* | |
17 | * HP9000/3xx 98658 SCSI host adaptor driver. | |
18 | */ | |
19 | #include "scsi.h" | |
20 | #if NSCSI > 0 | |
21 | ||
22 | #ifndef lint | |
9acfa6cd | 23 | static char rcsid[] = "$Header: /usr/src/sys/hp300/dev/RCS/scsi.c,v 1.2 92/04/10 20:48:29 mike Exp $"; |
60f56dfc KM |
24 | #endif |
25 | ||
38a01dbe KB |
26 | #include <sys/param.h> |
27 | #include <sys/systm.h> | |
28 | #include <sys/buf.h> | |
b28b3a13 | 29 | |
38a01dbe | 30 | #include <hp/dev/device.h> |
60f56dfc | 31 | |
38a01dbe KB |
32 | #include <hp300/dev/scsivar.h> |
33 | #include <hp300/dev/scsireg.h> | |
34 | #include <hp300/dev/dmavar.h> | |
35 | ||
36 | #include <machine/cpu.h> | |
37 | #include <hp300/hp300/isr.h> | |
60f56dfc | 38 | |
98511a3b KM |
39 | /* |
40 | * SCSI delays | |
41 | * In u-seconds, primarily for state changes on the SPC. | |
42 | */ | |
43 | #define SCSI_CMD_WAIT 1000 /* wait per step of 'immediate' cmds */ | |
44 | #define SCSI_DATA_WAIT 1000 /* wait per data in/out step */ | |
45 | #define SCSI_INIT_WAIT 50000 /* wait per step (both) during init */ | |
46 | ||
60f56dfc | 47 | extern void isrlink(); |
60f56dfc KM |
48 | extern void _insque(); |
49 | extern void _remque(); | |
60f56dfc KM |
50 | |
51 | int scsiinit(), scsigo(), scsiintr(), scsixfer(); | |
52 | void scsistart(), scsidone(), scsifree(), scsireset(); | |
53 | struct driver scsidriver = { | |
54 | scsiinit, "scsi", (int (*)())scsistart, scsigo, scsiintr, | |
55 | (int (*)())scsidone, | |
56 | }; | |
57 | ||
58 | struct scsi_softc scsi_softc[NSCSI]; | |
59 | struct isr scsi_isr[NSCSI]; | |
60 | ||
98511a3b KM |
61 | int scsi_cmd_wait = SCSI_CMD_WAIT; |
62 | int scsi_data_wait = SCSI_DATA_WAIT; | |
63 | int scsi_init_wait = SCSI_INIT_WAIT; | |
64 | ||
60f56dfc | 65 | int scsi_nosync = 1; /* inhibit sync xfers if 1 */ |
d989d7c8 | 66 | int scsi_pridma = 0; /* use "priority" dma */ |
60f56dfc KM |
67 | |
68 | #ifdef DEBUG | |
69 | int scsi_debug = 0; | |
70 | #define WAITHIST | |
71 | #endif | |
72 | ||
73 | #ifdef WAITHIST | |
d989d7c8 | 74 | #define MAXWAIT 1022 |
60f56dfc KM |
75 | u_int ixstart_wait[MAXWAIT+2]; |
76 | u_int ixin_wait[MAXWAIT+2]; | |
77 | u_int ixout_wait[MAXWAIT+2]; | |
78 | u_int mxin_wait[MAXWAIT+2]; | |
98511a3b | 79 | u_int mxin2_wait[MAXWAIT+2]; |
60f56dfc KM |
80 | u_int cxin_wait[MAXWAIT+2]; |
81 | u_int fxfr_wait[MAXWAIT+2]; | |
82 | u_int sgo_wait[MAXWAIT+2]; | |
83 | #define HIST(h,w) (++h[((w)>MAXWAIT? MAXWAIT : ((w) < 0 ? -1 : (w))) + 1]); | |
84 | #else | |
85 | #define HIST(h,w) | |
86 | #endif | |
87 | ||
88 | #define b_cylin b_resid | |
89 | ||
90 | static void | |
91 | scsiabort(hs, hd, where) | |
92 | register struct scsi_softc *hs; | |
93 | volatile register struct scsidevice *hd; | |
94 | char *where; | |
95 | { | |
96 | int len; | |
592df170 MT |
97 | int maxtries; /* XXX - kludge till I understand whats *supposed* to happen */ |
98 | int startlen; /* XXX - kludge till I understand whats *supposed* to happen */ | |
60f56dfc KM |
99 | u_char junk; |
100 | ||
101 | printf("scsi%d: abort from %s: phase=0x%x, ssts=0x%x, ints=0x%x\n", | |
102 | hs->sc_hc->hp_unit, where, hd->scsi_psns, hd->scsi_ssts, | |
103 | hd->scsi_ints); | |
104 | ||
105 | hd->scsi_ints = hd->scsi_ints; | |
106 | hd->scsi_csr = 0; | |
107 | if (hd->scsi_psns == 0 || (hd->scsi_ssts & SSTS_INITIATOR) == 0) | |
108 | /* no longer connected to scsi target */ | |
109 | return; | |
110 | ||
111 | /* get the number of bytes remaining in current xfer + fudge */ | |
112 | len = (hd->scsi_tch << 16) | (hd->scsi_tcm << 8) | hd->scsi_tcl; | |
113 | ||
114 | /* for that many bus cycles, try to send an abort msg */ | |
592df170 | 115 | for (startlen = (len += 1024); (hd->scsi_ssts & SSTS_INITIATOR) && --len >= 0; ) { |
60f56dfc | 116 | hd->scsi_scmd = SCMD_SET_ATN; |
592df170 | 117 | maxtries = 1000; |
60f56dfc KM |
118 | while ((hd->scsi_psns & PSNS_REQ) == 0) { |
119 | if (! (hd->scsi_ssts & SSTS_INITIATOR)) | |
120 | goto out; | |
121 | DELAY(1); | |
592df170 MT |
122 | if (--maxtries == 0) { |
123 | printf("-- scsiabort gave up after 1000 tries (startlen = %d len = %d)\n", | |
124 | startlen, len); | |
125 | goto out2; | |
126 | } | |
127 | ||
60f56dfc | 128 | } |
592df170 | 129 | out2: |
60f56dfc KM |
130 | if ((hd->scsi_psns & PHASE) == MESG_OUT_PHASE) |
131 | hd->scsi_scmd = SCMD_RST_ATN; | |
132 | hd->scsi_pctl = hd->scsi_psns & PHASE; | |
133 | if (hd->scsi_psns & PHASE_IO) { | |
134 | /* one of the input phases - read & discard a byte */ | |
135 | hd->scsi_scmd = SCMD_SET_ACK; | |
136 | if (hd->scsi_tmod == 0) | |
137 | while (hd->scsi_psns & PSNS_REQ) | |
138 | DELAY(1); | |
139 | junk = hd->scsi_temp; | |
140 | } else { | |
141 | /* one of the output phases - send an abort msg */ | |
142 | hd->scsi_temp = MSG_ABORT; | |
143 | hd->scsi_scmd = SCMD_SET_ACK; | |
144 | if (hd->scsi_tmod == 0) | |
145 | while (hd->scsi_psns & PSNS_REQ) | |
146 | DELAY(1); | |
147 | } | |
148 | hd->scsi_scmd = SCMD_RST_ACK; | |
149 | } | |
150 | out: | |
151 | /* | |
152 | * Either the abort was successful & the bus is disconnected or | |
153 | * the device didn't listen. If the latter, announce the problem. | |
154 | * Either way, reset the card & the SPC. | |
155 | */ | |
156 | if (len < 0 && hs) | |
157 | printf("scsi%d: abort failed. phase=0x%x, ssts=0x%x\n", | |
158 | hs->sc_hc->hp_unit, hd->scsi_psns, hd->scsi_ssts); | |
159 | ||
160 | if (! ((junk = hd->scsi_ints) & INTS_RESEL)) { | |
161 | hd->scsi_sctl |= SCTL_CTRLRST; | |
162 | DELAY(1); | |
163 | hd->scsi_sctl &=~ SCTL_CTRLRST; | |
164 | hd->scsi_hconf = 0; | |
165 | hd->scsi_ints = hd->scsi_ints; | |
166 | } | |
167 | } | |
168 | ||
98511a3b KM |
169 | /* |
170 | * XXX Set/reset long delays. | |
171 | * | |
172 | * if delay == 0, reset default delays | |
173 | * if delay < 0, set both delays to default long initialization values | |
174 | * if delay > 0, set both delays to this value | |
175 | * | |
176 | * Used when a devices is expected to respond slowly (e.g. during | |
177 | * initialization). | |
178 | */ | |
179 | void | |
180 | scsi_delay(delay) | |
181 | int delay; | |
182 | { | |
183 | static int saved_cmd_wait, saved_data_wait; | |
184 | ||
185 | if (delay) { | |
186 | saved_cmd_wait = scsi_cmd_wait; | |
187 | saved_data_wait = scsi_data_wait; | |
188 | if (delay > 0) | |
189 | scsi_cmd_wait = scsi_data_wait = delay; | |
190 | else | |
191 | scsi_cmd_wait = scsi_data_wait = scsi_init_wait; | |
192 | } else { | |
193 | scsi_cmd_wait = saved_cmd_wait; | |
194 | scsi_data_wait = saved_data_wait; | |
195 | } | |
196 | } | |
197 | ||
60f56dfc KM |
198 | int |
199 | scsiinit(hc) | |
200 | register struct hp_ctlr *hc; | |
201 | { | |
202 | register struct scsi_softc *hs = &scsi_softc[hc->hp_unit]; | |
203 | register struct scsidevice *hd = (struct scsidevice *)hc->hp_addr; | |
204 | ||
205 | if ((hd->scsi_id & ID_MASK) != SCSI_ID) | |
206 | return(0); | |
207 | hc->hp_ipl = SCSI_IPL(hd->scsi_csr); | |
208 | hs->sc_hc = hc; | |
209 | hs->sc_dq.dq_unit = hc->hp_unit; | |
210 | hs->sc_dq.dq_driver = &scsidriver; | |
211 | hs->sc_sq.dq_forw = hs->sc_sq.dq_back = &hs->sc_sq; | |
212 | scsi_isr[hc->hp_unit].isr_intr = scsiintr; | |
213 | scsi_isr[hc->hp_unit].isr_ipl = hc->hp_ipl; | |
214 | scsi_isr[hc->hp_unit].isr_arg = hc->hp_unit; | |
215 | isrlink(&scsi_isr[hc->hp_unit]); | |
216 | scsireset(hc->hp_unit); | |
9acfa6cd MH |
217 | /* |
218 | * XXX scale initialization wait according to CPU speed. | |
219 | * Should we do this for all wait? Should we do this at all? | |
220 | */ | |
221 | scsi_init_wait *= cpuspeed; | |
60f56dfc KM |
222 | return(1); |
223 | } | |
224 | ||
225 | void | |
226 | scsireset(unit) | |
227 | register int unit; | |
228 | { | |
229 | register struct scsi_softc *hs = &scsi_softc[unit]; | |
230 | volatile register struct scsidevice *hd = | |
231 | (struct scsidevice *)hs->sc_hc->hp_addr; | |
232 | u_int i; | |
233 | ||
234 | if (hs->sc_flags & SCSI_ALIVE) | |
235 | scsiabort(hs, hd, "reset"); | |
236 | ||
237 | printf("scsi%d: ", unit); | |
238 | ||
239 | hd->scsi_id = 0xFF; | |
240 | DELAY(100); | |
241 | /* | |
242 | * Disable interrupts then reset the FUJI chip. | |
243 | */ | |
244 | hd->scsi_csr = 0; | |
245 | hd->scsi_sctl = SCTL_DISABLE | SCTL_CTRLRST; | |
246 | hd->scsi_scmd = 0; | |
247 | hd->scsi_tmod = 0; | |
248 | hd->scsi_pctl = 0; | |
249 | hd->scsi_temp = 0; | |
250 | hd->scsi_tch = 0; | |
251 | hd->scsi_tcm = 0; | |
252 | hd->scsi_tcl = 0; | |
253 | hd->scsi_ints = 0; | |
254 | ||
255 | if ((hd->scsi_id & ID_WORD_DMA) == 0) { | |
256 | hs->sc_flags |= SCSI_DMA32; | |
257 | printf("32 bit dma, "); | |
258 | } | |
259 | ||
260 | /* Determine Max Synchronous Transfer Rate */ | |
261 | if (scsi_nosync) | |
262 | i = 3; | |
263 | else | |
264 | i = SCSI_SYNC_XFER(hd->scsi_hconf); | |
265 | switch (i) { | |
266 | case 0: | |
267 | hs->sc_sync = TMOD_SYNC | 0x3e; /* 250 nsecs */ | |
268 | printf("250ns sync"); | |
269 | break; | |
270 | case 1: | |
271 | hs->sc_sync = TMOD_SYNC | 0x5e; /* 375 nsecs */ | |
272 | printf("375ns sync"); | |
273 | break; | |
274 | case 2: | |
275 | hs->sc_sync = TMOD_SYNC | 0x7d; /* 500 nsecs */ | |
276 | printf("500ns sync"); | |
277 | break; | |
278 | case 3: | |
279 | hs->sc_sync = 0; | |
280 | printf("async"); | |
281 | break; | |
282 | } | |
283 | ||
284 | /* | |
285 | * Configure the FUJI chip with its SCSI address, all | |
286 | * interrupts enabled & appropriate parity. | |
287 | */ | |
288 | i = (~hd->scsi_hconf) & 0x7; | |
289 | hs->sc_scsi_addr = 1 << i; | |
290 | hd->scsi_bdid = i; | |
291 | if (hd->scsi_hconf & HCONF_PARITY) | |
292 | hd->scsi_sctl = SCTL_DISABLE | SCTL_ABRT_ENAB | | |
293 | SCTL_SEL_ENAB | SCTL_RESEL_ENAB | | |
294 | SCTL_INTR_ENAB | SCTL_PARITY_ENAB; | |
295 | else { | |
296 | hd->scsi_sctl = SCTL_DISABLE | SCTL_ABRT_ENAB | | |
297 | SCTL_SEL_ENAB | SCTL_RESEL_ENAB | | |
298 | SCTL_INTR_ENAB; | |
299 | printf(", no parity"); | |
300 | } | |
301 | hd->scsi_sctl &=~ SCTL_DISABLE; | |
302 | ||
303 | printf(", scsi id %d\n", i); | |
304 | hs->sc_flags |= SCSI_ALIVE; | |
305 | } | |
306 | ||
307 | static void | |
308 | scsierror(hs, hd, ints) | |
309 | register struct scsi_softc *hs; | |
310 | volatile register struct scsidevice *hd; | |
311 | u_char ints; | |
312 | { | |
313 | int unit = hs->sc_hc->hp_unit; | |
314 | char *sep = ""; | |
315 | ||
316 | printf("scsi%d: ", unit); | |
317 | if (ints & INTS_RST) { | |
318 | DELAY(100); | |
319 | if (hd->scsi_hconf & HCONF_SD) | |
320 | printf("spurious RST interrupt"); | |
321 | else | |
322 | printf("hardware error - check fuse"); | |
323 | sep = ", "; | |
324 | } | |
325 | if ((ints & INTS_HARD_ERR) || hd->scsi_serr) { | |
326 | if (hd->scsi_serr & SERR_SCSI_PAR) { | |
327 | printf("%sparity err", sep); | |
328 | sep = ", "; | |
329 | } | |
330 | if (hd->scsi_serr & SERR_SPC_PAR) { | |
331 | printf("%sSPC parity err", sep); | |
332 | sep = ", "; | |
333 | } | |
334 | if (hd->scsi_serr & SERR_TC_PAR) { | |
335 | printf("%sTC parity err", sep); | |
336 | sep = ", "; | |
337 | } | |
338 | if (hd->scsi_serr & SERR_PHASE_ERR) { | |
339 | printf("%sphase err", sep); | |
340 | sep = ", "; | |
341 | } | |
342 | if (hd->scsi_serr & SERR_SHORT_XFR) { | |
343 | printf("%ssync short transfer err", sep); | |
344 | sep = ", "; | |
345 | } | |
346 | if (hd->scsi_serr & SERR_OFFSET) { | |
347 | printf("%ssync offset error", sep); | |
348 | sep = ", "; | |
349 | } | |
350 | } | |
351 | if (ints & INTS_TIMEOUT) | |
352 | printf("%sSPC select timeout error", sep); | |
353 | if (ints & INTS_SRV_REQ) | |
354 | printf("%sspurious SRV_REQ interrupt", sep); | |
355 | if (ints & INTS_CMD_DONE) | |
356 | printf("%sspurious CMD_DONE interrupt", sep); | |
357 | if (ints & INTS_DISCON) | |
358 | printf("%sspurious disconnect interrupt", sep); | |
359 | if (ints & INTS_RESEL) | |
360 | printf("%sspurious reselect interrupt", sep); | |
361 | if (ints & INTS_SEL) | |
362 | printf("%sspurious select interrupt", sep); | |
363 | printf("\n"); | |
364 | } | |
365 | ||
366 | static int | |
367 | issue_select(hd, target, our_addr) | |
368 | volatile register struct scsidevice *hd; | |
369 | u_char target, our_addr; | |
370 | { | |
371 | if (hd->scsi_ssts & (SSTS_INITIATOR|SSTS_TARGET|SSTS_BUSY)) | |
372 | return (1); | |
373 | ||
374 | if (hd->scsi_ints & INTS_DISCON) | |
375 | hd->scsi_ints = INTS_DISCON; | |
376 | ||
377 | hd->scsi_pctl = 0; | |
378 | hd->scsi_temp = (1 << target) | our_addr; | |
379 | /* select timeout is hardcoded to 2ms */ | |
380 | hd->scsi_tch = 0; | |
381 | hd->scsi_tcm = 32; | |
382 | hd->scsi_tcl = 4; | |
383 | ||
384 | hd->scsi_scmd = SCMD_SELECT; | |
385 | return (0); | |
386 | } | |
387 | ||
388 | static int | |
389 | wait_for_select(hd) | |
390 | volatile register struct scsidevice *hd; | |
391 | { | |
392 | u_char ints; | |
393 | ||
394 | while ((ints = hd->scsi_ints) == 0) | |
395 | DELAY(1); | |
396 | hd->scsi_ints = ints; | |
397 | return (!(hd->scsi_ssts & SSTS_INITIATOR)); | |
398 | } | |
399 | ||
400 | static int | |
401 | ixfer_start(hd, len, phase, wait) | |
402 | volatile register struct scsidevice *hd; | |
403 | int len; | |
404 | u_char phase; | |
405 | register int wait; | |
406 | { | |
407 | ||
408 | hd->scsi_tch = len >> 16; | |
409 | hd->scsi_tcm = len >> 8; | |
410 | hd->scsi_tcl = len; | |
411 | hd->scsi_pctl = phase; | |
412 | hd->scsi_tmod = 0; /*XXX*/ | |
413 | hd->scsi_scmd = SCMD_XFR | SCMD_PROG_XFR; | |
414 | ||
415 | /* wait for xfer to start or svc_req interrupt */ | |
416 | while ((hd->scsi_ssts & SSTS_BUSY) == 0) { | |
417 | if (hd->scsi_ints || --wait < 0) { | |
418 | #ifdef DEBUG | |
419 | if (scsi_debug) | |
420 | printf("ixfer_start fail: i%x, w%d\n", | |
421 | hd->scsi_ints, wait); | |
422 | #endif | |
423 | HIST(ixstart_wait, wait) | |
424 | return (0); | |
425 | } | |
426 | DELAY(1); | |
427 | } | |
428 | HIST(ixstart_wait, wait) | |
429 | return (1); | |
430 | } | |
431 | ||
432 | static int | |
433 | ixfer_out(hd, len, buf) | |
434 | volatile register struct scsidevice *hd; | |
435 | int len; | |
436 | register u_char *buf; | |
437 | { | |
438 | register int wait = scsi_data_wait; | |
439 | ||
440 | for (; len > 0; --len) { | |
441 | while (hd->scsi_ssts & SSTS_DREG_FULL) { | |
442 | if (hd->scsi_ints || --wait < 0) { | |
443 | #ifdef DEBUG | |
444 | if (scsi_debug) | |
445 | printf("ixfer_out fail: l%d i%x w%d\n", | |
446 | len, hd->scsi_ints, wait); | |
447 | #endif | |
448 | HIST(ixout_wait, wait) | |
449 | return (len); | |
450 | } | |
451 | DELAY(1); | |
452 | } | |
453 | hd->scsi_dreg = *buf++; | |
454 | } | |
455 | HIST(ixout_wait, wait) | |
456 | return (0); | |
457 | } | |
458 | ||
459 | static void | |
460 | ixfer_in(hd, len, buf) | |
461 | volatile register struct scsidevice *hd; | |
462 | int len; | |
463 | register u_char *buf; | |
464 | { | |
465 | register int wait = scsi_data_wait; | |
466 | ||
467 | for (; len > 0; --len) { | |
468 | while (hd->scsi_ssts & SSTS_DREG_EMPTY) { | |
469 | if (hd->scsi_ints || --wait < 0) { | |
470 | while (! (hd->scsi_ssts & SSTS_DREG_EMPTY)) { | |
471 | *buf++ = hd->scsi_dreg; | |
472 | --len; | |
473 | } | |
474 | #ifdef DEBUG | |
475 | if (scsi_debug) | |
476 | printf("ixfer_in fail: l%d i%x w%d\n", | |
477 | len, hd->scsi_ints, wait); | |
478 | #endif | |
479 | HIST(ixin_wait, wait) | |
480 | return; | |
481 | } | |
482 | DELAY(1); | |
483 | } | |
484 | *buf++ = hd->scsi_dreg; | |
485 | } | |
486 | HIST(ixin_wait, wait) | |
487 | } | |
488 | ||
489 | static int | |
490 | mxfer_in(hd, len, buf, phase) | |
491 | volatile register struct scsidevice *hd; | |
492 | register int len; | |
493 | register u_char *buf; | |
494 | register u_char phase; | |
495 | { | |
496 | register int wait = scsi_cmd_wait; | |
497 | register int i; | |
498 | ||
499 | hd->scsi_tmod = 0; | |
500 | for (i = 0; i < len; ++i) { | |
98511a3b KM |
501 | /* |
502 | * manual sez: reset ATN before ACK is sent. | |
503 | */ | |
504 | if (hd->scsi_psns & PSNS_ATN) | |
505 | hd->scsi_scmd = SCMD_RST_ATN; | |
60f56dfc KM |
506 | /* |
507 | * wait for the request line (which says the target | |
508 | * wants to give us data). If the phase changes while | |
509 | * we're waiting, we're done. | |
510 | */ | |
511 | while ((hd->scsi_psns & PSNS_REQ) == 0) { | |
512 | if (--wait < 0) { | |
513 | HIST(mxin_wait, wait) | |
514 | return (-1); | |
515 | } | |
516 | if ((hd->scsi_psns & PHASE) != phase || | |
517 | (hd->scsi_ssts & SSTS_INITIATOR) == 0) | |
518 | goto out; | |
519 | ||
520 | DELAY(1); | |
521 | } | |
522 | /* | |
523 | * set ack (which says we're ready for the data, wait for | |
524 | * req to go away (target says data is available), grab the | |
525 | * data, then reset ack (say we've got the data). | |
526 | */ | |
527 | hd->scsi_pctl = phase; | |
528 | hd->scsi_scmd = SCMD_SET_ACK; | |
529 | while (hd->scsi_psns & PSNS_REQ) { | |
530 | if (--wait < 0) { | |
531 | HIST(mxin_wait, wait) | |
532 | return (-2); | |
533 | } | |
534 | DELAY(1); | |
535 | } | |
536 | *buf++ = hd->scsi_temp; | |
537 | hd->scsi_scmd = SCMD_RST_ACK; | |
60f56dfc KM |
538 | } |
539 | out: | |
540 | HIST(mxin_wait, wait) | |
98511a3b KM |
541 | /* |
542 | * Wait for manual transfer to finish. | |
543 | * Avoids occasional "unexpected phase" errors in finishxfer | |
544 | * formerly addressed by per-slave delays. | |
545 | */ | |
546 | wait = scsi_cmd_wait; | |
547 | while ((hd->scsi_ssts & SSTS_ACTIVE) == SSTS_INITIATOR) { | |
548 | if (--wait < 0) | |
549 | break; | |
550 | DELAY(1); | |
551 | } | |
552 | HIST(mxin2_wait, wait) | |
60f56dfc KM |
553 | return (i); |
554 | } | |
555 | ||
556 | /* | |
557 | * SCSI 'immediate' command: issue a command to some SCSI device | |
558 | * and get back an 'immediate' response (i.e., do programmed xfer | |
559 | * to get the response data). 'cbuf' is a buffer containing a scsi | |
560 | * command of length clen bytes. 'buf' is a buffer of length 'len' | |
561 | * bytes for data. The transfer direction is determined by the device | |
562 | * (i.e., by the scsi bus data xfer phase). If 'len' is zero, the | |
563 | * command must supply no data. 'xferphase' is the bus phase the | |
564 | * caller expects to happen after the command is issued. It should | |
565 | * be one of DATA_IN_PHASE, DATA_OUT_PHASE or STATUS_PHASE. | |
566 | */ | |
567 | static int | |
568 | scsiicmd(hs, target, cbuf, clen, buf, len, xferphase) | |
569 | struct scsi_softc *hs; | |
570 | int target; | |
571 | u_char *cbuf; | |
572 | int clen; | |
573 | u_char *buf; | |
574 | int len; | |
575 | u_char xferphase; | |
576 | { | |
577 | volatile register struct scsidevice *hd = | |
578 | (struct scsidevice *)hs->sc_hc->hp_addr; | |
579 | u_char phase, ints; | |
580 | register int wait; | |
581 | ||
582 | /* select the SCSI bus (it's an error if bus isn't free) */ | |
583 | if (issue_select(hd, target, hs->sc_scsi_addr)) | |
584 | return (-1); | |
585 | if (wait_for_select(hd)) | |
586 | return (-1); | |
587 | /* | |
588 | * Wait for a phase change (or error) then let the device | |
589 | * sequence us through the various SCSI phases. | |
590 | */ | |
591 | hs->sc_stat[0] = 0xff; | |
592 | hs->sc_msg[0] = 0xff; | |
593 | phase = CMD_PHASE; | |
594 | while (1) { | |
595 | wait = scsi_cmd_wait; | |
596 | switch (phase) { | |
597 | ||
598 | case CMD_PHASE: | |
599 | if (ixfer_start(hd, clen, phase, wait)) | |
600 | if (ixfer_out(hd, clen, cbuf)) | |
601 | goto abort; | |
602 | phase = xferphase; | |
603 | break; | |
604 | ||
605 | case DATA_IN_PHASE: | |
606 | if (len <= 0) | |
607 | goto abort; | |
608 | wait = scsi_data_wait; | |
609 | if (ixfer_start(hd, len, phase, wait) || | |
610 | !(hd->scsi_ssts & SSTS_DREG_EMPTY)) | |
611 | ixfer_in(hd, len, buf); | |
612 | phase = STATUS_PHASE; | |
613 | break; | |
614 | ||
615 | case DATA_OUT_PHASE: | |
616 | if (len <= 0) | |
617 | goto abort; | |
618 | wait = scsi_data_wait; | |
619 | if (ixfer_start(hd, len, phase, wait)) { | |
620 | if (ixfer_out(hd, len, buf)) | |
621 | goto abort; | |
622 | } | |
623 | phase = STATUS_PHASE; | |
624 | break; | |
625 | ||
626 | case STATUS_PHASE: | |
627 | wait = scsi_data_wait; | |
628 | if (ixfer_start(hd, sizeof(hs->sc_stat), phase, wait) || | |
629 | !(hd->scsi_ssts & SSTS_DREG_EMPTY)) | |
630 | ixfer_in(hd, sizeof(hs->sc_stat), hs->sc_stat); | |
631 | phase = MESG_IN_PHASE; | |
632 | break; | |
633 | ||
634 | case MESG_IN_PHASE: | |
635 | if (ixfer_start(hd, sizeof(hs->sc_msg), phase, wait) || | |
636 | !(hd->scsi_ssts & SSTS_DREG_EMPTY)) { | |
637 | ixfer_in(hd, sizeof(hs->sc_msg), hs->sc_msg); | |
638 | hd->scsi_scmd = SCMD_RST_ACK; | |
639 | } | |
640 | phase = BUS_FREE_PHASE; | |
641 | break; | |
642 | ||
643 | case BUS_FREE_PHASE: | |
644 | goto out; | |
645 | ||
646 | default: | |
647 | printf("scsi%d: unexpected phase %d in icmd from %d\n", | |
648 | hs->sc_hc->hp_unit, phase, target); | |
649 | goto abort; | |
650 | } | |
651 | /* wait for last command to complete */ | |
652 | while ((ints = hd->scsi_ints) == 0) { | |
653 | if (--wait < 0) { | |
654 | HIST(cxin_wait, wait) | |
655 | goto abort; | |
656 | } | |
657 | DELAY(1); | |
658 | } | |
659 | HIST(cxin_wait, wait) | |
660 | hd->scsi_ints = ints; | |
661 | if (ints & INTS_SRV_REQ) | |
662 | phase = hd->scsi_psns & PHASE; | |
663 | else if (ints & INTS_DISCON) | |
664 | goto out; | |
665 | else if ((ints & INTS_CMD_DONE) == 0) { | |
666 | scsierror(hs, hd, ints); | |
667 | goto abort; | |
668 | } | |
669 | } | |
670 | abort: | |
671 | scsiabort(hs, hd, "icmd"); | |
672 | out: | |
673 | return (hs->sc_stat[0]); | |
674 | } | |
675 | ||
676 | /* | |
677 | * Finish SCSI xfer command: After the completion interrupt from | |
678 | * a read/write operation, sequence through the final phases in | |
679 | * programmed i/o. This routine is a lot like scsiicmd except we | |
680 | * skip (and don't allow) the select, cmd out and data in/out phases. | |
681 | */ | |
682 | static void | |
683 | finishxfer(hs, hd, target) | |
684 | struct scsi_softc *hs; | |
685 | volatile register struct scsidevice *hd; | |
686 | int target; | |
687 | { | |
688 | u_char phase, ints; | |
689 | ||
690 | /* | |
691 | * We specified padding xfer so we ended with either a phase | |
692 | * change interrupt (normal case) or an error interrupt (handled | |
693 | * elsewhere). Reset the board dma logic then try to get the | |
694 | * completion status & command done msg. The reset confuses | |
695 | * the SPC REQ/ACK logic so we have to do any status/msg input | |
696 | * operations via 'manual xfer'. | |
697 | */ | |
698 | if (hd->scsi_ssts & SSTS_BUSY) { | |
699 | int wait = scsi_cmd_wait; | |
700 | ||
701 | /* wait for dma operation to finish */ | |
702 | while (hd->scsi_ssts & SSTS_BUSY) { | |
703 | if (--wait < 0) { | |
704 | #ifdef DEBUG | |
705 | if (scsi_debug) | |
706 | printf("finishxfer fail: ssts %x\n", | |
707 | hd->scsi_ssts); | |
708 | #endif | |
709 | HIST(fxfr_wait, wait) | |
710 | goto abort; | |
711 | } | |
712 | } | |
713 | HIST(fxfr_wait, wait) | |
714 | } | |
715 | hd->scsi_scmd |= SCMD_PROG_XFR; | |
716 | hd->scsi_sctl |= SCTL_CTRLRST; | |
717 | DELAY(1); | |
718 | hd->scsi_sctl &=~ SCTL_CTRLRST; | |
719 | hd->scsi_hconf = 0; | |
592df170 MT |
720 | /* |
721 | * The following delay is definitely needed when trying to | |
722 | * write on a write protected disk (in the optical jukebox anyways), | |
723 | * but we shall see if other unexplained machine freezeups | |
724 | * also stop occuring... A value of 5 seems to work but | |
725 | * 10 seems safer considering the potential consequences. | |
726 | */ | |
727 | DELAY(10); | |
60f56dfc KM |
728 | hs->sc_stat[0] = 0xff; |
729 | hs->sc_msg[0] = 0xff; | |
730 | hd->scsi_csr = 0; | |
731 | hd->scsi_ints = ints = hd->scsi_ints; | |
732 | while (1) { | |
733 | phase = hd->scsi_psns & PHASE; | |
734 | switch (phase) { | |
735 | ||
736 | case STATUS_PHASE: | |
737 | if (mxfer_in(hd, sizeof(hs->sc_stat), hs->sc_stat, | |
738 | phase) <= 0) | |
739 | goto abort; | |
740 | break; | |
741 | ||
742 | case MESG_IN_PHASE: | |
743 | if (mxfer_in(hd, sizeof(hs->sc_msg), hs->sc_msg, | |
744 | phase) < 0) | |
745 | goto abort; | |
746 | break; | |
747 | ||
748 | case BUS_FREE_PHASE: | |
749 | return; | |
750 | ||
751 | default: | |
752 | printf("scsi%d: unexpected phase %d in finishxfer from %d\n", | |
753 | hs->sc_hc->hp_unit, phase, target); | |
754 | goto abort; | |
755 | } | |
756 | if (ints = hd->scsi_ints) { | |
757 | hd->scsi_ints = ints; | |
758 | if (ints & INTS_DISCON) | |
759 | return; | |
760 | else if (ints & ~(INTS_SRV_REQ|INTS_CMD_DONE)) { | |
761 | scsierror(hs, hd, ints); | |
762 | break; | |
763 | } | |
764 | } | |
765 | if ((hd->scsi_ssts & SSTS_INITIATOR) == 0) | |
766 | return; | |
767 | } | |
768 | abort: | |
769 | scsiabort(hs, hd, "finishxfer"); | |
770 | hs->sc_stat[0] = 0xfe; | |
771 | } | |
772 | ||
773 | int | |
774 | scsi_test_unit_rdy(ctlr, slave, unit) | |
775 | int ctlr, slave, unit; | |
776 | { | |
777 | register struct scsi_softc *hs = &scsi_softc[ctlr]; | |
778 | static struct scsi_cdb6 cdb = { CMD_TEST_UNIT_READY }; | |
779 | ||
780 | cdb.lun = unit; | |
781 | return (scsiicmd(hs, slave, &cdb, sizeof(cdb), (u_char *)0, 0, | |
782 | STATUS_PHASE)); | |
783 | } | |
784 | ||
785 | int | |
786 | scsi_request_sense(ctlr, slave, unit, buf, len) | |
787 | int ctlr, slave, unit; | |
788 | u_char *buf; | |
789 | unsigned len; | |
790 | { | |
791 | register struct scsi_softc *hs = &scsi_softc[ctlr]; | |
792 | static struct scsi_cdb6 cdb = { CMD_REQUEST_SENSE }; | |
793 | ||
794 | cdb.lun = unit; | |
795 | cdb.len = len; | |
796 | return (scsiicmd(hs, slave, &cdb, sizeof(cdb), buf, len, DATA_IN_PHASE)); | |
797 | } | |
798 | ||
799 | int | |
800 | scsi_immed_command(ctlr, slave, unit, cdb, buf, len, rd) | |
801 | int ctlr, slave, unit; | |
802 | struct scsi_fmt_cdb *cdb; | |
803 | u_char *buf; | |
804 | unsigned len; | |
805 | { | |
806 | register struct scsi_softc *hs = &scsi_softc[ctlr]; | |
807 | ||
808 | cdb->cdb[1] |= unit << 5; | |
809 | return (scsiicmd(hs, slave, cdb->cdb, cdb->len, buf, len, | |
810 | rd != 0? DATA_IN_PHASE : DATA_OUT_PHASE)); | |
811 | } | |
812 | ||
813 | /* | |
814 | * The following routines are test-and-transfer i/o versions of read/write | |
815 | * for things like reading disk labels and writing core dumps. The | |
816 | * routine scsigo should be used for normal data transfers, NOT these | |
817 | * routines. | |
818 | */ | |
819 | int | |
820 | scsi_tt_read(ctlr, slave, unit, buf, len, blk, bshift) | |
821 | int ctlr, slave, unit; | |
822 | u_char *buf; | |
823 | u_int len; | |
824 | daddr_t blk; | |
825 | int bshift; | |
826 | { | |
827 | register struct scsi_softc *hs = &scsi_softc[ctlr]; | |
828 | struct scsi_cdb10 cdb; | |
829 | int stat; | |
830 | int old_wait = scsi_data_wait; | |
831 | ||
832 | scsi_data_wait = 300000; | |
833 | bzero(&cdb, sizeof(cdb)); | |
834 | cdb.cmd = CMD_READ_EXT; | |
835 | cdb.lun = unit; | |
836 | blk >>= bshift; | |
837 | cdb.lbah = blk >> 24; | |
838 | cdb.lbahm = blk >> 16; | |
839 | cdb.lbalm = blk >> 8; | |
840 | cdb.lbal = blk; | |
841 | cdb.lenh = len >> (8 + DEV_BSHIFT + bshift); | |
842 | cdb.lenl = len >> (DEV_BSHIFT + bshift); | |
843 | stat = scsiicmd(hs, slave, &cdb, sizeof(cdb), buf, len, DATA_IN_PHASE); | |
844 | scsi_data_wait = old_wait; | |
845 | return (stat); | |
846 | } | |
847 | ||
848 | int | |
849 | scsi_tt_write(ctlr, slave, unit, buf, len, blk, bshift) | |
850 | int ctlr, slave, unit; | |
851 | u_char *buf; | |
852 | u_int len; | |
853 | daddr_t blk; | |
854 | int bshift; | |
855 | { | |
856 | register struct scsi_softc *hs = &scsi_softc[ctlr]; | |
857 | struct scsi_cdb10 cdb; | |
858 | int stat; | |
859 | int old_wait = scsi_data_wait; | |
860 | ||
861 | scsi_data_wait = 300000; | |
862 | ||
863 | bzero(&cdb, sizeof(cdb)); | |
864 | cdb.cmd = CMD_WRITE_EXT; | |
865 | cdb.lun = unit; | |
866 | blk >>= bshift; | |
867 | cdb.lbah = blk >> 24; | |
868 | cdb.lbahm = blk >> 16; | |
869 | cdb.lbalm = blk >> 8; | |
870 | cdb.lbal = blk; | |
871 | cdb.lenh = len >> (8 + DEV_BSHIFT + bshift); | |
872 | cdb.lenl = len >> (DEV_BSHIFT + bshift); | |
873 | stat = scsiicmd(hs, slave, &cdb, sizeof(cdb), buf, len, DATA_OUT_PHASE); | |
874 | scsi_data_wait = old_wait; | |
875 | return (stat); | |
876 | } | |
877 | ||
60f56dfc KM |
878 | int |
879 | scsireq(dq) | |
880 | register struct devqueue *dq; | |
881 | { | |
882 | register struct devqueue *hq; | |
883 | ||
884 | hq = &scsi_softc[dq->dq_ctlr].sc_sq; | |
885 | insque(dq, hq->dq_back); | |
886 | if (dq->dq_back == hq) | |
887 | return(1); | |
888 | return(0); | |
889 | } | |
890 | ||
891 | int | |
892 | scsiustart(unit) | |
893 | int unit; | |
894 | { | |
895 | register struct scsi_softc *hs = &scsi_softc[unit]; | |
896 | ||
897 | hs->sc_dq.dq_ctlr = DMA0 | DMA1; | |
9acfa6cd | 898 | hs->sc_flags |= SCSI_HAVEDMA; |
60f56dfc KM |
899 | if (dmareq(&hs->sc_dq)) |
900 | return(1); | |
901 | return(0); | |
902 | } | |
903 | ||
904 | void | |
905 | scsistart(unit) | |
906 | int unit; | |
907 | { | |
908 | register struct devqueue *dq; | |
909 | ||
910 | dq = scsi_softc[unit].sc_sq.dq_forw; | |
911 | (dq->dq_driver->d_go)(dq->dq_unit); | |
912 | } | |
913 | ||
914 | int | |
915 | scsigo(ctlr, slave, unit, bp, cdb, pad) | |
916 | int ctlr, slave, unit; | |
917 | struct buf *bp; | |
918 | struct scsi_fmt_cdb *cdb; | |
919 | int pad; | |
920 | { | |
921 | register struct scsi_softc *hs = &scsi_softc[ctlr]; | |
922 | volatile register struct scsidevice *hd = | |
923 | (struct scsidevice *)hs->sc_hc->hp_addr; | |
924 | int i, dmaflags; | |
925 | u_char phase, ints, cmd; | |
926 | ||
927 | cdb->cdb[1] |= unit << 5; | |
928 | ||
929 | /* select the SCSI bus (it's an error if bus isn't free) */ | |
930 | if (issue_select(hd, slave, hs->sc_scsi_addr) || wait_for_select(hd)) { | |
9acfa6cd MH |
931 | if (hs->sc_flags & SCSI_HAVEDMA) { |
932 | hs->sc_flags &=~ SCSI_HAVEDMA; | |
933 | dmafree(&hs->sc_dq); | |
934 | } | |
60f56dfc KM |
935 | return (1); |
936 | } | |
937 | /* | |
938 | * Wait for a phase change (or error) then let the device | |
939 | * sequence us through command phase (we may have to take | |
940 | * a msg in/out before doing the command). If the disk has | |
941 | * to do a seek, it may be a long time until we get a change | |
942 | * to data phase so, in the absense of an explicit phase | |
943 | * change, we assume data phase will be coming up and tell | |
944 | * the SPC to start a transfer whenever it does. We'll get | |
945 | * a service required interrupt later if this assumption is | |
946 | * wrong. Otherwise we'll get a service required int when | |
947 | * the transfer changes to status phase. | |
948 | */ | |
949 | phase = CMD_PHASE; | |
950 | while (1) { | |
951 | register int wait = scsi_cmd_wait; | |
952 | ||
953 | switch (phase) { | |
954 | ||
955 | case CMD_PHASE: | |
956 | if (ixfer_start(hd, cdb->len, phase, wait)) | |
957 | if (ixfer_out(hd, cdb->len, cdb->cdb)) | |
958 | goto abort; | |
959 | break; | |
960 | ||
961 | case MESG_IN_PHASE: | |
962 | if (ixfer_start(hd, sizeof(hs->sc_msg), phase, wait)|| | |
963 | !(hd->scsi_ssts & SSTS_DREG_EMPTY)) { | |
964 | ixfer_in(hd, sizeof(hs->sc_msg), hs->sc_msg); | |
965 | hd->scsi_scmd = SCMD_RST_ACK; | |
966 | } | |
967 | phase = BUS_FREE_PHASE; | |
968 | break; | |
969 | ||
970 | case DATA_IN_PHASE: | |
971 | case DATA_OUT_PHASE: | |
972 | goto out; | |
973 | ||
974 | default: | |
975 | printf("scsi%d: unexpected phase %d in go from %d\n", | |
976 | hs->sc_hc->hp_unit, phase, slave); | |
977 | goto abort; | |
978 | } | |
979 | while ((ints = hd->scsi_ints) == 0) { | |
980 | if (--wait < 0) { | |
981 | HIST(sgo_wait, wait) | |
982 | goto abort; | |
983 | } | |
984 | DELAY(1); | |
985 | } | |
986 | HIST(sgo_wait, wait) | |
987 | hd->scsi_ints = ints; | |
988 | if (ints & INTS_SRV_REQ) | |
989 | phase = hd->scsi_psns & PHASE; | |
990 | else if (ints & INTS_CMD_DONE) | |
991 | goto out; | |
992 | else { | |
993 | scsierror(hs, hd, ints); | |
994 | goto abort; | |
995 | } | |
996 | } | |
997 | out: | |
998 | /* | |
999 | * Reset the card dma logic, setup the dma channel then | |
1000 | * get the dio part of the card set for a dma xfer. | |
1001 | */ | |
1002 | hd->scsi_hconf = 0; | |
d989d7c8 | 1003 | cmd = CSR_IE; |
60f56dfc | 1004 | dmaflags = DMAGO_NOINT; |
d989d7c8 KM |
1005 | if (scsi_pridma) |
1006 | dmaflags |= DMAGO_PRI; | |
60f56dfc KM |
1007 | if (bp->b_flags & B_READ) |
1008 | dmaflags |= DMAGO_READ; | |
1009 | if ((hs->sc_flags & SCSI_DMA32) && | |
1010 | ((int)bp->b_un.b_addr & 3) == 0 && (bp->b_bcount & 3) == 0) { | |
1011 | cmd |= CSR_DMA32; | |
1012 | dmaflags |= DMAGO_LWORD; | |
1013 | } else | |
1014 | dmaflags |= DMAGO_WORD; | |
1015 | dmago(hs->sc_dq.dq_ctlr, bp->b_un.b_addr, bp->b_bcount, dmaflags); | |
1016 | ||
1017 | if (bp->b_flags & B_READ) { | |
1018 | cmd |= CSR_DMAIN; | |
1019 | phase = DATA_IN_PHASE; | |
1020 | } else | |
1021 | phase = DATA_OUT_PHASE; | |
d989d7c8 KM |
1022 | /* |
1023 | * DMA enable bits must be set after size and direction bits. | |
1024 | */ | |
60f56dfc | 1025 | hd->scsi_csr = cmd; |
d989d7c8 | 1026 | hd->scsi_csr |= (CSR_DE0 << hs->sc_dq.dq_ctlr); |
60f56dfc KM |
1027 | /* |
1028 | * Setup the SPC for the transfer. We don't want to take | |
1029 | * first a command complete then a service required interrupt | |
1030 | * at the end of the transfer so we try to disable the cmd | |
1031 | * complete by setting the transfer counter to more bytes | |
1032 | * than we expect. (XXX - This strategy may have to be | |
1033 | * modified to deal with devices that return variable length | |
1034 | * blocks, e.g., some tape drives.) | |
1035 | */ | |
1036 | cmd = SCMD_XFR; | |
1037 | i = (unsigned)bp->b_bcount; | |
1038 | if (pad) { | |
1039 | cmd |= SCMD_PAD; | |
1040 | /* | |
1041 | * XXX - If we don't do this, the last 2 or 4 bytes | |
1042 | * (depending on word/lword DMA) of a read get trashed. | |
1043 | * It looks like it is necessary for the DMA to complete | |
1044 | * before the SPC goes into "pad mode"??? Note: if we | |
1045 | * also do this on a write, the request never completes. | |
1046 | */ | |
1047 | if (bp->b_flags & B_READ) | |
1048 | i += 2; | |
1049 | #ifdef DEBUG | |
1050 | hs->sc_flags |= SCSI_PAD; | |
1051 | if (i & 1) | |
1052 | printf("scsi%d: odd byte count: %d bytes @ %d\n", | |
1053 | ctlr, i, bp->b_cylin); | |
1054 | #endif | |
1055 | } else | |
1056 | i += 4; | |
1057 | hd->scsi_tch = i >> 16; | |
1058 | hd->scsi_tcm = i >> 8; | |
1059 | hd->scsi_tcl = i; | |
1060 | hd->scsi_pctl = phase; | |
1061 | hd->scsi_tmod = 0; | |
1062 | hd->scsi_scmd = cmd; | |
1063 | hs->sc_flags |= SCSI_IO; | |
1064 | return (0); | |
1065 | abort: | |
1066 | scsiabort(hs, hd, "go"); | |
9acfa6cd | 1067 | hs->sc_flags &=~ SCSI_HAVEDMA; |
60f56dfc KM |
1068 | dmafree(&hs->sc_dq); |
1069 | return (1); | |
1070 | } | |
1071 | ||
1072 | void | |
1073 | scsidone(unit) | |
1074 | register int unit; | |
1075 | { | |
1076 | volatile register struct scsidevice *hd = | |
1077 | (struct scsidevice *)scsi_softc[unit].sc_hc->hp_addr; | |
1078 | ||
d989d7c8 KM |
1079 | #ifdef DEBUG |
1080 | if (scsi_debug) | |
1081 | printf("scsi%d: done called!\n"); | |
1082 | #endif | |
60f56dfc KM |
1083 | /* dma operation is done -- turn off card dma */ |
1084 | hd->scsi_csr &=~ (CSR_DE1|CSR_DE0); | |
1085 | } | |
1086 | ||
1087 | int | |
1088 | scsiintr(unit) | |
1089 | register int unit; | |
1090 | { | |
1091 | register struct scsi_softc *hs = &scsi_softc[unit]; | |
1092 | volatile register struct scsidevice *hd = | |
1093 | (struct scsidevice *)hs->sc_hc->hp_addr; | |
1094 | register u_char ints; | |
1095 | register struct devqueue *dq; | |
1096 | ||
1097 | if ((hd->scsi_csr & (CSR_IE|CSR_IR)) != (CSR_IE|CSR_IR)) | |
1098 | return (0); | |
1099 | ||
1100 | ints = hd->scsi_ints; | |
1101 | if ((ints & INTS_SRV_REQ) && (hs->sc_flags & SCSI_IO)) { | |
1102 | /* | |
1103 | * this should be the normal i/o completion case. | |
1104 | * get the status & cmd complete msg then let the | |
1105 | * device driver look at what happened. | |
1106 | */ | |
1107 | #ifdef DEBUG | |
1108 | int len = (hd->scsi_tch << 16) | (hd->scsi_tcm << 8) | | |
1109 | hd->scsi_tcl; | |
1110 | if (!(hs->sc_flags & SCSI_PAD)) | |
1111 | len -= 4; | |
60f56dfc KM |
1112 | hs->sc_flags &=~ SCSI_PAD; |
1113 | #endif | |
1114 | dq = hs->sc_sq.dq_forw; | |
98511a3b | 1115 | finishxfer(hs, hd, dq->dq_slave); |
9acfa6cd | 1116 | hs->sc_flags &=~ (SCSI_IO|SCSI_HAVEDMA); |
60f56dfc KM |
1117 | dmafree(&hs->sc_dq); |
1118 | (dq->dq_driver->d_intr)(dq->dq_unit, hs->sc_stat[0]); | |
1119 | } else { | |
1120 | /* Something unexpected happened -- deal with it. */ | |
1121 | hd->scsi_ints = ints; | |
1122 | hd->scsi_csr = 0; | |
1123 | scsierror(hs, hd, ints); | |
1124 | scsiabort(hs, hd, "intr"); | |
1125 | if (hs->sc_flags & SCSI_IO) { | |
9acfa6cd | 1126 | hs->sc_flags &=~ (SCSI_IO|SCSI_HAVEDMA); |
60f56dfc KM |
1127 | dmafree(&hs->sc_dq); |
1128 | dq = hs->sc_sq.dq_forw; | |
1129 | (dq->dq_driver->d_intr)(dq->dq_unit, -1); | |
1130 | } | |
1131 | } | |
1132 | return(1); | |
1133 | } | |
1134 | ||
1135 | void | |
1136 | scsifree(dq) | |
1137 | register struct devqueue *dq; | |
1138 | { | |
1139 | register struct devqueue *hq; | |
1140 | ||
1141 | hq = &scsi_softc[dq->dq_ctlr].sc_sq; | |
1142 | remque(dq); | |
1143 | if ((dq = hq->dq_forw) != hq) | |
1144 | (dq->dq_driver->d_start)(dq->dq_unit); | |
1145 | } | |
98511a3b KM |
1146 | |
1147 | /* | |
1148 | * (XXX) The following routine is needed for the SCSI tape driver | |
1149 | * to read odd-size records. | |
1150 | */ | |
1151 | ||
1152 | #include "st.h" | |
1153 | #if NST > 0 | |
1154 | int | |
1155 | scsi_tt_oddio(ctlr, slave, unit, buf, len, b_flags, freedma) | |
1156 | int ctlr, slave, unit, b_flags; | |
1157 | u_char *buf; | |
1158 | u_int len; | |
1159 | { | |
1160 | register struct scsi_softc *hs = &scsi_softc[ctlr]; | |
1161 | struct scsi_cdb6 cdb; | |
1162 | u_char iphase; | |
1163 | int stat; | |
1164 | ||
9acfa6cd MH |
1165 | #ifdef DEBUG |
1166 | if (freedma && (hs->sc_flags & SCSI_HAVEDMA) == 0 || | |
1167 | !freedma && (hs->sc_flags & SCSI_HAVEDMA)) | |
1168 | printf("oddio: freedma (%d) inconsistency (flags=%x)\n", | |
1169 | freedma, hs->sc_flags); | |
1170 | #endif | |
98511a3b KM |
1171 | /* |
1172 | * First free any DMA channel that was allocated. | |
1173 | * We can't use DMA to do this transfer. | |
1174 | */ | |
9acfa6cd MH |
1175 | if (freedma) { |
1176 | hs->sc_flags &=~ SCSI_HAVEDMA; | |
98511a3b | 1177 | dmafree(hs->sc_dq); |
9acfa6cd | 1178 | } |
98511a3b KM |
1179 | /* |
1180 | * Initialize command block | |
1181 | */ | |
1182 | bzero(&cdb, sizeof(cdb)); | |
1183 | cdb.lun = unit; | |
1184 | cdb.lbam = (len >> 16) & 0xff; | |
1185 | cdb.lbal = (len >> 8) & 0xff; | |
1186 | cdb.len = len & 0xff; | |
1187 | if (buf == 0) { | |
1188 | cdb.cmd = CMD_SPACE; | |
1189 | cdb.lun |= 0x00; | |
1190 | len = 0; | |
1191 | iphase = MESG_IN_PHASE; | |
1192 | } else if (b_flags & B_READ) { | |
1193 | cdb.cmd = CMD_READ; | |
1194 | iphase = DATA_IN_PHASE; | |
1195 | } else { | |
1196 | cdb.cmd = CMD_WRITE; | |
1197 | iphase = DATA_OUT_PHASE; | |
1198 | } | |
1199 | /* | |
1200 | * Perform command (with very long delays) | |
1201 | */ | |
1202 | scsi_delay(30000000); | |
1203 | stat = scsiicmd(hs, slave, &cdb, sizeof(cdb), buf, len, iphase); | |
1204 | scsi_delay(0); | |
1205 | return (stat); | |
1206 | } | |
1207 | #endif | |
60f56dfc | 1208 | #endif |