projects / unix-history / blame
| Commit | Line | Data |
|---|---|---|
| da7c5cc6 KM |
1 | /* |
| 2 | * Copyright (c) 1982 Regents of the University of California. | |
| 3 | * All rights reserved. The Berkeley software License Agreement | |
| 4 | * specifies the terms and conditions for redistribution. | |
| 5 | * | |
| 667b3286 | 6 | * @(#)if_ecreg.h 6.4 (Berkeley) %G% |
| da7c5cc6 | 7 | */ |
| b1953f96 BF |
8 | |
| 9 | /* | |
| 10 | * 3Com Ethernet controller registers. | |
| 11 | */ | |
| 12 | struct ecdevice { | |
| 13 | short ec_rcr; /* Receive Control Register */ | |
| 14 | short ec_xcr; /* Transmit Control Register */ | |
| 15 | }; | |
| 16 | ||
| 17 | /* | |
| 18 | * Control and status bits -- rcr | |
| 19 | */ | |
| 20 | #define EC_SPIE 0x8000 /* set parity interrupt enable */ | |
| 21 | #define EC_ASTEP 0x4000 /* increment address counter */ | |
| 22 | #define EC_AROM 0x2000 /* 1: Use address ROM, 0: use RAM */ | |
| 23 | #define EC_PE 0x2000 /* Parity error */ | |
| 24 | #define EC_AWCLK 0x1000 /* address write clock bit */ | |
| 25 | #define EC_PIE 0x1000 /* Parity interrupt enable (read) */ | |
| 26 | #define EC_ADATA 0x0f00 /* address/filtering */ | |
| 27 | #define EC_RDONE 0x0080 /* receive done */ | |
| a26646de | 28 | #define EC_MDISAB 0x0080 /* memory disable */ |
| b1953f96 BF |
29 | #define EC_RINTEN 0x0040 /* receive interrupt enable */ |
| 30 | #define EC_RCLR 0x0020 /* clear RDONE bit */ | |
| 31 | #define EC_RWBN 0x0010 /* submit buffer for receive */ | |
| 32 | #define EC_RBN 0x000f /* buffer number */ | |
| 33 | ||
| 34 | #define EC_RBITS "\10\16PE\15PIE\10RDONE\7RINTEN" | |
| 35 | ||
| 36 | /* | |
| 37 | * Control and status bits -- xcr | |
| 38 | */ | |
| 39 | #define EC_JAM 0x8000 /* collision dectected */ | |
| 40 | #define EC_JINTEN 0x4000 /* collision interrupt enable */ | |
| 41 | #define EC_JCLR 0x2000 /* clear collision detect */ | |
| 42 | #define EC_UECLR 0x0100 /* reset controller */ | |
| 43 | #define EC_XDONE 0x0080 /* transmit done */ | |
| 44 | #define EC_XINTEN 0x0040 /* transmit interrupt enable */ | |
| 45 | #define EC_XCLR 0x0020 /* clear XDONE bit */ | |
| 46 | #define EC_XWBN 0x0010 /* submit buffer for transmit */ | |
| 47 | #define EC_XBN 0x000f /* buffer number */ | |
| 48 | ||
| 49 | #define EC_XBITS "\10\20JAM\17JINTEN\10XDONE\7XINTEN" | |
| 50 | ||
| 51 | /* | |
| 52 | * Useful combinations | |
| 53 | */ | |
| f88925fb | 54 | #define EC_READ (0x600|EC_RINTEN|EC_RWBN) |
| b1953f96 | 55 | #define EC_WRITE (EC_JINTEN|EC_XINTEN|EC_XWBN) |
| 58a58893 | 56 | #define EC_CLEAR (EC_JINTEN|EC_XINTEN|EC_JCLR) |
| b1953f96 BF |
57 | |
| 58 | /* | |
| 59 | * Buffer number definitions | |
| 60 | */ | |
| 61 | #define ECTBF 0 /* Buffer for transmit */ | |
| 62 | #define ECRLBF 1 /* First buffer for receive */ | |
| 63 | #define ECRHBF 15 /* Last buffer for receive */ | |
| 64 | ||
| 65 | #define ECRDOFF 528 /* Packet offset in read buffer */ |