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63665984 BJ |
1 | /* if_dmc.c 4.1 82/02/08 */ |
2 | ||
3 | #include "dmc.h" | |
4 | #if NDMC > 0 | |
5 | #define printd if(dmcdebug)printf | |
6 | int dmcdebug = 1; | |
7 | /* | |
8 | * DMC11 device driver, internet version | |
9 | * | |
10 | * TODO | |
11 | * allow more than one outstanding read or write. | |
12 | */ | |
13 | ||
14 | #include "../h/param.h" | |
15 | #include "../h/systm.h" | |
16 | #include "../h/mbuf.h" | |
17 | #include "../h/pte.h" | |
18 | #include "../h/buf.h" | |
19 | #include "../h/tty.h" | |
20 | #include "../h/protosw.h" | |
21 | #include "../h/socket.h" | |
22 | #include "../h/ubareg.h" | |
23 | #include "../h/ubavar.h" | |
24 | #include "../h/cpu.h" | |
25 | #include "../h/mtpr.h" | |
26 | #include "../h/vmmac.h" | |
27 | #include "../net/in.h" | |
28 | #include "../net/in_systm.h" | |
29 | #include "../net/if.h" | |
30 | #include "../net/if_uba.h" | |
31 | #include "../net/ip.h" | |
32 | #include "../net/ip_var.h" | |
33 | ||
34 | /* | |
35 | * Driver information for auto-configuration stuff. | |
36 | */ | |
37 | int dmcprobe(), dmcattach(), dmcinit(), dmcoutput(), dmcreset(); | |
38 | struct uba_device *dmcinfo[NDMC]; | |
39 | u_short dmcstd[] = { 0 }; | |
40 | struct uba_driver dmcdriver = | |
41 | { dmcprobe, 0, dmcattach, 0, dmcstd, "dmc", dmcinfo }; | |
42 | ||
43 | struct dmcdevice { | |
44 | union { | |
45 | char b[8]; | |
46 | short w[4]; | |
47 | } un; | |
48 | }; | |
49 | ||
50 | #define bsel0 un.b[0] | |
51 | #define bsel1 un.b[1] | |
52 | #define bsel2 un.b[2] | |
53 | #define bsel3 un.b[3] | |
54 | #define bsel4 un.b[4] | |
55 | #define bsel5 un.b[5] | |
56 | #define bsel6 un.b[6] | |
57 | #define bsel7 un.b[7] | |
58 | #define sel0 un.w[0] | |
59 | #define sel2 un.w[1] | |
60 | #define sel4 un.w[2] | |
61 | #define sel6 un.w[3] | |
62 | ||
63 | #define DMCMTU (2048) | |
64 | ||
65 | #define RDYSCAN 16 /* loop delay for RDYI after RQI */ | |
66 | ||
67 | /* defines for bsel0 */ | |
68 | #define DMC_BACCI 0 | |
69 | #define DMC_CNTLI 1 | |
70 | #define DMC_PERR 2 | |
71 | #define DMC_BASEI 3 | |
72 | #define DMC_WRITE 0 /* transmit block */ | |
73 | #define DMC_READ 4 /* read block */ | |
74 | #define DMC_RQI 0040 /* port request bit */ | |
75 | #define DMC_IEI 0100 /* enable input interrupts */ | |
76 | #define DMC_RDYI 0200 /* port ready */ | |
77 | ||
78 | /* defines for bsel1 */ | |
79 | #define DMC_MCLR 0100 /* DMC11 Master Clear */ | |
80 | #define DMC_RUN 0200 /* clock running */ | |
81 | ||
82 | /* defines for bsel2 */ | |
83 | #define DMC_BACCO 0 | |
84 | #define DMC_CNTLO 1 | |
85 | #define DMC_OUX 0 /* transmit block */ | |
86 | #define DMC_OUR 4 /* read block */ | |
87 | #define DMC_IEO 0100 /* enable output interrupts */ | |
88 | #define DMC_RDYO 0200 /* port available */ | |
89 | ||
90 | /* defines for CNTLI mode */ | |
91 | #define DMC_HDPLX 02000 /* half duplex DDCMP operation */ | |
92 | #define DMC_SEC 04000 /* half duplex secondary station */ | |
93 | #define DMC_MAINT 00400 /* enter maintenance mode */ | |
94 | ||
95 | /* defines for BACCI/O and BASEI mode */ | |
96 | #define DMC_XMEM 0140000 /* xmem bit position */ | |
97 | #define DMC_CCOUNT 0037777 /* character count mask */ | |
98 | #define DMC_RESUME 0002000 /* resume (BASEI only) */ | |
99 | ||
100 | /* defines for CNTLO */ | |
101 | #define DMC_CNTMASK 01777 | |
102 | #define DMC_FATAL 01620 | |
103 | ||
104 | #define DMC_PF 0xff /* 8 bits of protocol type in ui_flags */ | |
105 | #define DMC_NET 0xff00 /* 8 bits of net number in ui_flags */ | |
106 | ||
107 | /* | |
108 | * DMC software status per interface. | |
109 | * | |
110 | * Each interface is referenced by a network interface structure, | |
111 | * sc_if, which the routing code uses to locate the interface. | |
112 | * This structure contains the output queue for the interface, its address, ... | |
113 | * We also have, for each interface, a UBA interface structure, which | |
114 | * contains information about the UNIBUS resources held by the interface: | |
115 | * map registers, buffered data paths, etc. Information is cached in this | |
116 | * structure for use by the if_uba.c routines in running the interface | |
117 | * efficiently. | |
118 | */ | |
119 | struct dmc_softc { | |
120 | struct ifnet sc_if; /* network-visible interface */ | |
121 | struct ifuba sc_ifuba; /* UNIBUS resources */ | |
122 | short sc_flag; /* flags */ | |
123 | short sc_oactive; /* output active */ | |
124 | int sc_ubinfo; /* UBA mapping info for base table */ | |
125 | struct clist sc_que; /* command queue */ | |
126 | } dmc_softc[NDMC]; | |
127 | ||
128 | /* flags */ | |
129 | #define DMCRUN 01 | |
130 | #define DMCBMAPPED 02 /* base table mapped */ | |
131 | ||
132 | struct dmc_base { | |
133 | short d_base[128]; /* DMC base table */ | |
134 | } dmc_base[NDMC]; | |
135 | ||
136 | #define loword(x) ((short *)&x)[0] | |
137 | #define hiword(x) ((short *)&x)[1] | |
138 | ||
139 | dmcprobe(reg) | |
140 | caddr_t reg; | |
141 | { | |
142 | register int br, cvec; | |
143 | register struct dmcdevice *addr = (struct dmcdevice *)reg; | |
144 | register int i; | |
145 | ||
146 | #ifdef lint | |
147 | br = 0; cvec = br; br = cvec; | |
148 | dmcrint(0); dmcxint(0); | |
149 | #endif | |
150 | addr->bsel1 = DMC_MCLR; | |
151 | for (i = 100000; i && (addr->bsel1 & DMC_RUN) == 0; i--) | |
152 | ; | |
153 | if ((addr->bsel1 & DMC_RUN) == 0) | |
154 | return(0); | |
155 | addr->bsel1 &= ~DMC_MCLR; | |
156 | addr->bsel0 = DMC_RQI|DMC_IEI; | |
157 | DELAY(100000); | |
158 | addr->bsel1 = DMC_MCLR; | |
159 | for (i = 100000; i && (addr->bsel1 & DMC_RUN) == 0; i--) | |
160 | ; | |
161 | return(1); | |
162 | } | |
163 | ||
164 | /* | |
165 | * Interface exists: make available by filling in network interface | |
166 | * record. System will initialize the interface when it is ready | |
167 | * to accept packets. | |
168 | */ | |
169 | dmcattach(ui) | |
170 | register struct uba_device *ui; | |
171 | { | |
172 | register struct dmc_softc *sc = &dmc_softc[ui->ui_unit]; | |
173 | ||
174 | sc->sc_if.if_unit = ui->ui_unit; | |
175 | sc->sc_if.if_name = "dmc"; | |
176 | sc->sc_if.if_mtu = DMCMTU; | |
177 | sc->sc_if.if_net = (ui->ui_flags & DMC_NET) >> 8; | |
178 | sc->sc_if.if_host[0] = 17; /* random number */ | |
179 | sc->sc_if.if_addr = | |
180 | if_makeaddr(sc->sc_if.if_net, sc->sc_if.if_host[0]); | |
181 | sc->sc_if.if_init = dmcinit; | |
182 | sc->sc_if.if_output = dmcoutput; | |
183 | sc->sc_if.if_ubareset = dmcreset; | |
184 | if_attach(&sc->sc_if); | |
185 | } | |
186 | ||
187 | /* | |
188 | * Reset of interface after UNIBUS reset. | |
189 | * If interface is on specified UBA, reset it's state. | |
190 | */ | |
191 | dmcreset(unit, uban) | |
192 | int unit, uban; | |
193 | { | |
194 | register struct uba_device *ui; | |
195 | ||
196 | if (unit >= NDMC || (ui = dmcinfo[unit]) == 0 || ui->ui_alive == 0 || | |
197 | ui->ui_ubanum != uban) | |
198 | return; | |
199 | printf(" dmc%d", unit); | |
200 | dmcinit(unit); | |
201 | } | |
202 | ||
203 | /* | |
204 | * Initialization of interface; reinitialize UNIBUS usage. | |
205 | */ | |
206 | dmcinit(unit) | |
207 | int unit; | |
208 | { | |
209 | register struct dmc_softc *sc = &dmc_softc[unit]; | |
210 | register struct uba_device *ui = dmcinfo[unit]; | |
211 | register struct dmcdevice *addr; | |
212 | int base; | |
213 | ||
214 | printd("dmcinit\n"); | |
215 | if ((sc->sc_flag&DMCBMAPPED) == 0) { | |
216 | sc->sc_ubinfo = uballoc(ui->ui_ubanum, | |
217 | (caddr_t)&dmc_base[unit], sizeof (struct dmc_base), 0); | |
218 | sc->sc_flag |= DMCBMAPPED; | |
219 | } | |
220 | if (if_ubainit(&sc->sc_ifuba, ui->ui_ubanum, 0, | |
221 | (int)btop(DMCMTU)) == 0) { | |
222 | printf("dmc%d: can't initialize\n", unit); | |
223 | return; | |
224 | } | |
225 | addr = (struct dmcdevice *)ui->ui_addr; | |
226 | addr->bsel2 |= DMC_IEO; | |
227 | base = sc->sc_ubinfo & 0x3ffff; | |
228 | printd(" base 0x%x\n", base); | |
229 | dmcload(sc, DMC_BASEI, base, (base>>2)&DMC_XMEM); | |
230 | dmcload(sc, DMC_CNTLI, 0, 0); | |
231 | base = sc->sc_ifuba.ifu_r.ifrw_info & 0x3ffff; | |
232 | dmcload(sc, DMC_READ, base, ((base>>2)&DMC_XMEM)|DMCMTU); | |
233 | printd(" first read queued, addr 0x%x\n", base); | |
234 | } | |
235 | ||
236 | /* | |
237 | * Start output on interface. Get another datagram | |
238 | * to send from the interface queue and map it to | |
239 | * the interface before starting output. | |
240 | */ | |
241 | dmcstart(dev) | |
242 | dev_t dev; | |
243 | { | |
244 | int unit = minor(dev); | |
245 | struct uba_device *ui = dmcinfo[unit]; | |
246 | register struct dmc_softc *sc = &dmc_softc[unit]; | |
247 | int addr, len; | |
248 | struct mbuf *m; | |
249 | ||
250 | printd("dmcstart\n"); | |
251 | /* | |
252 | * Dequeue a request and map it to the UNIBUS. | |
253 | * If no more requests, just return. | |
254 | */ | |
255 | IF_DEQUEUE(&sc->sc_if.if_snd, m); | |
256 | if (m == 0) | |
257 | return; | |
258 | len = if_wubaput(&sc->sc_ifuba, m); | |
259 | ||
260 | /* | |
261 | * Have request mapped to UNIBUS for transmission. | |
262 | * Purge any stale data from this BDP and start the output. | |
263 | */ | |
264 | UBAPURGE(sc->sc_ifuba.ifu_uba, sc->sc_ifuba.ifu_w.ifrw_bdp); | |
265 | addr = sc->sc_ifuba.ifu_w.ifrw_info & 0x3ffff; | |
266 | printd(" len %d, addr 0x%x, ", len, addr); | |
267 | printd("mr 0x%x\n", sc->sc_ifuba.ifu_w.ifrw_mr[0]); | |
268 | dmcload(sc, DMC_WRITE, addr, (len&DMC_CCOUNT)|((addr>>2)&DMC_XMEM)); | |
269 | sc->sc_oactive = 1; | |
270 | } | |
271 | ||
272 | /* | |
273 | * Utility routine to load the DMC device registers. | |
274 | */ | |
275 | dmcload(sc, type, w0, w1) | |
276 | register struct dmc_softc *sc; | |
277 | int type, w0, w1; | |
278 | { | |
279 | register struct dmcdevice *addr; | |
280 | register int unit, sps, n; | |
281 | ||
282 | printd("dmcload: 0x%x 0x%x 0x%x\n", type, w0, w1); | |
283 | unit = sc - dmc_softc; | |
284 | addr = (struct dmcdevice *)dmcinfo[unit]->ui_addr; | |
285 | sps = spl5(); | |
286 | if ((n = sc->sc_que.c_cc) == 0) | |
287 | addr->bsel0 = type | DMC_RQI; | |
288 | else | |
289 | putc(type | DMC_RQI, &sc->sc_que); | |
290 | putw(w0, &sc->sc_que); | |
291 | putw(w1, &sc->sc_que); | |
292 | if (n == 0) | |
293 | dmcrint(unit); | |
294 | splx(sps); | |
295 | } | |
296 | ||
297 | /* | |
298 | * DMC interface receiver interrupt. | |
299 | * Ready to accept another command, | |
300 | * pull one off the command queue. | |
301 | */ | |
302 | dmcrint(unit) | |
303 | int unit; | |
304 | { | |
305 | register struct dmc_softc *sc; | |
306 | register struct dmcdevice *addr; | |
307 | register int n; | |
308 | int w0, w1; /* DEBUG */ | |
309 | ||
310 | addr = (struct dmcdevice *)dmcinfo[unit]->ui_addr; | |
311 | sc = &dmc_softc[unit]; | |
312 | while (addr->bsel0&DMC_RDYI) { | |
313 | w0 = getw(&sc->sc_que); /* DEBUG */ | |
314 | addr->sel4 = w0; /* DEBUG */ | |
315 | w1 = getw(&sc->sc_que); /* DEBUG */ | |
316 | addr->sel6 = w1; /* DEBUG */ | |
317 | /* DEBUG | |
318 | addr->sel4 = getw(&sc->sc_que); | |
319 | addr->sel6 = getw(&sc->sc_que); | |
320 | DEBUG */ | |
321 | addr->bsel0 &= ~(DMC_IEI|DMC_RQI); | |
322 | printd(" w0 0x%x, w1 0x%x\n", w0, w1); | |
323 | while (addr->bsel0&DMC_RDYI) | |
324 | ; | |
325 | if (sc->sc_que.c_cc == 0) | |
326 | return; | |
327 | addr->bsel0 = getc(&sc->sc_que); | |
328 | n = RDYSCAN; | |
329 | while (n-- && (addr->bsel0&DMC_RDYI) == 0) | |
330 | ; | |
331 | } | |
332 | if (sc->sc_que.c_cc) | |
333 | addr->bsel0 |= DMC_IEI; | |
334 | } | |
335 | ||
336 | /* | |
337 | * DMC interface transmitter interrupt. | |
338 | * A transfer has completed, check for errors. | |
339 | * If it was a read, notify appropriate protocol. | |
340 | * If it was a write, pull the next one off the queue. | |
341 | */ | |
342 | dmcxint(unit) | |
343 | int unit; | |
344 | { | |
345 | register struct dmc_softc *sc; | |
346 | struct uba_device *ui = dmcinfo[unit]; | |
347 | struct dmcdevice *addr; | |
348 | struct mbuf *m; | |
349 | register struct ifqueue *inq; | |
350 | int arg, cmd, len; | |
351 | ||
352 | addr = (struct dmcdevice *)ui->ui_addr; | |
353 | arg = addr->sel6; | |
354 | cmd = addr->bsel2&7; | |
355 | addr->bsel2 &= ~DMC_RDYO; | |
356 | sc = &dmc_softc[unit]; | |
357 | printd("dmcxint\n"); | |
358 | switch (cmd) { | |
359 | ||
360 | case DMC_OUR: | |
361 | /* | |
362 | * A read has completed. Purge input buffered | |
363 | * data path. Pass packet to type specific | |
364 | * higher-level input routine. | |
365 | */ | |
366 | sc->sc_if.if_ipackets++; | |
367 | UBAPURGE(sc->sc_ifuba.ifu_uba, sc->sc_ifuba.ifu_r.ifrw_bdp); | |
368 | len = arg & DMC_CCOUNT; | |
369 | printd(" read done, len %d\n", len); | |
370 | switch (ui->ui_flags & DMC_PF) { | |
371 | #ifdef INET | |
372 | case PF_INET: | |
373 | setipintr(); | |
374 | inq = &ipintrq; | |
375 | break; | |
376 | #endif | |
377 | ||
378 | default: | |
379 | printf("dmc%d: unknown packet type %d\n", unit, | |
380 | ui->ui_flags & DMC_NET); | |
381 | goto setup; | |
382 | } | |
383 | m = if_rubaget(&sc->sc_ifuba, len, 0); | |
384 | if (m == 0) | |
385 | goto setup; | |
386 | IF_ENQUEUE(inq, m); | |
387 | ||
388 | setup: | |
389 | arg = sc->sc_ifuba.ifu_r.ifrw_info & 0x3ffff; | |
390 | dmcload(sc, DMC_READ, arg, ((arg >> 2) & DMC_XMEM) | DMCMTU); | |
391 | return; | |
392 | ||
393 | case DMC_OUX: | |
394 | /* | |
395 | * A write has completed, start another | |
396 | * transfer if there is more data to send. | |
397 | */ | |
398 | if (sc->sc_oactive == 0) | |
399 | return; /* SHOULD IT BE A FATAL ERROR? */ | |
400 | printd(" write done\n"); | |
401 | sc->sc_if.if_opackets++; | |
402 | sc->sc_oactive = 0; | |
403 | if (sc->sc_ifuba.ifu_xtofree) { | |
404 | m_freem(sc->sc_ifuba.ifu_xtofree); | |
405 | sc->sc_ifuba.ifu_xtofree = 0; | |
406 | } | |
407 | if (sc->sc_if.if_snd.ifq_head == 0) | |
408 | return; | |
409 | dmcstart(unit); | |
410 | return; | |
411 | ||
412 | case DMC_CNTLO: | |
413 | arg &= DMC_CNTMASK; | |
414 | if (arg&DMC_FATAL) { | |
415 | addr->bsel1 = DMC_MCLR; | |
416 | sc->sc_flag &= ~DMCRUN; | |
417 | /*** DO SOMETHING TO RESTART DEVICE ***/ | |
418 | printf("DMC FATAL ERROR 0%o\n", arg); | |
419 | } else { | |
420 | /* ACCUMULATE STATISTICS */ | |
421 | printf("DMC SOFT ERROR 0%o\n", arg); | |
422 | } | |
423 | return; | |
424 | ||
425 | default: | |
426 | printf("dmc%d: bad control %o\n", unit, cmd); | |
427 | } | |
428 | } | |
429 | ||
430 | /* | |
431 | * DMC output routine. | |
432 | * Just send the data, header was supplied by | |
433 | * upper level protocol routines. | |
434 | */ | |
435 | dmcoutput(ifp, m, pf) | |
436 | register struct ifnet *ifp; | |
437 | register struct mbuf *m; | |
438 | int pf; | |
439 | { | |
440 | struct uba_device *ui = dmcinfo[ifp->if_unit]; | |
441 | int s; | |
442 | ||
443 | printd("dmcoutput\n"); | |
444 | if (pf != (ui->ui_flags & DMC_PF)) { | |
445 | printf("dmc%d: protocol %d not supported\n", ifp->if_unit, pf); | |
446 | m_freem(m); | |
447 | return (0); | |
448 | } | |
449 | s = splimp(); | |
450 | IF_ENQUEUE(&ifp->if_snd, m); | |
451 | if (dmc_softc[ifp->if_unit].sc_oactive == 0) | |
452 | dmcstart(ifp->if_unit); | |
453 | splx(s); | |
454 | return (1); | |
455 | } |