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1 | /* |
2 | * Copyright (c) 1992 The Regents of the University of California. | |
3 | * All rights reserved. | |
4 | * | |
5 | * This software was developed by the Computer Systems Engineering group | |
6 | * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and | |
7 | * contributed to Berkeley. | |
8 | * | |
b480239a KB |
9 | * All advertising materials mentioning features or use of this software |
10 | * must display the following acknowledgement: | |
11 | * This product includes software developed by the University of | |
12 | * California, Lawrence Berkeley Laboratories. | |
13 | * | |
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14 | * %sccs.include.redist.c% |
15 | * | |
b480239a | 16 | * @(#)pmap.h 7.2 (Berkeley) %G% |
e6394f29 CT |
17 | * |
18 | * from: $Header: pmap.h,v 1.9 92/06/17 06:10:22 torek Exp $ | |
19 | */ | |
20 | ||
21 | #ifndef _SPARC_PMAP_H_ | |
22 | #define _SPARC_PMAP_H_ | |
23 | ||
24 | #include "machine/pte.h" | |
25 | ||
26 | /* | |
27 | * Pmap structure. | |
28 | * | |
29 | * The pmap structure really comes in two variants, one---a single | |
30 | * instance---for kernel virtual memory and the other---up to nproc | |
31 | * instances---for user virtual memory. Unfortunately, we have to mash | |
32 | * both into the same structure. Fortunately, they are almost the same. | |
33 | * | |
34 | * The kernel begins at 0xf8000000 and runs to 0xffffffff (although | |
35 | * some of this is not actually used). Kernel space, including DVMA | |
36 | * space (for now?), is mapped identically into all user contexts. | |
37 | * There is no point in duplicating this mapping in each user process | |
38 | * so they do not appear in the user structures. | |
39 | * | |
40 | * User space begins at 0x00000000 and runs through 0x1fffffff, | |
41 | * then has a `hole', then resumes at 0xe0000000 and runs until it | |
42 | * hits the kernel space at 0xf8000000. This can be mapped | |
43 | * contiguously by ignorning the top two bits and pretending the | |
44 | * space goes from 0 to 37ffffff. Typically the lower range is | |
45 | * used for text+data and the upper for stack, but the code here | |
46 | * makes no such distinction. | |
47 | * | |
48 | * Since each virtual segment covers 256 kbytes, the user space | |
49 | * requires 3584 segments, while the kernel (including DVMA) requires | |
50 | * only 512 segments. | |
51 | * | |
52 | * The segment map entry for virtual segment vseg is offset in | |
53 | * pmap->pm_rsegmap by 0 if pmap is not the kernel pmap, or by | |
54 | * NUSEG if it is. We keep a pointer called pmap->pm_segmap | |
55 | * pre-offset by this value. pmap->pm_segmap thus contains the | |
56 | * values to be loaded into the user portion of the hardware segment | |
57 | * map so as to reach the proper PMEGs within the MMU. The kernel | |
58 | * mappings are `set early' and are always valid in every context | |
59 | * (every change is always propagated immediately). | |
60 | * | |
61 | * The PMEGs within the MMU are loaded `on demand'; when a PMEG is | |
62 | * taken away from context `c', the pmap for context c has its | |
63 | * corresponding pm_segmap[vseg] entry marked invalid (the MMU segment | |
64 | * map entry is also made invalid at the same time). Thus | |
65 | * pm_segmap[vseg] is the `invalid pmeg' number (127 or 511) whenever | |
66 | * the corresponding PTEs are not actually in the MMU. On the other | |
67 | * hand, pm_pte[vseg] is NULL only if no pages in that virtual segment | |
68 | * are in core; otherwise it points to a copy of the 32 or 64 PTEs that | |
69 | * must be loaded in the MMU in order to reach those pages. | |
70 | * pm_npte[vseg] counts the number of valid pages in each vseg. | |
71 | * | |
72 | * XXX performance: faster to count valid bits? | |
73 | * | |
74 | * The kernel pmap cannot malloc() PTEs since malloc() will sometimes | |
75 | * allocate a new virtual segment. Since kernel mappings are never | |
76 | * `stolen' out of the the MMU, we just keep all its PTEs there, and | |
77 | * have no software copies. Its mmu entries are nonetheless kept on lists | |
78 | * so that the code that fiddles with mmu lists has something to fiddle. | |
79 | */ | |
80 | #define NKSEG ((int)((-(unsigned)KERNBASE) / NBPSG)) /* i.e., 512 */ | |
81 | #define NUSEG (4096 - NKSEG) /* i.e., 3584 */ | |
82 | ||
83 | /* data appearing in both user and kernel pmaps */ | |
84 | struct pmap_common { | |
85 | union ctxinfo *pmc_ctx; /* current context, if any */ | |
86 | int pmc_ctxnum; /* current context's number */ | |
87 | #if NCPUS > 1 | |
88 | simple_lock_data_t pmc_lock; /* spinlock */ | |
89 | #endif | |
90 | int pmc_refcount; /* just what it says */ | |
91 | struct mmuentry *pmc_mmuforw; /* pmap pmeg chain */ | |
92 | struct mmuentry **pmc_mmuback; /* (two way street) */ | |
93 | pmeg_t *pmc_segmap; /* points to pm_rsegmap per above */ | |
94 | u_char *pmc_npte; /* points to pm_rnpte */ | |
95 | int **pmc_pte; /* points to pm_rpte */ | |
96 | }; | |
97 | ||
98 | /* data appearing only in user pmaps */ | |
99 | struct pmap { | |
100 | struct pmap_common pmc; | |
101 | pmeg_t pm_rsegmap[NUSEG]; /* segment map */ | |
102 | u_char pm_rnpte[NUSEG]; /* number of valid PTEs per seg */ | |
103 | int *pm_rpte[NUSEG]; /* points to PTEs for valid segments */ | |
104 | }; | |
105 | ||
106 | /* data appearing only in the kernel pmap */ | |
107 | struct kpmap { | |
108 | struct pmap_common pmc; | |
109 | pmeg_t pm_rsegmap[NKSEG]; /* segment map */ | |
110 | u_char pm_rnpte[NKSEG]; /* number of valid PTEs per kseg */ | |
111 | int *pm_rpte[NKSEG]; /* always NULL */ | |
112 | }; | |
113 | ||
114 | #define pm_ctx pmc.pmc_ctx | |
115 | #define pm_ctxnum pmc.pmc_ctxnum | |
116 | #define pm_lock pmc.pmc_lock | |
117 | #define pm_refcount pmc.pmc_refcount | |
118 | #define pm_mmuforw pmc.pmc_mmuforw | |
119 | #define pm_mmuback pmc.pmc_mmuback | |
120 | #define pm_segmap pmc.pmc_segmap | |
121 | #define pm_npte pmc.pmc_npte | |
122 | #define pm_pte pmc.pmc_pte | |
123 | ||
124 | #ifdef KERNEL | |
125 | ||
126 | typedef struct pmap *pmap_t; | |
127 | #define PMAP_NULL ((pmap_t)0) | |
128 | ||
129 | extern struct kpmap kernel_pmap_store; | |
130 | #define kernel_pmap ((struct pmap *)(&kernel_pmap_store)) | |
131 | ||
132 | #define PMAP_ACTIVATE(pmap, pcb, iscurproc) | |
133 | #define PMAP_DEACTIVATE(pmap, pcb) | |
134 | ||
135 | /* | |
136 | * Since PTEs also contain type bits, we have to have some way | |
137 | * to tell pmap_enter `this is an IO page' or `this is not to | |
138 | * be cached'. Since physical addresses are always aligned, we | |
139 | * can do this with the low order bits. | |
140 | * | |
141 | * The ordering below is important: PMAP_PGTYPE << PG_TNC must give | |
142 | * exactly the PG_NC and PG_TYPE bits. | |
143 | */ | |
144 | #define PMAP_OBIO 1 /* tells pmap_enter to use PG_OBIO */ | |
145 | #define PMAP_VME16 2 /* etc */ | |
146 | #define PMAP_VME32 3 /* etc */ | |
147 | #define PMAP_NC 4 /* tells pmap_enter to set PG_NC */ | |
148 | #define PMAP_TNC 7 /* mask to get PG_TYPE & PG_NC */ | |
149 | ||
150 | #endif KERNEL | |
151 | ||
152 | #endif /* _SPARC_PMAP_H_ */ |