[unix-history] / sys / i386 / isa / isa.h

/*-
 * Copyright (c) 1990 The Regents of the University of California.
 * All rights reserved.
 *
 * This code is derived from software contributed to Berkeley by
 * William Jolitz.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *	This product includes software developed by the University of
 *	California, Berkeley and its contributors.
 * 4. Neither the name of the University nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 *	from: @(#)isa.h	5.7 (Berkeley) 5/9/91
 *	$Id$
 */

/*
 * ISA Bus conventions
 */

#ifndef LOCORE
#include <sys/cdefs.h>

unsigned char rtcin __P((int));
extern unsigned int atdevbase;	/* offset in virtual memory of ISA io mem */
void sysbeep __P((int, int));
unsigned kbd_8042cmd __P((int));
struct isa_device;
int isa_irq_pending __P((struct isa_device *dvp));
#endif


/*
 * Input / Output Port Assignments
 */

#ifndef IO_BEGIN
#define	IO_ISABEGIN	0x000		/* 0x000 - Beginning of I/O Registers */

		/* CPU Board */
#define IO_DMA1		0x000		/* 8237A DMA Controller #1 */
#define IO_ICU1		0x020		/* 8259A Interrupt Controller #1 */
#define IO_TIMER1	0x040		/* 8252 Timer #1 */
#define IO_TIMER2	0x048		/* 8252 Timer #2 */
#define IO_KBD		0x060		/* 8042 Keyboard */
#define IO_RTC		0x070		/* RTC */
#define IO_NMI		IO_RTC		/* NMI Control */
#define IO_DMAPG	0x080		/* DMA Page Registers */
#define IO_ICU2		0x0A0		/* 8259A Interrupt Controller #2 */
#define IO_DMA2		0x0C0		/* 8237A DMA Controller #2 */
#define IO_NPX		0x0F0		/* Numeric Coprocessor */

		/* Cards */
					/* 0x100 - 0x16F Open */

#define IO_WD2		0x170		/* Secondary Fixed Disk Controller */

					/* 0x178 - 0x1EF Open */

#define IO_WD1		0x1f0		/* Primary Fixed Disk Controller */
#define IO_GAME		0x200		/* Game Controller */

					/* 0x208 - 0x277 Open */

#define IO_LPT2		0x278		/* Parallel Port #2 */

					/* 0x280 - 0x2E7 Open */

#define	IO_COM4		0x2e8		/* COM4 i/o address */

					/* 0x2F0 - 0x2F7 Open */

#define IO_COM2		0x2f8		/* COM2 i/o address */
					/* 0x300 - 0x32F Open */

#define	IO_BT0		0x330		/* bustek 742a default addr. */
#define	IO_AHA0		0x330		/* adaptec 1542 default addr. */
#define	IO_UHA0		0x330		/* ultrastore 14f default addr. */
#define	IO_BT1		0x334		/* bustek 742a default addr. */
#define	IO_AHA1		0x334		/* adaptec 1542 default addr. */
					/* 0x338 - 0x36F Open */

#define IO_FD2		0x370		/* secondary base i/o address */
#define IO_LPT1		0x378		/* Parallel Port #1 */

					/* 0x380 - 0x3AF Open */

#define IO_MDA		0x3B0		/* Monochome Adapter */
#define IO_LPT3		0x3BC		/* Monochome Adapter Printer Port */
#define IO_VGA		0x3C0		/* E/VGA Ports */
#define IO_CGA		0x3D0		/* CGA Ports */

					/* 0x3E0 - 0x3E7 Open */

#define	IO_COM3		0x3e8		/* COM3 i/o address */
#define IO_FD1		0x3f0		/* primary base i/o address */
#define IO_COM1		0x3f8		/* COM1 i/o address */

#define	IO_ISAEND	0x3FF		/* - 0x3FF End of I/O Registers */
#endif	IO_ISABEGIN

/*
 * Input / Output Port Sizes - these are from several sources, and tend
 * to be the larger of what was found, ie COM ports can be 4, but some
 * boards do not fully decode the address, thus 8 ports are used.
 */

#ifndef	IO_ISASIZES
#define	IO_ISASIZES

#define	IO_COMSIZE	8		/* 8250, 16X50 com controllers (4?) */
#define	IO_CGASIZE	16		/* CGA controllers */
#define	IO_DMASIZE	16		/* 8237 DMA controllers */
#define	IO_DPGSIZE	32		/* 74LS612 DMA page reisters */
#define	IO_FDCSIZE	8		/* Nec765 floppy controllers */
#define	IO_WDCSIZE	8		/* WD compatible disk controllers */
#define	IO_GAMSIZE	16		/* AT compatible game controllers */
#define	IO_ICUSIZE	16		/* 8259A interrupt controllers */
#define	IO_KBDSIZE	16		/* 8042 Keyboard controllers */
#define	IO_LPTSIZE	8		/* LPT controllers, some use only 4 */
#define	IO_MDASIZE	16		/* Monochrome display controllers */
#define	IO_RTCSIZE	16		/* CMOS real time clock, NMI control */
#define	IO_TMRSIZE	16		/* 8253 programmable timers */
#define	IO_NPXSIZE	16		/* 80387/80487 NPX registers */
#define	IO_VGASIZE	16		/* VGA controllers */

#endif	/* IO_ISASIZES */

/*
 * Input / Output Memory Physical Addresses
 */

#ifndef	IOM_BEGIN
#define	IOM_BEGIN	0x0a0000		/* Start of I/O Memory "hole" */
#define	IOM_END		0x100000		/* End of I/O Memory "hole" */
#define	IOM_SIZE	(IOM_END - IOM_BEGIN)
#endif	IOM_BEGIN

/*
 * RAM Physical Address Space (ignoring the above mentioned "hole")
 */

#ifndef	RAM_BEGIN
#define	RAM_BEGIN	0x0000000	/* Start of RAM Memory */
#define	RAM_END		0x1000000	/* End of RAM Memory */
#define	RAM_SIZE	(RAM_END - RAM_BEGIN)
#endif	RAM_BEGIN

/*
 * Oddball Physical Memory Addresses
 */
#ifndef	COMPAQ_RAMRELOC
#define	COMPAQ_RAMRELOC	0x80c00000	/* Compaq RAM relocation/diag */
#define	COMPAQ_RAMSETUP	0x80c00002	/* Compaq RAM setup */
#define	WEITEK_FPU	0xC0000000	/* WTL 2167 */
#define	CYRIX_EMC	0xC0000000	/* Cyrix EMC */
#endif	COMPAQ_RAMRELOC
Commit	Line	Data
15637ed4 RG	1	/*-
	2	* Copyright (c) 1990 The Regents of the University of California.
	3	* All rights reserved.
	4	*
	5	* This code is derived from software contributed to Berkeley by
	6	* William Jolitz.
	7	*
	8	* Redistribution and use in source and binary forms, with or without
	9	* modification, are permitted provided that the following conditions
	10	* are met:
	11	* 1. Redistributions of source code must retain the above copyright
	12	* notice, this list of conditions and the following disclaimer.
	13	* 2. Redistributions in binary form must reproduce the above copyright
	14	* notice, this list of conditions and the following disclaimer in the
	15	* documentation and/or other materials provided with the distribution.
	16	* 3. All advertising materials mentioning features or use of this software
	17	* must display the following acknowledgement:
	18	* This product includes software developed by the University of
	19	* California, Berkeley and its contributors.
	20	* 4. Neither the name of the University nor the names of its contributors
	21	* may be used to endorse or promote products derived from this software
	22	* without specific prior written permission.
	23	*
	24	* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
	25	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
	27	* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
	30	* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
	31	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
	32	* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
	33	* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
	34	* SUCH DAMAGE.
	35	*
78ed81a3	36	* from: @(#)isa.h 5.7 (Berkeley) 5/9/91
78ed81a3	37	* $Id$
15637ed4 RG	38	*/
	39
	40	/*
	41	* ISA Bus conventions
	42	*/
	43
	44	#ifndef LOCORE
	45	#include <sys/cdefs.h>
	46
	47	unsigned char rtcin __P((int));
	48	extern unsigned int atdevbase; /* offset in virtual memory of ISA io mem */
	49	void sysbeep __P((int, int));
	50	unsigned kbd_8042cmd __P((int));
	51	struct isa_device;
	52	int isa_irq_pending __P((struct isa_device *dvp));
	53	#endif
	54
	55
	56	/*
	57	* Input / Output Port Assignments
	58	*/
	59
	60	#ifndef IO_BEGIN
	61	#define IO_ISABEGIN 0x000 /* 0x000 - Beginning of I/O Registers */
	62
	63	/* CPU Board */
	64	#define IO_DMA1 0x000 /* 8237A DMA Controller #1 */
	65	#define IO_ICU1 0x020 /* 8259A Interrupt Controller #1 */
	66	#define IO_TIMER1 0x040 /* 8252 Timer #1 */
	67	#define IO_TIMER2 0x048 /* 8252 Timer #2 */
	68	#define IO_KBD 0x060 /* 8042 Keyboard */
	69	#define IO_RTC 0x070 /* RTC */
	70	#define IO_NMI IO_RTC /* NMI Control */
	71	#define IO_DMAPG 0x080 /* DMA Page Registers */
	72	#define IO_ICU2 0x0A0 /* 8259A Interrupt Controller #2 */
	73	#define IO_DMA2 0x0C0 /* 8237A DMA Controller #2 */
	74	#define IO_NPX 0x0F0 /* Numeric Coprocessor */
	75
	76	/* Cards */
	77	/* 0x100 - 0x16F Open */
	78
	79	#define IO_WD2 0x170 /* Secondary Fixed Disk Controller */
	80
	81	/* 0x178 - 0x1EF Open */
	82
	83	#define IO_WD1 0x1f0 /* Primary Fixed Disk Controller */
	84	#define IO_GAME 0x200 /* Game Controller */
	85
	86	/* 0x208 - 0x277 Open */
	87
	88	#define IO_LPT2 0x278 /* Parallel Port #2 */
	89
	90	/* 0x280 - 0x2E7 Open */
	91
	92	#define IO_COM4 0x2e8 /* COM4 i/o address */
	93
	94	/* 0x2F0 - 0x2F7 Open */
	95
	96	#define IO_COM2 0x2f8 /* COM2 i/o address */
	97	/* 0x300 - 0x32F Open */
	98
	99	#define IO_BT0 0x330 /* bustek 742a default addr. */
	100	#define IO_AHA0 0x330 /* adaptec 1542 default addr. */
	101	#define IO_UHA0 0x330 /* ultrastore 14f default addr. */
102	#define IO_BT1 0x334 /* bustek 742a default addr. */
103	#define IO_AHA1 0x334 /* adaptec 1542 default addr. */
104	/* 0x338 - 0x36F Open */
105
106	#define IO_FD2 0x370 /* secondary base i/o address */
107	#define IO_LPT1 0x378 /* Parallel Port #1 */
108
109	/* 0x380 - 0x3AF Open */
110
111	#define IO_MDA 0x3B0 /* Monochome Adapter */
112	#define IO_LPT3 0x3BC /* Monochome Adapter Printer Port */
113	#define IO_VGA 0x3C0 /* E/VGA Ports */
114	#define IO_CGA 0x3D0 /* CGA Ports */
115
116	/* 0x3E0 - 0x3E7 Open */
117
118	#define IO_COM3 0x3e8 /* COM3 i/o address */
119	#define IO_FD1 0x3f0 /* primary base i/o address */
120	#define IO_COM1 0x3f8 /* COM1 i/o address */
121
122	#define IO_ISAEND 0x3FF /* - 0x3FF End of I/O Registers */
123	#endif IO_ISABEGIN
124
125	/*
126	* Input / Output Port Sizes - these are from several sources, and tend
127	* to be the larger of what was found, ie COM ports can be 4, but some
128	* boards do not fully decode the address, thus 8 ports are used.
129	*/
130
131	#ifndef IO_ISASIZES
132	#define IO_ISASIZES
133
134	#define IO_COMSIZE 8 /* 8250, 16X50 com controllers (4?) */
135	#define IO_CGASIZE 16 /* CGA controllers */
136	#define IO_DMASIZE 16 /* 8237 DMA controllers */
137	#define IO_DPGSIZE 32 /* 74LS612 DMA page reisters */
138	#define IO_FDCSIZE 8 /* Nec765 floppy controllers */
139	#define IO_WDCSIZE 8 /* WD compatible disk controllers */
140	#define IO_GAMSIZE 16 /* AT compatible game controllers */
141	#define IO_ICUSIZE 16 /* 8259A interrupt controllers */
142	#define IO_KBDSIZE 16 /* 8042 Keyboard controllers */
143	#define IO_LPTSIZE 8 /* LPT controllers, some use only 4 */
144	#define IO_MDASIZE 16 /* Monochrome display controllers */
145	#define IO_RTCSIZE 16 /* CMOS real time clock, NMI control */
146	#define IO_TMRSIZE 16 /* 8253 programmable timers */
147	#define IO_NPXSIZE 16 /* 80387/80487 NPX registers */
148	#define IO_VGASIZE 16 /* VGA controllers */
149
150	#endif /* IO_ISASIZES */
151
152	/*
153	* Input / Output Memory Physical Addresses
154	*/
155
156	#ifndef IOM_BEGIN
157	#define IOM_BEGIN 0x0a0000 /* Start of I/O Memory "hole" */
158	#define IOM_END 0x100000 /* End of I/O Memory "hole" */
159	#define IOM_SIZE (IOM_END - IOM_BEGIN)
160	#endif IOM_BEGIN
161
162	/*
163	* RAM Physical Address Space (ignoring the above mentioned "hole")
164	*/
165
166	#ifndef RAM_BEGIN
167	#define RAM_BEGIN 0x0000000 /* Start of RAM Memory */
168	#define RAM_END 0x1000000 /* End of RAM Memory */
169	#define RAM_SIZE (RAM_END - RAM_BEGIN)
170	#endif RAM_BEGIN
171
172	/*
173	* Oddball Physical Memory Addresses
174	*/
175	#ifndef COMPAQ_RAMRELOC
176	#define COMPAQ_RAMRELOC 0x80c00000 /* Compaq RAM relocation/diag */
177	#define COMPAQ_RAMSETUP 0x80c00002 /* Compaq RAM setup */
178	#define WEITEK_FPU 0xC0000000 /* WTL 2167 */
179	#define CYRIX_EMC 0xC0000000 /* Cyrix EMC */
180	#endif COMPAQ_RAMRELOC