[unix-history] / sys / i386 / isa / if_wereg.h

/*-
 * Copyright (c) 1991 The Regents of the University of California.
 * All rights reserved.
 *
 * This code is derived from software contributed to Berkeley by
 * Tim L. Tucker.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *	This product includes software developed by the University of
 *	California, Berkeley and its contributors.
 * 4. Neither the name of the University nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 *	@(#)if_wereg.h	7.1 (Berkeley) 5/9/91
 *
 * PATCHES MAGIC                LEVEL   PATCH THAT GOT US HERE
 * --------------------         -----   ----------------------
 * CURRENT PATCH LEVEL:         1       00100
 * --------------------         -----   ----------------------
 *
 * 20 Sep 92	Barry Lustig		WD8013 16 bit mode -- enable
 *						with "options WD8013".
 */

/*
 * Western Digital 8003 ethernet/starlan adapter 
 */
 
/*
 * Memory Select Register (MSR)
 */
union we_mem_sel {
    struct memory_decode {
        u_char msd_addr:6,		/* Memory decode bits		*/
	       msd_enable:1,		/* Memory (RAM) enable		*/
	       msd_reset:1;		/* Software reset 		*/
    } msd_decode;
#define ms_addr		msd_decode.msd_addr
#define ms_enable	msd_decode.msd_enable
#define ms_reset	msd_decode.msd_reset
    u_char ms_byte;			/* entire byte			*/
};

/* 20 Sep 92*/
/*
 * LA Address Register (LAAR)
 */
union we_laar {
	struct lan_addr_reg {
		u_char addr_l19_b:1,	/* Address Line 19 for enabling    */
					/* 16 bit NIC access to shared RAM */
		unused_b:5,		/* unused (or unknown) bits        */
		lan_16_en_b:1,		/* Enables 16bit shrd RAM for LAN  */
		mem_16_en_b:1;		/* Enables 16bit shrd RAM for host */
	} laar_decode;
#define addr_l19	laar_decode.addr_l19_b
#define lan_16_en	laar_decode.lan_16_en_b
#define mem_16_en	laar_decode.mem_16_en_b
	u_char laar_byte;		/* entire byte                  */
};

/*
 * receive ring discriptor
 *
 * The National Semiconductor DS8390 Network interface controller uses
 * the following receive ring headers.  The way this works is that the
 * memory on the interface card is chopped up into 256 bytes blocks.
 * A contiguous portion of those blocks are marked for receive packets
 * by setting start and end block #'s in the NIC.  For each packet that
 * is put into the receive ring, one of these headers (4 bytes each) is
 * tacked onto the front.
 */
struct we_ring	{
	struct wer_status {		/* received packet status	*/
	    u_char rs_prx:1,		    /* packet received intack	*/
		   rs_crc:1,		    /* crc error		*/
	           rs_fae:1,		    /* frame alignment error	*/
	           rs_fo:1,		    /* fifo overrun		*/
	           rs_mpa:1,		    /* packet received intack	*/
	           rs_phy:1,		    /* packet received intack	*/
	           rs_dis:1,		    /* packet received intack	*/
	           rs_dfr:1;		    /* packet received intack	*/
	} we_rcv_status;		/* received packet status	*/
	u_char	we_next_packet;		/* pointer to next packet	*/
	u_short	we_count;		/* bytes in packet (length + 4)	*/
};

/*
 * Command word definition
 */
union we_command {
    struct command_decode {
	u_char csd_stp:1,		/* STOP!			*/
	       csd_sta:1,		/* START!			*/
               csd_txp:1,		/* Transmit packet		*/
               csd_rd:3,		/* Remote DMA command		*/
               csd_ps:2;		/* Page select			*/
    } csd_decode;
#define cs_stp		csd_decode.csd_stp
#define cs_sta		csd_decode.csd_sta
#define cs_txp		csd_decode.csd_txp
#define cs_rd		csd_decode.csd_rd
#define cs_ps		csd_decode.csd_ps
    u_char cs_byte;			/* entire command byte		*/
};

/*
 * Interrupt status definition
 */
union we_interrupt {
    struct interrupt_decode {
	u_char isd_prx:1,		/* Packet received		*/
	       isd_ptx:1,		/* Packet transmitted		*/
               isd_rxe:1,		/* Receive error		*/
               isd_txe:1,		/* Transmit error		*/
               isd_ovw:1,		/* Overwrite warning		*/
               isd_cnt:1,		/* Counter overflow		*/
               isd_rdc:1,		/* Remote DMA complete		*/
               isd_rst:1;		/* Reset status			*/
    } isd_decode;
#define is_prx		isd_decode.isd_prx
#define is_ptx		isd_decode.isd_ptx
#define is_rxe		isd_decode.isd_rxe
#define is_txe		isd_decode.isd_txe
#define is_ovw		isd_decode.isd_ovw
#define is_cnt		isd_decode.isd_cnt
#define is_rdc		isd_decode.isd_rdc
#define is_rst		isd_decode.isd_rst
    u_char is_byte;			/* entire interrupt byte	*/
};
 
/*
 * Status word definition (transmit)
 */
union wet_status {
    struct tstat {
	u_char tsd_ptx:1,		/* Packet transmitted intack	*/
	       tsd_dfr:1,		/* Non deferred transmition	*/
               tsd_col:1,		/* Transmit Collided		*/
               tsd_abt:1,		/* Transmit Aborted (coll > 16)	*/
               tsd_crs:1,		/* Carrier Sense Lost		*/
               tsd_fu:1,		/* Fifo Underrun		*/
               tsd_chd:1,		/* CD Heartbeat			*/
               tsd_owc:1;		/* Out of Window Collision	*/
    } tsd_decode;
#define ts_ptx		tsd_decode.tsd_ptx
#define ts_dfr		tsd_decode.tsd_dfr
#define ts_col		tsd_decode.tsd_col
#define ts_abt		tsd_decode.tsd_abt
#define ts_crs		tsd_decode.tsd_crs
#define ts_fu		tsd_decode.tsd_fu
#define ts_chd		tsd_decode.tsd_chd
#define ts_owc		tsd_decode.tsd_owc
    u_char ts_byte;			/* entire transmit byte		*/
};

/*
 * General constant definitions
 */

/* Bits in the REGE register */
#define	WD_MICROCHANEL	0x80	/* Microchannel bus (vs. isa) */
#define	WD_LARGERAM	0x40    /* Large RAM */
#define	WD_SOFTCONFIG   0x20	/* Soft config */
#define	WD_REVMASK	0x1e	/* Revision mask */
#define WD_ETHERNET	0x01	/* Ethernet (vs. Starlan) */

#define WD_CHECKSUM	0xFF		/* Checksum byte		*/
#define WD_PAGE_SIZE	256		/* Size of RAM pages in bytes	*/
#define WD_TXBUF_SIZE	6		/* Size of TX buffer in pages	*/
#define WD_ROM_OFFSET	8		/* i/o base offset to ROM	*/
#define WD_IO_PORTS	32		/* # of i/o addresses used	*/
#define WD_NIC_OFFSET	16		/* i/o base offset to NIC	*/

/*
 * Page register offset values
 */
#define WD_P0_COMMAND	0x00		/* Command register 		*/
#define WD_P0_PSTART	0x01		/* Page Start register		*/
#define WD_P0_PSTOP	0x02		/* Page Stop register		*/
#define WD_P0_BNRY	0x03		/* Boundary Pointer		*/
#define WD_P0_TSR	0x04		/* Transmit Status (read-only)	*/
#define WD_P0_TPSR	WD_P0_TSR	/* Transmit Page (write-only)	*/
#define WD_P0_TBCR0	0x05		/* Transmit Byte count, low  WO	*/
#define WD_P0_TBCR1	0x06		/* Transmit Byte count, high WO	*/
#define WD_P0_ISR	0x07		/* Interrupt status register	*/
#define WD_P0_RBCR0	0x0A		/* Remote byte count low     WO	*/
#define WD_P0_RBCR1	0x0B		/* Remote byte count high    WO	*/
#define WD_P0_RSR	0x0C		/* Receive status            RO	*/
#define WD_P0_RCR	WD_P0_RSR	/* Receive configuration     WO */
#define WD_P0_TCR	0x0D		/* Transmit configuration    WO */
#define WD_P0_DCR	0x0E		/* Data configuration	     WO */
#define WD_P0_IMR	0x0F		/* Interrupt masks	     WO	*/
#define WD_P1_COMMAND	0x00		/* Command register 		*/
#define WD_P1_PAR0	0x01		/* Physical address register 0	*/
#define WD_P1_PAR1	0x02		/* Physical address register 1	*/
#define WD_P1_PAR2	0x03		/* Physical address register 2	*/
#define WD_P1_PAR3	0x04		/* Physical address register 3	*/
#define WD_P1_PAR4	0x05		/* Physical address register 4	*/
#define WD_P1_PAR5	0x06		/* Physical address register 5	*/
#define WD_P1_CURR	0x07		/* Current page (receive unit)  */
#define WD_P1_MAR0	0x08		/* Multicast address register 0	*/

/*
 * Configuration constants (receive unit)
 */
#define WD_R_SEP	0x01		/* Save error packets		*/
#define WD_R_AR		0x02		/* Accept Runt packets		*/
#define WD_R_AB		0x04		/* Accept Broadcast packets	*/
#define WD_R_AM		0x08		/* Accept Multicast packets	*/
#define WD_R_PRO	0x10		/* Promiscuous physical		*/
#define WD_R_MON	0x20		/* Monitor mode			*/
#define WD_R_RES1	0x40		/* reserved...			*/
#define WD_R_RES2	0x80		/* reserved...			*/
#define	WD_R_CONFIG	(WD_R_AB)

/*
 * Configuration constants (transmit unit)
 */
#define WD_T_CRC	0x01		/* Inhibit CRC			*/
#define WD_T_LB0	0x02		/* Encoded Loopback Control	*/
#define WD_T_LB1	0x04		/* Encoded Loopback Control	*/
#define WD_T_ATD	0x08		/* Auto Transmit Disable	*/
#define WD_T_OFST	0x10		/* Collision Offset Enable	*/
#define WD_T_RES1	0x20		/* reserved...			*/
#define WD_T_RES2	0x40		/* reserved...			*/
#define WD_T_RES3	0x80		/* reserved...			*/
#define	WD_T_CONFIG	(0)

/*
 * Configuration constants (data unit)
 */
#define WD_D_WTS	0x01		/* Word Transfer Select		*/
#define WD_D_BOS	0x02		/* Byte Order Select		*/
#define WD_D_LAS	0x04		/* Long Address Select		*/
#define WD_D_BMS	0x08		/* Burst Mode Select		*/
#define WD_D_AR		0x10		/* Autoinitialize Remote	*/
#define WD_D_FT0	0x20		/* Fifo Threshold Select	*/
#define WD_D_FT1	0x40		/* Fifo Threshold Select	*/
#define WD_D_RES	0x80		/* reserved...			*/
#define	WD_D_CONFIG	(WD_D_FT1|WD_D_BMS)
#define WD_D_CONFIG16	(WD_D_FT1|WD_D_BMS|WD_D_LAS|WD_D_WTS)	/* 20 Sep 92*/

/*
 * Configuration constants (interrupt mask register)
 */
#define WD_I_PRXE	0x01		/* Packet received enable	*/
#define WD_I_PTXE	0x02		/* Packet transmitted enable	*/
#define WD_I_RXEE	0x04		/* Receive error enable		*/
#define WD_I_TXEE	0x08		/* Transmit error enable	*/
#define WD_I_OVWE	0x10		/* Overwrite warning enable	*/
#define WD_I_CNTE	0x20		/* Counter overflow enable	*/
#define WD_I_RDCE	0x40		/* Dma complete enable		*/
#define WD_I_RES	0x80		/* reserved...			*/
#define WD_I_CONFIG     (WD_I_PRXE|WD_I_PTXE|WD_I_RXEE|WD_I_TXEE)
Commit	Line	Data
15637ed4 RG	1	/*-
	2	* Copyright (c) 1991 The Regents of the University of California.
	3	* All rights reserved.
	4	*
	5	* This code is derived from software contributed to Berkeley by
	6	* Tim L. Tucker.
	7	*
	8	* Redistribution and use in source and binary forms, with or without
	9	* modification, are permitted provided that the following conditions
	10	* are met:
	11	* 1. Redistributions of source code must retain the above copyright
	12	* notice, this list of conditions and the following disclaimer.
	13	* 2. Redistributions in binary form must reproduce the above copyright
	14	* notice, this list of conditions and the following disclaimer in the
	15	* documentation and/or other materials provided with the distribution.
	16	* 3. All advertising materials mentioning features or use of this software
	17	* must display the following acknowledgement:
	18	* This product includes software developed by the University of
	19	* California, Berkeley and its contributors.
	20	* 4. Neither the name of the University nor the names of its contributors
	21	* may be used to endorse or promote products derived from this software
	22	* without specific prior written permission.
	23	*
	24	* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
	25	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
	27	* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
	30	* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
	31	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
	32	* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
	33	* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
	34	* SUCH DAMAGE.
	35	*
	36	* @(#)if_wereg.h 7.1 (Berkeley) 5/9/91
	37	*
	38	* PATCHES MAGIC LEVEL PATCH THAT GOT US HERE
	39	* -------------------- ----- ----------------------
	40	* CURRENT PATCH LEVEL: 1 00100
	41	* -------------------- ----- ----------------------
	42	*
	43	* 20 Sep 92 Barry Lustig WD8013 16 bit mode -- enable
	44	* with "options WD8013".
	45	*/
	46
	47	/*
	48	* Western Digital 8003 ethernet/starlan adapter
	49	*/
	50
	51	/*
	52	* Memory Select Register (MSR)
	53	*/
	54	union we_mem_sel {
	55	struct memory_decode {
	56	u_char msd_addr:6, /* Memory decode bits */
	57	msd_enable:1, /* Memory (RAM) enable */
	58	msd_reset:1; /* Software reset */
	59	} msd_decode;
	60	#define ms_addr msd_decode.msd_addr
	61	#define ms_enable msd_decode.msd_enable
	62	#define ms_reset msd_decode.msd_reset
	63	u_char ms_byte; /* entire byte */
	64	};
65
66	/* 20 Sep 92*/
67	/*
68	* LA Address Register (LAAR)
69	*/
70	union we_laar {
71	struct lan_addr_reg {
72	u_char addr_l19_b:1, /* Address Line 19 for enabling */
73	/* 16 bit NIC access to shared RAM */
74	unused_b:5, /* unused (or unknown) bits */
75	lan_16_en_b:1, /* Enables 16bit shrd RAM for LAN */
76	mem_16_en_b:1; /* Enables 16bit shrd RAM for host */
77	} laar_decode;
78	#define addr_l19 laar_decode.addr_l19_b
79	#define lan_16_en laar_decode.lan_16_en_b
80	#define mem_16_en laar_decode.mem_16_en_b
81	u_char laar_byte; /* entire byte */
82	};
83
84	/*
85	* receive ring discriptor
86	*
87	* The National Semiconductor DS8390 Network interface controller uses
88	* the following receive ring headers. The way this works is that the
89	* memory on the interface card is chopped up into 256 bytes blocks.
90	* A contiguous portion of those blocks are marked for receive packets
91	* by setting start and end block #'s in the NIC. For each packet that
92	* is put into the receive ring, one of these headers (4 bytes each) is
93	* tacked onto the front.
94	*/
95	struct we_ring {
96	struct wer_status { /* received packet status */
97	u_char rs_prx:1, /* packet received intack */
98	rs_crc:1, /* crc error */
99	rs_fae:1, /* frame alignment error */
100	rs_fo:1, /* fifo overrun */
101	rs_mpa:1, /* packet received intack */
102	rs_phy:1, /* packet received intack */
103	rs_dis:1, /* packet received intack */
104	rs_dfr:1; /* packet received intack */
105	} we_rcv_status; /* received packet status */
106	u_char we_next_packet; /* pointer to next packet */
107	u_short we_count; /* bytes in packet (length + 4) */
108	};
109
110	/*
111	* Command word definition
112	*/
113	union we_command {
114	struct command_decode {
115	u_char csd_stp:1, /* STOP! */
116	csd_sta:1, /* START! */
117	csd_txp:1, /* Transmit packet */
118	csd_rd:3, /* Remote DMA command */
119	csd_ps:2; /* Page select */
120	} csd_decode;
121	#define cs_stp csd_decode.csd_stp
122	#define cs_sta csd_decode.csd_sta
123	#define cs_txp csd_decode.csd_txp
124	#define cs_rd csd_decode.csd_rd
125	#define cs_ps csd_decode.csd_ps
126	u_char cs_byte; /* entire command byte */
127	};
128
129	/*
130	* Interrupt status definition
131	*/
132	union we_interrupt {
133	struct interrupt_decode {
134	u_char isd_prx:1, /* Packet received */
135	isd_ptx:1, /* Packet transmitted */
136	isd_rxe:1, /* Receive error */
137	isd_txe:1, /* Transmit error */
138	isd_ovw:1, /* Overwrite warning */
139	isd_cnt:1, /* Counter overflow */
140	isd_rdc:1, /* Remote DMA complete */
141	isd_rst:1; /* Reset status */
142	} isd_decode;
143	#define is_prx isd_decode.isd_prx
144	#define is_ptx isd_decode.isd_ptx
145	#define is_rxe isd_decode.isd_rxe
146	#define is_txe isd_decode.isd_txe
147	#define is_ovw isd_decode.isd_ovw
148	#define is_cnt isd_decode.isd_cnt
149	#define is_rdc isd_decode.isd_rdc
150	#define is_rst isd_decode.isd_rst
151	u_char is_byte; /* entire interrupt byte */
152	};
153
154	/*
155	* Status word definition (transmit)
156	*/
157	union wet_status {
158	struct tstat {
159	u_char tsd_ptx:1, /* Packet transmitted intack */
160	tsd_dfr:1, /* Non deferred transmition */
161	tsd_col:1, /* Transmit Collided */
162	tsd_abt:1, /* Transmit Aborted (coll > 16) */
163	tsd_crs:1, /* Carrier Sense Lost */
164	tsd_fu:1, /* Fifo Underrun */
165	tsd_chd:1, /* CD Heartbeat */
166	tsd_owc:1; /* Out of Window Collision */
167	} tsd_decode;
168	#define ts_ptx tsd_decode.tsd_ptx
169	#define ts_dfr tsd_decode.tsd_dfr
170	#define ts_col tsd_decode.tsd_col
171	#define ts_abt tsd_decode.tsd_abt
172	#define ts_crs tsd_decode.tsd_crs
173	#define ts_fu tsd_decode.tsd_fu
174	#define ts_chd tsd_decode.tsd_chd
175	#define ts_owc tsd_decode.tsd_owc
176	u_char ts_byte; /* entire transmit byte */
177	};
178
179	/*
180	* General constant definitions
181	*/
182
183	/* Bits in the REGE register */
184	#define WD_MICROCHANEL 0x80 /* Microchannel bus (vs. isa) */
185	#define WD_LARGERAM 0x40 /* Large RAM */
186	#define WD_SOFTCONFIG 0x20 /* Soft config */
187	#define WD_REVMASK 0x1e /* Revision mask */
188	#define WD_ETHERNET 0x01 /* Ethernet (vs. Starlan) */
189
190	#define WD_CHECKSUM 0xFF /* Checksum byte */
191	#define WD_PAGE_SIZE 256 /* Size of RAM pages in bytes */
192	#define WD_TXBUF_SIZE 6 /* Size of TX buffer in pages */
193	#define WD_ROM_OFFSET 8 /* i/o base offset to ROM */
194	#define WD_IO_PORTS 32 /* # of i/o addresses used */
195	#define WD_NIC_OFFSET 16 /* i/o base offset to NIC */
196
197	/*
198	* Page register offset values
199	*/
200	#define WD_P0_COMMAND 0x00 /* Command register */
201	#define WD_P0_PSTART 0x01 /* Page Start register */
202	#define WD_P0_PSTOP 0x02 /* Page Stop register */
203	#define WD_P0_BNRY 0x03 /* Boundary Pointer */
204	#define WD_P0_TSR 0x04 /* Transmit Status (read-only) */
205	#define WD_P0_TPSR WD_P0_TSR /* Transmit Page (write-only) */
206	#define WD_P0_TBCR0 0x05 /* Transmit Byte count, low WO */
207	#define WD_P0_TBCR1 0x06 /* Transmit Byte count, high WO */
208	#define WD_P0_ISR 0x07 /* Interrupt status register */
209	#define WD_P0_RBCR0 0x0A /* Remote byte count low WO */
210	#define WD_P0_RBCR1 0x0B /* Remote byte count high WO */
211	#define WD_P0_RSR 0x0C /* Receive status RO */
212	#define WD_P0_RCR WD_P0_RSR /* Receive configuration WO */
213	#define WD_P0_TCR 0x0D /* Transmit configuration WO */
214	#define WD_P0_DCR 0x0E /* Data configuration WO */
215	#define WD_P0_IMR 0x0F /* Interrupt masks WO */
216	#define WD_P1_COMMAND 0x00 /* Command register */
217	#define WD_P1_PAR0 0x01 /* Physical address register 0 */
218	#define WD_P1_PAR1 0x02 /* Physical address register 1 */
219	#define WD_P1_PAR2 0x03 /* Physical address register 2 */
220	#define WD_P1_PAR3 0x04 /* Physical address register 3 */
221	#define WD_P1_PAR4 0x05 /* Physical address register 4 */
222	#define WD_P1_PAR5 0x06 /* Physical address register 5 */
223	#define WD_P1_CURR 0x07 /* Current page (receive unit) */
224	#define WD_P1_MAR0 0x08 /* Multicast address register 0 */
225
226	/*
227	* Configuration constants (receive unit)
228	*/
229	#define WD_R_SEP 0x01 /* Save error packets */
230	#define WD_R_AR 0x02 /* Accept Runt packets */
231	#define WD_R_AB 0x04 /* Accept Broadcast packets */
232	#define WD_R_AM 0x08 /* Accept Multicast packets */
233	#define WD_R_PRO 0x10 /* Promiscuous physical */
234	#define WD_R_MON 0x20 /* Monitor mode */
235	#define WD_R_RES1 0x40 /* reserved... */
236	#define WD_R_RES2 0x80 /* reserved... */
237	#define WD_R_CONFIG (WD_R_AB)
238
239	/*
240	* Configuration constants (transmit unit)
241	*/
242	#define WD_T_CRC 0x01 /* Inhibit CRC */
243	#define WD_T_LB0 0x02 /* Encoded Loopback Control */
244	#define WD_T_LB1 0x04 /* Encoded Loopback Control */
245	#define WD_T_ATD 0x08 /* Auto Transmit Disable */
246	#define WD_T_OFST 0x10 /* Collision Offset Enable */
247	#define WD_T_RES1 0x20 /* reserved... */
248	#define WD_T_RES2 0x40 /* reserved... */
249	#define WD_T_RES3 0x80 /* reserved... */
250	#define WD_T_CONFIG (0)
251
252	/*
253	* Configuration constants (data unit)
254	*/
255	#define WD_D_WTS 0x01 /* Word Transfer Select */
256	#define WD_D_BOS 0x02 /* Byte Order Select */
257	#define WD_D_LAS 0x04 /* Long Address Select */
258	#define WD_D_BMS 0x08 /* Burst Mode Select */
259	#define WD_D_AR 0x10 /* Autoinitialize Remote */
260	#define WD_D_FT0 0x20 /* Fifo Threshold Select */
261	#define WD_D_FT1 0x40 /* Fifo Threshold Select */
262	#define WD_D_RES 0x80 /* reserved... */
263	#define WD_D_CONFIG (WD_D_FT1\|WD_D_BMS)
264	#define WD_D_CONFIG16 (WD_D_FT1\|WD_D_BMS\|WD_D_LAS\|WD_D_WTS) /* 20 Sep 92*/
265
266	/*
267	* Configuration constants (interrupt mask register)
268	*/
269	#define WD_I_PRXE 0x01 /* Packet received enable */
270	#define WD_I_PTXE 0x02 /* Packet transmitted enable */
271	#define WD_I_RXEE 0x04 /* Receive error enable */
272	#define WD_I_TXEE 0x08 /* Transmit error enable */
273	#define WD_I_OVWE 0x10 /* Overwrite warning enable */
274	#define WD_I_CNTE 0x20 /* Counter overflow enable */
275	#define WD_I_RDCE 0x40 /* Dma complete enable */
276	#define WD_I_RES 0x80 /* reserved... */
277	#define WD_I_CONFIG (WD_I_PRXE\|WD_I_PTXE\|WD_I_RXEE\|WD_I_TXEE)