[unix-history] / usr / src / sys / pmax / dev / sccreg.h

/*-
 * Copyright (c) 1992, 1993
 *	The Regents of the University of California.  All rights reserved.
 *
 * This code is derived from software contributed to Berkeley by
 * Ralph Campbell and Rick Macklem.
 *
 * %sccs.include.redist.c%
 *
 *	@(#)sccreg.h	8.1 (Berkeley) %G%
 */

/* 
 * Mach Operating System
 * Copyright (c) 1991,1990,1989 Carnegie Mellon University
 * All Rights Reserved.
 * 
 * Permission to use, copy, modify and distribute this software and its
 * documentation is hereby granted, provided that both the copyright
 * notice and this permission notice appear in all copies of the
 * software, derivative works or modified versions, and any portions
 * thereof, and that both notices appear in supporting documentation.
 * 
 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
 * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
 * 
 * Carnegie Mellon requests users of this software to return to
 * 
 *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
 *  School of Computer Science
 *  Carnegie Mellon University
 *  Pittsburgh PA 15213-3890
 * 
 * any improvements or extensions that they make and grant Carnegie Mellon
 * the rights to redistribute these changes.
 */
/*
 * Definitions for Intel 82530 serial communications chip.
 * Each chip is a dual uart with the A channels used for the keyboard and
 * mouse with the B channel(s) for comm ports with modem control. Since
 * some registers are used for the other channel, the following macros
 * are used to access the register ports.
 */
typedef struct {
    /* Channel B is first, then A */
    struct {
	char		scc_pad0;
	volatile u_char	scc_command;	/* reg select */
	char		scc_pad1[3];
	volatile u_char	scc_data;	/* Rx/Tx buffer */
	char		scc_pad3[2];
    } scc_channel[2];
} scc_regmap_t;

#define	SCC_CHANNEL_A	1
#define	SCC_CHANNEL_B	0

#define	SCC_INIT_REG(scc,chan)		{ \
		char tmp; \
		tmp = (scc)->scc_channel[(chan)].scc_command; \
		tmp = (scc)->scc_channel[(chan)].scc_command; \
	}

#define	SCC_READ_REG(scc,chan,reg,val)	{ \
		(scc)->scc_channel[(chan)].scc_command = (reg); \
		(val) = (scc)->scc_channel[(chan)].scc_command; \
	}

#define	SCC_READ_REG_ZERO(scc,chan,val)	{ \
		(val) = (scc)->scc_channel[(chan)].scc_command; \
	}

#define	SCC_WRITE_REG(scc,chan,reg,val)	{ \
		(scc)->scc_channel[(chan)].scc_command = (reg); \
		(scc)->scc_channel[(chan)].scc_command = (val); \
	}

#define	SCC_WRITE_REG_ZERO(scc,chan,val) { \
		(scc)->scc_channel[(chan)].scc_command = (val); \
	}

#define	SCC_READ_DATA(scc,chan,val)	{ \
		(val) = (scc)->scc_channel[(chan)].scc_data; \
	}

#define	SCC_WRITE_DATA(scc,chan,val) { \
		(scc)->scc_channel[(chan)].scc_data = (val); \
	}

#define	SCC_RR0		0	/* status register */
#define	SCC_RR1		1	/* special receive conditions */
#define	SCC_RR2		2	/* (modified) interrupt vector */
#define	SCC_RR3		3	/* interrupts pending (cha A only) */
#define	SCC_RR8		8	/* recv buffer (alias for data) */
#define	SCC_RR10	10	/* sdlc status */
#define	SCC_RR12	12	/* BRG constant, low part */
#define	SCC_RR13	13	/* BRG constant, high part */
#define	SCC_RR15	15	/* interrupts currently enabled */

#define	SCC_WR0		0	/* reg select, and commands */
#define	SCC_WR1		1	/* interrupt and DMA enables */
#define	SCC_WR2		2	/* interrupt vector */
#define	SCC_WR3		3	/* receiver params and enables */
#define	SCC_WR4		4	/* clock/char/parity params */
#define	SCC_WR5		5	/* xmit params and enables */
#define	SCC_WR6		6	/* synchr SYNCH/address */
#define	SCC_WR7		7	/* synchr SYNCH/flag */
#define	SCC_WR8		8	/* xmit buffer (alias for data) */
#define	SCC_WR9		9	/* vectoring and resets */
#define	SCC_WR10	10	/* synchr params */
#define	SCC_WR11	11	/* clocking definitions */
#define	SCC_WR12	12	/* BRG constant, low part */
#define	SCC_WR13	13	/* BRG constant, high part */
#define	SCC_WR14	14	/* BRG enables and commands */
#define	SCC_WR15	15	/* interrupt enables */

/*
 * Read registers defines
 */
#define	SCC_RR0_BREAK		0x80	/* break detected (rings twice), or */
#define	SCC_RR0_ABORT		0x80	/* abort (synchr) */
#define	SCC_RR0_TX_UNDERRUN	0x40	/* xmit buffer empty/end of message */
#define	SCC_RR0_CTS		0x20	/* clear-to-send pin active (sampled
					   only on intr and after RESI cmd */
#define	SCC_RR0_SYNCH		0x10	/* SYNCH found/still hunting */
#define	SCC_RR0_DCD		0x08	/* carrier-detect (same as CTS) */
#define	SCC_RR0_TX_EMPTY	0x04	/* xmit buffer empty */
#define	SCC_RR0_ZERO_COUNT	0x02	/* ? */
#define	SCC_RR0_RX_AVAIL	0x01	/* recv fifo not empty */

#define	SCC_RR1_EOF		0x80	/* end-of-frame, SDLC mode */
#define	SCC_RR1_CRC_ERR		0x40	/* incorrect CRC or.. */
#define	SCC_RR1_FRAME_ERR	0x40	/* ..bad frame */
#define	SCC_RR1_RX_OVERRUN	0x20	/* rcv fifo overflow */
#define	SCC_RR1_PARITY_ERR	0x10	/* incorrect parity in data */
#define	SCC_RR1_RESIDUE0	0x08
#define	SCC_RR1_RESIDUE1	0x04
#define	SCC_RR1_RESIDUE2	0x02
#define	SCC_RR1_ALL_SENT	0x01

/* RR2 contains the interrupt vector unmodified (channel A) or
   modified as follows (channel B, if vector-include-status) */

#define	SCC_RR2_STATUS(val)	((val)&0xf)

#define	SCC_RR2_B_XMIT_DONE	0x0
#define	SCC_RR2_B_EXT_STATUS	0x2
#define	SCC_RR2_B_RECV_DONE	0x4
#define	SCC_RR2_B_RECV_SPECIAL	0x6
#define	SCC_RR2_A_XMIT_DONE	0x8
#define	SCC_RR2_A_EXT_STATUS	0xa
#define	SCC_RR2_A_RECV_DONE	0xc
#define	SCC_RR2_A_RECV_SPECIAL	0xe

/* Interrupts pending, to be read from channel A only (B raz) */
#define	SCC_RR3_zero		0xc0
#define	SCC_RR3_RX_IP_A		0x20
#define	SCC_RR3_TX_IP_A		0x10
#define	SCC_RR3_EXT_IP_A	0x08
#define	SCC_RR3_RX_IP_B		0x04
#define	SCC_RR3_TX_IP_B		0x02
#define	SCC_RR3_EXT_IP_B	0x01

/* RR8 is the receive data buffer, a 3 deep FIFO */
#define	SCC_RECV_BUFFER		SCC_RR8
#define	SCC_RECV_FIFO_DEEP	3

#define	SCC_RR10_1CLKS		0x80
#define	SCC_RR10_2CLKS		0x40
#define	SCC_RR10_zero		0x2d
#define	SCC_RR10_LOOP_SND	0x10
#define	SCC_RR10_ON_LOOP	0x02

/* RR12/RR13 hold the timing base, upper byte in RR13 */

#define	SCC_GET_TIMING_BASE(scc,chan,val)	{ \
		register char	tmp;	\
		SCC_READ_REG(scc,chan,SCC_RR12,val);\
		SCC_READ_REG(scc,chan,SCC_RR13,tmp);\
		(val) = ((val)<<8)|(tmp&0xff);\
	}

#define	SCC_RR15_BREAK_IE	0x80
#define	SCC_RR15_TX_UNDERRUN_IE	0x40
#define	SCC_RR15_CTS_IE		0x20
#define	SCC_RR15_SYNCH_IE	0x10
#define	SCC_RR15_DCD_IE		0x08
#define	SCC_RR15_zero		0x05
#define	SCC_RR15_ZERO_COUNT_IE	0x02

/*
 * Write registers defines
 */
/* WR0 is used for commands too */
#define	SCC_RESET_TXURUN_LATCH	0xc0
#define	SCC_RESET_TX_CRC	0x80
#define	SCC_RESET_RX_CRC	0x40
#define	SCC_RESET_HIGHEST_IUS	0x38	/* channel A only */
#define	SCC_RESET_ERROR		0x30
#define	SCC_RESET_TX_IP		0x28
#define	SCC_IE_NEXT_CHAR	0x20
#define	SCC_SEND_SDLC_ABORT	0x18
#define	SCC_RESET_EXT_IP	0x10

#define	SCC_WR1_DMA_ENABLE	0x80	/* dma control */
#define	SCC_WR1_DMA_MODE	0x40	/* drive ~req for DMA controller */
#define	SCC_WR1_DMA_RECV_DATA	0x20	/* from wire to host memory */
					/* interrupt enable/conditions */
#define	SCC_WR1_RXI_SPECIAL_O	0x18	/* on special only */
#define	SCC_WR1_RXI_ALL_CHAR	0x10	/* on each char, or special */
#define	SCC_WR1_RXI_FIRST_CHAR	0x08	/* on first char, or special */
#define	SCC_WR1_RXI_DISABLE	0x00	/* never on recv */
#define	SCC_WR1_PARITY_IE	0x04	/* on parity errors */
#define	SCC_WR1_TX_IE		0x02
#define	SCC_WR1_EXT_IE		0x01

/* WR2 is common and contains the interrupt vector (high nibble) */

#define	SCC_WR3_RX_8_BITS	0xc0
#define	SCC_WR3_RX_6_BITS	0x80
#define	SCC_WR3_RX_7_BITS	0x40
#define	SCC_WR3_RX_5_BITS	0x00
#define	SCC_WR3_AUTO_ENABLE	0x20
#define	SCC_WR3_HUNT_MODE	0x10
#define	SCC_WR3_RX_CRC_ENABLE	0x08
#define	SCC_WR3_SDLC_SRCH	0x04
#define	SCC_WR3_INHIBIT_SYNCH	0x02
#define	SCC_WR3_RX_ENABLE	0x01

/* Should be re-written after reset */
#define	SCC_WR4_CLK_x64		0xc0	/* clock divide factor */
#define	SCC_WR4_CLK_x32		0x80
#define	SCC_WR4_CLK_x16		0x40
#define	SCC_WR4_CLK_x1		0x00
#define	SCC_WR4_EXT_SYNCH_MODE	0x30	/* synch modes */
#define	SCC_WR4_SDLC_MODE	0x20
#define	SCC_WR4_16BIT_SYNCH	0x10
#define	SCC_WR4_8BIT_SYNCH	0x00
#define	SCC_WR4_2_STOP		0x0c	/* asynch modes */
#define	SCC_WR4_1_5_STOP	0x08
#define	SCC_WR4_1_STOP		0x04
#define	SCC_WR4_SYNCH_MODE	0x00
#define	SCC_WR4_EVEN_PARITY	0x02
#define	SCC_WR4_PARITY_ENABLE	0x01

#define	SCC_WR5_DTR		0x80	/* drive DTR pin */
#define	SCC_WR5_TX_8_BITS	0x60
#define	SCC_WR5_TX_6_BITS	0x40
#define	SCC_WR5_TX_7_BITS	0x20
#define	SCC_WR5_TX_5_BITS	0x00
#define	SCC_WR5_SEND_BREAK	0x10
#define	SCC_WR5_TX_ENABLE	0x08
#define	SCC_WR5_CRC_16		0x04	/* CRC if non zero, .. */
#define	SCC_WR5_SDLC		0x00	/* ..SDLC otherwise  */
#define	SCC_WR5_RTS		0x02	/* drive RTS pin */
#define	SCC_WR5_TX_CRC_ENABLE	0x01

/* Registers WR6 and WR7 are for synch modes data, with among other things: */

#define	SCC_WR6_BISYNCH_12	0x0f
#define	SCC_WR6_SDLC_RANGE_MASK	0x0f
#define	SCC_WR7_SDLC_FLAG	0x7e

/* WR8 is the transmit data buffer (no FIFO) */
#define	SCC_XMT_BUFFER		SCC_WR8

#define	SCC_WR9_HW_RESET	0xc0	/* force hardware reset */
#define	SCC_WR9_RESET_CHA_A	0x80
#define	SCC_WR9_RESET_CHA_B	0x40
#define	SCC_WR9_NON_VECTORED	0x20	/* mbz for Zilog chip */
#define	SCC_WR9_STATUS_HIGH	0x10
#define	SCC_WR9_MASTER_IE	0x08
#define	SCC_WR9_DLC		0x04	/* disable-lower-chain */
#define	SCC_WR9_NV		0x02	/* no vector */
#define	SCC_WR9_VIS		0x01	/* vector-includes-status */

#define	SCC_WR10_CRC_PRESET	0x80
#define	SCC_WR10_FM0		0x60
#define	SCC_WR10_FM1		0x40
#define	SCC_WR10_NRZI		0x20
#define	SCC_WR10_NRZ		0x00
#define	SCC_WR10_ACTIVE_ON_POLL	0x10
#define	SCC_WR10_MARK_IDLE	0x08	/* flag if zero */
#define	SCC_WR10_ABORT_ON_URUN	0x04	/* flag if zero */
#define	SCC_WR10_LOOP_MODE	0x02
#define	SCC_WR10_6BIT_SYNCH	0x01
#define	SCC_WR10_8BIT_SYNCH	0x00

#define	SCC_WR11_RTxC_XTAL	0x80	/* RTxC pin is input (ext oscill) */
#define	SCC_WR11_RCLK_DPLL	0x60	/* clock received data on dpll */
#define	SCC_WR11_RCLK_BAUDR	0x40	/* .. on BRG */
#define	SCC_WR11_RCLK_TRc_PIN	0x20	/* .. on TRxC pin */
#define	SCC_WR11_RCLK_RTc_PIN	0x00	/* .. on RTxC pin */
#define	SCC_WR11_XTLK_DPLL	0x18
#define	SCC_WR11_XTLK_BAUDR	0x10
#define	SCC_WR11_XTLK_TRc_PIN	0x08
#define	SCC_WR11_XTLK_RTc_PIN	0x00
#define	SCC_WR11_TRc_OUT	0x04	/* drive TRxC pin as output from..*/
#define	SCC_WR11_TRcOUT_DPLL	0x03	/* .. the dpll */
#define	SCC_WR11_TRcOUT_BAUDR	0x02	/* .. the BRG */
#define	SCC_WR11_TRcOUT_XMTCLK	0x01	/* .. the xmit clock */
#define	SCC_WR11_TRcOUT_XTAL	0x00	/* .. the external oscillator */

/* WR12/WR13 are for timing base preset */
#define	SCC_SET_TIMING_BASE(scc,chan,val)	{ \
		SCC_WRITE_REG(scc,chan,SCC_RR12,val);\
		SCC_WRITE_REG(scc,chan,SCC_RR13,(val)>>8);\
	}

/* More commands in this register */
#define	SCC_WR14_NRZI_MODE	0xe0	/* synch modulations */
#define	SCC_WR14_FM_MODE	0xc0
#define	SCC_WR14_RTc_SOURCE	0xa0	/* clock is from pin .. */
#define	SCC_WR14_BAUDR_SOURCE	0x80	/* .. or internal BRG */
#define	SCC_WR14_DISABLE_DPLL	0x60
#define	SCC_WR14_RESET_CLKMISS	0x40
#define	SCC_WR14_SEARCH_MODE	0x20
/* ..and more bitsy */
#define	SCC_WR14_LOCAL_LOOPB	0x10
#define	SCC_WR14_AUTO_ECHO	0x08
#define	SCC_WR14_DTR_REQUEST	0x04
#define	SCC_WR14_BAUDR_SRC	0x02
#define	SCC_WR14_BAUDR_ENABLE	0x01

#define	SCC_WR15_BREAK_IE	0x80
#define	SCC_WR15_TX_UNDERRUN_IE	0x40
#define	SCC_WR15_CTS_IE		0x20
#define	SCC_WR15_SYNCHUNT_IE	0x10
#define	SCC_WR15_DCD_IE		0x08
#define	SCC_WR15_zero		0x05
#define	SCC_WR15_ZERO_COUNT_IE	0x02

/* bits in dm lsr, copied from dmreg.h */
#define	DML_DSR		0000400		/* data set ready, not a real DM bit */
#define	DML_RNG		0000200		/* ring */
#define	DML_CAR		0000100		/* carrier detect */
#define	DML_CTS		0000040		/* clear to send */
#define	DML_SR		0000020		/* secondary receive */
#define	DML_ST		0000010		/* secondary transmit */
#define	DML_RTS		0000004		/* request to send */
#define	DML_DTR		0000002		/* data terminal ready */
#define	DML_LE		0000001		/* line enable */

/*
 * Minor device numbers for scc. Weird because B channel comes
 * first and the A channels are wired for keyboard/mouse and the
 * B channels for the comm port(s).
 */
#define	SCCCOMM2_PORT	0x0
#define	SCCMOUSE_PORT	0x1
#define	SCCCOMM3_PORT	0x2
#define	SCCKBD_PORT	0x3
Commit	Line	Data
c16df7fe	1	/*-
86090d31 KB	2	* Copyright (c) 1992, 1993
86090d31 KB	3	* The Regents of the University of California. All rights reserved.
c16df7fe RC	4	*
	5	* This code is derived from software contributed to Berkeley by
	6	* Ralph Campbell and Rick Macklem.
	7	*
	8	* %sccs.include.redist.c%
	9	*
86090d31	10	* @(#)sccreg.h 8.1 (Berkeley) %G%
c16df7fe RC	11	*/
	12
	13	/*
	14	* Mach Operating System
	15	* Copyright (c) 1991,1990,1989 Carnegie Mellon University
	16	* All Rights Reserved.
	17	*
	18	* Permission to use, copy, modify and distribute this software and its
	19	* documentation is hereby granted, provided that both the copyright
	20	* notice and this permission notice appear in all copies of the
	21	* software, derivative works or modified versions, and any portions
	22	* thereof, and that both notices appear in supporting documentation.
	23	*
	24	* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
	25	* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
	26	* ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
	27	*
	28	* Carnegie Mellon requests users of this software to return to
	29	*
	30	* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
	31	* School of Computer Science
	32	* Carnegie Mellon University
	33	* Pittsburgh PA 15213-3890
	34	*
	35	* any improvements or extensions that they make and grant Carnegie Mellon
	36	* the rights to redistribute these changes.
	37	*/
	38	/*
	39	* Definitions for Intel 82530 serial communications chip.
	40	* Each chip is a dual uart with the A channels used for the keyboard and
	41	* mouse with the B channel(s) for comm ports with modem control. Since
	42	* some registers are used for the other channel, the following macros
	43	* are used to access the register ports.
	44	*/
	45	typedef struct {
	46	/* Channel B is first, then A */
	47	struct {
	48	char scc_pad0;
	49	volatile u_char scc_command; /* reg select */
	50	char scc_pad1[3];
	51	volatile u_char scc_data; /* Rx/Tx buffer */
	52	char scc_pad3[2];
	53	} scc_channel[2];
	54	} scc_regmap_t;
	55
	56	#define SCC_CHANNEL_A 1
	57	#define SCC_CHANNEL_B 0
	58
	59	#define SCC_INIT_REG(scc,chan) { \
	60	char tmp; \
	61	tmp = (scc)->scc_channel[(chan)].scc_command; \
	62	tmp = (scc)->scc_channel[(chan)].scc_command; \
	63	}
	64
	65	#define SCC_READ_REG(scc,chan,reg,val) { \
	66	(scc)->scc_channel[(chan)].scc_command = (reg); \
	67	(val) = (scc)->scc_channel[(chan)].scc_command; \
	68	}
	69
	70	#define SCC_READ_REG_ZERO(scc,chan,val) { \
	71	(val) = (scc)->scc_channel[(chan)].scc_command; \
	72	}
	73
	74	#define SCC_WRITE_REG(scc,chan,reg,val) { \
75	(scc)->scc_channel[(chan)].scc_command = (reg); \
76	(scc)->scc_channel[(chan)].scc_command = (val); \
77	}
78
79	#define SCC_WRITE_REG_ZERO(scc,chan,val) { \
80	(scc)->scc_channel[(chan)].scc_command = (val); \
81	}
82
83	#define SCC_READ_DATA(scc,chan,val) { \
84	(val) = (scc)->scc_channel[(chan)].scc_data; \
85	}
86
87	#define SCC_WRITE_DATA(scc,chan,val) { \
88	(scc)->scc_channel[(chan)].scc_data = (val); \
89	}
90
91	#define SCC_RR0 0 /* status register */
92	#define SCC_RR1 1 /* special receive conditions */
93	#define SCC_RR2 2 /* (modified) interrupt vector */
94	#define SCC_RR3 3 /* interrupts pending (cha A only) */
95	#define SCC_RR8 8 /* recv buffer (alias for data) */
96	#define SCC_RR10 10 /* sdlc status */
97	#define SCC_RR12 12 /* BRG constant, low part */
98	#define SCC_RR13 13 /* BRG constant, high part */
99	#define SCC_RR15 15 /* interrupts currently enabled */
100
101	#define SCC_WR0 0 /* reg select, and commands */
102	#define SCC_WR1 1 /* interrupt and DMA enables */
103	#define SCC_WR2 2 /* interrupt vector */
104	#define SCC_WR3 3 /* receiver params and enables */
105	#define SCC_WR4 4 /* clock/char/parity params */
106	#define SCC_WR5 5 /* xmit params and enables */
107	#define SCC_WR6 6 /* synchr SYNCH/address */
108	#define SCC_WR7 7 /* synchr SYNCH/flag */
109	#define SCC_WR8 8 /* xmit buffer (alias for data) */
110	#define SCC_WR9 9 /* vectoring and resets */
111	#define SCC_WR10 10 /* synchr params */
112	#define SCC_WR11 11 /* clocking definitions */
113	#define SCC_WR12 12 /* BRG constant, low part */
114	#define SCC_WR13 13 /* BRG constant, high part */
115	#define SCC_WR14 14 /* BRG enables and commands */
116	#define SCC_WR15 15 /* interrupt enables */
117
118	/*
119	* Read registers defines
120	*/
121	#define SCC_RR0_BREAK 0x80 /* break detected (rings twice), or */
122	#define SCC_RR0_ABORT 0x80 /* abort (synchr) */
123	#define SCC_RR0_TX_UNDERRUN 0x40 /* xmit buffer empty/end of message */
124	#define SCC_RR0_CTS 0x20 /* clear-to-send pin active (sampled
125	only on intr and after RESI cmd */
126	#define SCC_RR0_SYNCH 0x10 /* SYNCH found/still hunting */
127	#define SCC_RR0_DCD 0x08 /* carrier-detect (same as CTS) */
128	#define SCC_RR0_TX_EMPTY 0x04 /* xmit buffer empty */
129	#define SCC_RR0_ZERO_COUNT 0x02 /* ? */
130	#define SCC_RR0_RX_AVAIL 0x01 /* recv fifo not empty */
131
132	#define SCC_RR1_EOF 0x80 /* end-of-frame, SDLC mode */
133	#define SCC_RR1_CRC_ERR 0x40 /* incorrect CRC or.. */
134	#define SCC_RR1_FRAME_ERR 0x40 /* ..bad frame */
135	#define SCC_RR1_RX_OVERRUN 0x20 /* rcv fifo overflow */
136	#define SCC_RR1_PARITY_ERR 0x10 /* incorrect parity in data */
137	#define SCC_RR1_RESIDUE0 0x08
138	#define SCC_RR1_RESIDUE1 0x04
139	#define SCC_RR1_RESIDUE2 0x02
140	#define SCC_RR1_ALL_SENT 0x01
141
142	/* RR2 contains the interrupt vector unmodified (channel A) or
143	modified as follows (channel B, if vector-include-status) */
144
145	#define SCC_RR2_STATUS(val) ((val)&0xf)
146
147	#define SCC_RR2_B_XMIT_DONE 0x0
148	#define SCC_RR2_B_EXT_STATUS 0x2
149	#define SCC_RR2_B_RECV_DONE 0x4
150	#define SCC_RR2_B_RECV_SPECIAL 0x6
151	#define SCC_RR2_A_XMIT_DONE 0x8
152	#define SCC_RR2_A_EXT_STATUS 0xa
153	#define SCC_RR2_A_RECV_DONE 0xc
154	#define SCC_RR2_A_RECV_SPECIAL 0xe
155
156	/* Interrupts pending, to be read from channel A only (B raz) */
157	#define SCC_RR3_zero 0xc0
158	#define SCC_RR3_RX_IP_A 0x20
159	#define SCC_RR3_TX_IP_A 0x10
160	#define SCC_RR3_EXT_IP_A 0x08
161	#define SCC_RR3_RX_IP_B 0x04
162	#define SCC_RR3_TX_IP_B 0x02
163	#define SCC_RR3_EXT_IP_B 0x01
164
165	/* RR8 is the receive data buffer, a 3 deep FIFO */
166	#define SCC_RECV_BUFFER SCC_RR8
167	#define SCC_RECV_FIFO_DEEP 3
168
169	#define SCC_RR10_1CLKS 0x80
170	#define SCC_RR10_2CLKS 0x40
171	#define SCC_RR10_zero 0x2d
172	#define SCC_RR10_LOOP_SND 0x10
173	#define SCC_RR10_ON_LOOP 0x02
174
175	/* RR12/RR13 hold the timing base, upper byte in RR13 */
176
177	#define SCC_GET_TIMING_BASE(scc,chan,val) { \
178	register char tmp; \
179	SCC_READ_REG(scc,chan,SCC_RR12,val);\
180	SCC_READ_REG(scc,chan,SCC_RR13,tmp);\
181	(val) = ((val)<<8)\|(tmp&0xff);\
182	}
183
184	#define SCC_RR15_BREAK_IE 0x80
185	#define SCC_RR15_TX_UNDERRUN_IE 0x40
186	#define SCC_RR15_CTS_IE 0x20
187	#define SCC_RR15_SYNCH_IE 0x10
188	#define SCC_RR15_DCD_IE 0x08
189	#define SCC_RR15_zero 0x05
190	#define SCC_RR15_ZERO_COUNT_IE 0x02
191
192	/*
193	* Write registers defines
194	*/
195	/* WR0 is used for commands too */
196	#define SCC_RESET_TXURUN_LATCH 0xc0
197	#define SCC_RESET_TX_CRC 0x80
198	#define SCC_RESET_RX_CRC 0x40
199	#define SCC_RESET_HIGHEST_IUS 0x38 /* channel A only */
200	#define SCC_RESET_ERROR 0x30
201	#define SCC_RESET_TX_IP 0x28
202	#define SCC_IE_NEXT_CHAR 0x20
203	#define SCC_SEND_SDLC_ABORT 0x18
204	#define SCC_RESET_EXT_IP 0x10
205
206	#define SCC_WR1_DMA_ENABLE 0x80 /* dma control */
207	#define SCC_WR1_DMA_MODE 0x40 /* drive ~req for DMA controller */
208	#define SCC_WR1_DMA_RECV_DATA 0x20 /* from wire to host memory */
209	/* interrupt enable/conditions */
210	#define SCC_WR1_RXI_SPECIAL_O 0x18 /* on special only */
211	#define SCC_WR1_RXI_ALL_CHAR 0x10 /* on each char, or special */
212	#define SCC_WR1_RXI_FIRST_CHAR 0x08 /* on first char, or special */
213	#define SCC_WR1_RXI_DISABLE 0x00 /* never on recv */
214	#define SCC_WR1_PARITY_IE 0x04 /* on parity errors */
215	#define SCC_WR1_TX_IE 0x02
216	#define SCC_WR1_EXT_IE 0x01
217
218	/* WR2 is common and contains the interrupt vector (high nibble) */
219
220	#define SCC_WR3_RX_8_BITS 0xc0
221	#define SCC_WR3_RX_6_BITS 0x80
222	#define SCC_WR3_RX_7_BITS 0x40
223	#define SCC_WR3_RX_5_BITS 0x00
224	#define SCC_WR3_AUTO_ENABLE 0x20
225	#define SCC_WR3_HUNT_MODE 0x10
226	#define SCC_WR3_RX_CRC_ENABLE 0x08
227	#define SCC_WR3_SDLC_SRCH 0x04
228	#define SCC_WR3_INHIBIT_SYNCH 0x02
229	#define SCC_WR3_RX_ENABLE 0x01
230
231	/* Should be re-written after reset */
232	#define SCC_WR4_CLK_x64 0xc0 /* clock divide factor */
233	#define SCC_WR4_CLK_x32 0x80
234	#define SCC_WR4_CLK_x16 0x40
235	#define SCC_WR4_CLK_x1 0x00
236	#define SCC_WR4_EXT_SYNCH_MODE 0x30 /* synch modes */
237	#define SCC_WR4_SDLC_MODE 0x20
238	#define SCC_WR4_16BIT_SYNCH 0x10
239	#define SCC_WR4_8BIT_SYNCH 0x00
240	#define SCC_WR4_2_STOP 0x0c /* asynch modes */
241	#define SCC_WR4_1_5_STOP 0x08
242	#define SCC_WR4_1_STOP 0x04
243	#define SCC_WR4_SYNCH_MODE 0x00
244	#define SCC_WR4_EVEN_PARITY 0x02
245	#define SCC_WR4_PARITY_ENABLE 0x01
246
247	#define SCC_WR5_DTR 0x80 /* drive DTR pin */
248	#define SCC_WR5_TX_8_BITS 0x60
249	#define SCC_WR5_TX_6_BITS 0x40
250	#define SCC_WR5_TX_7_BITS 0x20
251	#define SCC_WR5_TX_5_BITS 0x00
252	#define SCC_WR5_SEND_BREAK 0x10
253	#define SCC_WR5_TX_ENABLE 0x08
254	#define SCC_WR5_CRC_16 0x04 /* CRC if non zero, .. */
255	#define SCC_WR5_SDLC 0x00 /* ..SDLC otherwise */
256	#define SCC_WR5_RTS 0x02 /* drive RTS pin */
257	#define SCC_WR5_TX_CRC_ENABLE 0x01
258
259	/* Registers WR6 and WR7 are for synch modes data, with among other things: */
260
261	#define SCC_WR6_BISYNCH_12 0x0f
262	#define SCC_WR6_SDLC_RANGE_MASK 0x0f
263	#define SCC_WR7_SDLC_FLAG 0x7e
264
265	/* WR8 is the transmit data buffer (no FIFO) */
266	#define SCC_XMT_BUFFER SCC_WR8
267
268	#define SCC_WR9_HW_RESET 0xc0 /* force hardware reset */
269	#define SCC_WR9_RESET_CHA_A 0x80
270	#define SCC_WR9_RESET_CHA_B 0x40
271	#define SCC_WR9_NON_VECTORED 0x20 /* mbz for Zilog chip */
272	#define SCC_WR9_STATUS_HIGH 0x10
273	#define SCC_WR9_MASTER_IE 0x08
274	#define SCC_WR9_DLC 0x04 /* disable-lower-chain */
275	#define SCC_WR9_NV 0x02 /* no vector */
276	#define SCC_WR9_VIS 0x01 /* vector-includes-status */
277
278	#define SCC_WR10_CRC_PRESET 0x80
279	#define SCC_WR10_FM0 0x60
280	#define SCC_WR10_FM1 0x40
281	#define SCC_WR10_NRZI 0x20
282	#define SCC_WR10_NRZ 0x00
283	#define SCC_WR10_ACTIVE_ON_POLL 0x10
284	#define SCC_WR10_MARK_IDLE 0x08 /* flag if zero */
285	#define SCC_WR10_ABORT_ON_URUN 0x04 /* flag if zero */
286	#define SCC_WR10_LOOP_MODE 0x02
287	#define SCC_WR10_6BIT_SYNCH 0x01
288	#define SCC_WR10_8BIT_SYNCH 0x00
289
290	#define SCC_WR11_RTxC_XTAL 0x80 /* RTxC pin is input (ext oscill) */
291	#define SCC_WR11_RCLK_DPLL 0x60 /* clock received data on dpll */
292	#define SCC_WR11_RCLK_BAUDR 0x40 /* .. on BRG */
293	#define SCC_WR11_RCLK_TRc_PIN 0x20 /* .. on TRxC pin */
294	#define SCC_WR11_RCLK_RTc_PIN 0x00 /* .. on RTxC pin */
295	#define SCC_WR11_XTLK_DPLL 0x18
296	#define SCC_WR11_XTLK_BAUDR 0x10
297	#define SCC_WR11_XTLK_TRc_PIN 0x08
298	#define SCC_WR11_XTLK_RTc_PIN 0x00
299	#define SCC_WR11_TRc_OUT 0x04 /* drive TRxC pin as output from..*/
300	#define SCC_WR11_TRcOUT_DPLL 0x03 /* .. the dpll */
301	#define SCC_WR11_TRcOUT_BAUDR 0x02 /* .. the BRG */
302	#define SCC_WR11_TRcOUT_XMTCLK 0x01 /* .. the xmit clock */
303	#define SCC_WR11_TRcOUT_XTAL 0x00 /* .. the external oscillator */
304
305	/* WR12/WR13 are for timing base preset */
306	#define SCC_SET_TIMING_BASE(scc,chan,val) { \
307	SCC_WRITE_REG(scc,chan,SCC_RR12,val);\
308	SCC_WRITE_REG(scc,chan,SCC_RR13,(val)>>8);\
309	}
310
311	/* More commands in this register */
312	#define SCC_WR14_NRZI_MODE 0xe0 /* synch modulations */
313	#define SCC_WR14_FM_MODE 0xc0
314	#define SCC_WR14_RTc_SOURCE 0xa0 /* clock is from pin .. */
315	#define SCC_WR14_BAUDR_SOURCE 0x80 /* .. or internal BRG */
316	#define SCC_WR14_DISABLE_DPLL 0x60
317	#define SCC_WR14_RESET_CLKMISS 0x40
318	#define SCC_WR14_SEARCH_MODE 0x20
319	/* ..and more bitsy */
320	#define SCC_WR14_LOCAL_LOOPB 0x10
321	#define SCC_WR14_AUTO_ECHO 0x08
322	#define SCC_WR14_DTR_REQUEST 0x04
323	#define SCC_WR14_BAUDR_SRC 0x02
324	#define SCC_WR14_BAUDR_ENABLE 0x01
325
326	#define SCC_WR15_BREAK_IE 0x80
327	#define SCC_WR15_TX_UNDERRUN_IE 0x40
328	#define SCC_WR15_CTS_IE 0x20
329	#define SCC_WR15_SYNCHUNT_IE 0x10
330	#define SCC_WR15_DCD_IE 0x08
331	#define SCC_WR15_zero 0x05
332	#define SCC_WR15_ZERO_COUNT_IE 0x02
333
334	/* bits in dm lsr, copied from dmreg.h */
335	#define DML_DSR 0000400 /* data set ready, not a real DM bit */
336	#define DML_RNG 0000200 /* ring */
337	#define DML_CAR 0000100 /* carrier detect */
338	#define DML_CTS 0000040 /* clear to send */
339	#define DML_SR 0000020 /* secondary receive */
340	#define DML_ST 0000010 /* secondary transmit */
341	#define DML_RTS 0000004 /* request to send */
342	#define DML_DTR 0000002 /* data terminal ready */
343	#define DML_LE 0000001 /* line enable */
344
345	/*
346	* Minor device numbers for scc. Weird because B channel comes
347	* first and the A channels are wired for keyboard/mouse and the
348	* B channels for the comm port(s).
349	*/
350	#define SCCCOMM2_PORT 0x0
a7971d31	351	#define SCCMOUSE_PORT 0x1
c16df7fe	352	#define SCCCOMM3_PORT 0x2
a7971d31	353	#define SCCKBD_PORT 0x3