[unix-history] / usr / src / sys / vax / mba / ht.c

/*	ht.c	4.8	81/03/07	*/

#include "tu.h"
#if NHT > 0
/*
 * TM03/TU?? tape driver
 */
#include "../h/param.h"
#include "../h/systm.h"
#include "../h/buf.h"
#include "../h/conf.h"
#include "../h/dir.h"
#include "../h/file.h"
#include "../h/user.h"
#include "../h/map.h"
#include "../h/pte.h"
#include "../h/mbareg.h"
#include "../h/mbavar.h"
#include "../h/mtio.h"
#include "../h/ioctl.h"
#include "../h/cmap.h"
#include "../h/cpu.h"

#include "../h/htreg.h"

struct	buf	rhtbuf[NHT];
struct	buf	chtbuf[NHT];

short	httypes[] =
	{ MBDT_TE16, MBDT_TU45, MBDT_TU77, 0 };
struct	mba_device *htinfo[NHT];
int	htdkinit(), htattach(), htslave(), htustart(), htndtint(), htdtint();
struct	mba_driver htdriver =
    { htattach, htslave, htustart, 0, htdtint, htndtint,
      httypes, "ht", "tu", htinfo };

#define MASKREG(r)	((r) & 0xffff)

/* bits in minor device */
#define	TUUNIT(dev)	(minor(dev)&03)
#define	H_NOREWIND	04
#define	H_1600BPI	08

#define HTUNIT(dev)	(htunit[TUUNIT(dev)])

#define	INF	(daddr_t)1000000L	/* a block number that wont exist */

struct	ht_softc {
	char	sc_openf;
	char	sc_flags;
	daddr_t	sc_blkno;
	daddr_t	sc_nxrec;
	u_short	sc_erreg;
	u_short	sc_dsreg;
	short	sc_resid;
	short	sc_dens;
	struct	mba_device *sc_mi;
	int	sc_slave;
} ht_softc[NTU];
short	htunit[NTU];

/*
 * Bits for sc_flags.
 */
#define	H_WRITTEN 1	/* last operation was a write */
#define H_ERASED  2	/* last write retry was an erase gap */
#define H_REWIND  4	/* last unit start was a rewind */

/*ARGSUSED*/
htattach(mi)
	struct mba_device *mi;
{

}

htslave(mi, ms)
	struct mba_device *mi;
	struct mba_slave *ms;
{
	register struct ht_softc *sc = &ht_softc[ms->ms_unit];

	sc->sc_mi = mi;
	sc->sc_slave = ms->ms_slave;
	htunit[ms->ms_unit] = mi->mi_unit;
}

htopen(dev, flag)
	dev_t dev;
	int flag;
{
	register int unit;
	register struct mba_device *mi;
	register struct ht_softc *sc;

	unit = TUUNIT(dev);
	if (unit >= NTU || (sc = &ht_softc[unit])->sc_openf ||
	    (mi = htinfo[HTUNIT(dev)]) == 0 || mi->mi_alive == 0) {
		u.u_error = ENXIO;
		return;
	}
	/*
	 * The NOP below serves two purposes:
	 * 1. To get a recent copy of the status registers.
	 * 2. To ensure that any outstanding rewinds are truly finished
	 */
	htcommand(dev, HT_SENSE, 1);
	if ((sc->sc_dsreg & HTDS_MOL) == 0 || 
	   (flag & (FREAD|FWRITE)) == FWRITE && sc->sc_dsreg&HTDS_WRL) {
		u.u_error = EIO;
		return;
	}
	sc->sc_dens =
	    ((minor(dev)&H_1600BPI)?HTTC_1600BPI:HTTC_800BPI)|
		HTTC_PDP11|sc->sc_slave;
	sc->sc_openf = 1;
	sc->sc_blkno = (daddr_t)0;
	sc->sc_nxrec = INF;
	sc->sc_flags = 0;
}

htclose(dev, flag)
	register dev_t dev;
	register flag;
{
	register struct ht_softc *sc = &ht_softc[TUUNIT(dev)];

	if (flag == FWRITE || ((flag&FWRITE) && (sc->sc_flags&H_WRITTEN))) {
		htcommand(dev, HT_WEOF, 1);
		htcommand(dev, HT_WEOF, 1);
		htcommand(dev, HT_SREV, 1);
	}
	if ((minor(dev)&H_NOREWIND) == 0)
		/* 0 as third arg means don't wait */
		htcommand(dev, HT_REW, 0);
	sc->sc_openf = 0;
}

/*
 * Do a non-data-transfer command.
 *
 * N.B.: Count should be zero ONLY for rewind during close.
 */
htcommand(dev, com, count)
	dev_t dev;
	int com, count;
{
	register struct buf *bp;

	bp = &chtbuf[HTUNIT(dev)];
	(void) spl5();
	while (bp->b_flags&B_BUSY) {
		if (bp->b_command == H_REWIND && bp->b_repcnt == 0 &&
		    (bp->b_flags&B_DONE))
			break;
		bp->b_flags |= B_WANTED;
		sleep((caddr_t)bp, PRIBIO);
	}
	bp->b_flags = B_BUSY|B_READ;
	(void) spl0();
	bp->b_dev = dev;
	bp->b_command = com;
	bp->b_repcnt = count;
	bp->b_blkno = 0;
	htstrategy(bp);
	if (count == 0)
		return;
	iowait(bp);
	if (bp->b_flags&B_WANTED)
		wakeup((caddr_t)bp);
	bp->b_flags &= B_ERROR;
}

htstrategy(bp)
	register struct buf *bp;
{
	register int unit = HTUNIT(bp->b_dev);
	register struct mba_device *mi = htinfo[unit];
	register struct buf *dp;

	bp->av_forw = NULL;
	dp = &mi->mi_tab;
	(void) spl5();
	if (dp->b_actf == NULL)
		dp->b_actf = bp;
	else
		dp->b_actl->av_forw = bp;
	dp->b_actl = bp;
	if (dp->b_active == 0)
		mbustart(mi);
	(void) spl0();
}

htustart(mi)
	register struct mba_device *mi;
{
	register struct htdevice *htaddr =
	    (struct htdevice *)mi->mi_drv;
	register struct buf *bp = mi->mi_tab.b_actf;
	int unit = TUUNIT(bp->b_dev);
	register struct ht_softc *sc = &ht_softc[unit];
	daddr_t blkno;

	htaddr->httc = sc->sc_dens;
	sc->sc_dsreg = htaddr->htds;
	sc->sc_erreg = htaddr->hter;
	sc->sc_resid = htaddr->htfc;
	sc->sc_flags &= ~(H_WRITTEN|H_REWIND);
	if ((htaddr->htdt & HTDT_SPR) == 0 || (htaddr->htds & HTDS_MOL) == 0)
		if (sc->sc_openf > 0)
			sc->sc_openf = -1;
	if (sc->sc_openf < 0) {
		bp->b_flags |= B_ERROR;
		return (MBU_NEXT);
	}
	if (bp != &chtbuf[unit]) {
		if (dbtofsb(bp->b_blkno) > sc->sc_nxrec) {
			bp->b_flags |= B_ERROR;
			bp->b_error = ENXIO;
			return (MBU_NEXT);
		} else if (dbtofsb(bp->b_blkno) == sc->sc_nxrec &&
		    bp->b_flags&B_READ) {
			bp->b_resid = bp->b_bcount;
			clrbuf(bp);
			return (MBU_NEXT);
		} else if ((bp->b_flags&B_READ)==0)
			sc->sc_nxrec = dbtofsb(bp->b_blkno) + 1;
	} else {
		if (bp->b_command == HT_SENSE)
			return (MBU_NEXT);
		if (bp->b_command == HT_REW)
			sc->sc_flags |= H_REWIND;
		else
			htaddr->htfc = -bp->b_bcount;
		htaddr->htcs1 = bp->b_command|HT_GO;
		return (MBU_STARTED);
	}
	if ((blkno = sc->sc_blkno) == dbtofsb(bp->b_blkno)) {
		htaddr->htfc = -bp->b_bcount;
		if ((bp->b_flags&B_READ) == 0) {
			if (mi->mi_tab.b_errcnt)
				if (sc->sc_flags & H_ERASED)
					sc->sc_flags &= ~H_ERASED;
				else {
					sc->sc_flags |= H_ERASED;
					htaddr->htcs1 = HT_ERASE | HT_GO;
					return (MBU_STARTED);
				}
			if (htaddr->htds & HTDS_EOT) {
				bp->b_resid = bp->b_bcount;
				return (MBU_NEXT);
			}
		}
		return (MBU_DODATA);
	}
	if (blkno < dbtofsb(bp->b_blkno)) {
		htaddr->htfc = blkno - dbtofsb(bp->b_blkno);
		htaddr->htcs1 = HT_SFORW|HT_GO;
	} else {
		htaddr->htfc = dbtofsb(bp->b_blkno) - blkno;
		htaddr->htcs1 = HT_SREV|HT_GO;
	}
	return (MBU_STARTED);
}

/*
 * data transfer interrupt - must be read or write
 */
/*ARGSUSED*/
htdtint(mi, mbasr)
	register struct mba_device *mi;
	int mbasr;
{
	register struct htdevice *htaddr = (struct htdevice *)mi->mi_drv;
	register struct buf *bp = mi->mi_tab.b_actf;
	register struct ht_softc *sc;
	int ds, er, mbs;

	sc = &ht_softc[TUUNIT(bp->b_dev)];
	ds = sc->sc_dsreg = MASKREG(htaddr->htds);
	er = sc->sc_erreg = MASKREG(htaddr->hter);
	sc->sc_resid = MASKREG(htaddr->htfc);
	mbs = mbasr;
	sc->sc_blkno++;
	if((bp->b_flags & B_READ) == 0)
		sc->sc_flags |= H_WRITTEN;
	if ((ds&(HTDS_ERR|HTDS_MOL)) != HTDS_MOL ||
	    mbs & MBAEBITS) {
		htaddr->htcs1 = HT_DCLR|HT_GO;
		mbclrattn(mi);
		if (bp == &rhtbuf[HTUNIT(bp->b_dev)]) {
			er &= ~HTER_FCE;
			mbs &= ~(MBS_DTABT|MBS_MBEXC);
		}
		if (bp->b_flags & B_READ && ds & HTDS_PES)
			er &= ~(HTER_CSITM|HTER_CORCRC);
		if (er&HTER_HARD ||
		    mbs&MBAEBITS || (ds&HTDS_MOL) == 0 ||
		    er && ++mi->mi_tab.b_errcnt >= 7) {
			if ((ds & HTDS_MOL) == 0 && sc->sc_openf > 0)
				sc->sc_openf = -1;
			printf("tu%d: hard error bn%d mbasr=%b er=%b\n",
			    TUUNIT(bp->b_dev), bp->b_blkno,
			    mbasr, mbasr_bits,
			    MASKREG(htaddr->hter), HTER_BITS);
			bp->b_flags |= B_ERROR;
			return (MBD_DONE);
		}
		if (er)
			return (MBD_RETRY);
	}
	bp->b_resid = 0;
	if (bp->b_flags & B_READ)
		if (ds&HTDS_TM) {		/* must be a read, right? */
			bp->b_resid = bp->b_bcount;
			sc->sc_nxrec = dbtofsb(bp->b_blkno);
		} else if(bp->b_bcount > MASKREG(htaddr->htfc))
			bp->b_resid = bp->b_bcount - MASKREG(htaddr->htfc);
	return (MBD_DONE);
}

/*
 * non-data-transfer interrupt
 */
htndtint(mi)
	register struct mba_device *mi;
{
	register struct htdevice *htaddr = (struct htdevice *)mi->mi_drv;
	register struct buf *bp = mi->mi_tab.b_actf;
	register struct ht_softc *sc;
	int er, ds, fc;

	if (bp == 0)
		return (MBN_SKIP);
	sc = &ht_softc[TUUNIT(bp->b_dev)];
	ds = sc->sc_dsreg = MASKREG(htaddr->htds);
	er = sc->sc_erreg = MASKREG(htaddr->hter);
	fc = sc->sc_resid = MASKREG(htaddr->htfc);
	if (sc->sc_erreg) {
		htaddr->htcs1 = HT_DCLR|HT_GO;
		mbclrattn(mi);
	}
	if (sc->sc_flags&H_REWIND) {
		sc->sc_flags &= ~H_REWIND;
		return (MBN_CONT);
	}
	if (bp == &chtbuf[TUUNIT(bp->b_dev)]) {
		if (bp->b_command == HT_REWOFFL)
			/* offline is on purpose; don't do anything special */
			ds |= HTDS_MOL;	
		else if (bp->b_resid == HT_SREV &&
		    er == (HTER_NEF|HTER_FCE) &&
		    ds&HTDS_BOT && bp->b_bcount == INF)
			er &= ~HTER_NEF;
		er &= ~HTER_FCE;
		if (er == 0)
			ds &= ~HTDS_ERR;
	}
	if ((ds & (HTDS_ERR|HTDS_MOL)) != HTDS_MOL) {
		if ((ds & HTDS_MOL) == 0 && sc->sc_openf > 0)
			sc->sc_openf = -1;
		printf("tu%d: hard error bn%d er=%b ds=%b\n",
		    TUUNIT(bp->b_dev), bp->b_blkno,
		    sc->sc_erreg, HTER_BITS, sc->sc_dsreg, HTDS_BITS);
		bp->b_flags |= B_ERROR;
		return (MBN_DONE);
	}
	if (bp == &chtbuf[TUUNIT(bp->b_dev)]) {
		if (sc->sc_flags & H_REWIND)
			return (ds & HTDS_BOT ? MBN_DONE : MBN_RETRY);
		bp->b_resid = -sc->sc_resid;
		return (MBN_DONE);
	}
	if (ds & HTDS_TM)
		if (sc->sc_blkno > dbtofsb(bp->b_blkno)) {/* reversing */
			sc->sc_nxrec = dbtofsb(bp->b_blkno) - fc;
			sc->sc_blkno = sc->sc_nxrec;
		} else {			/* spacing forward */
			sc->sc_blkno = dbtofsb(bp->b_blkno) + fc;
			sc->sc_nxrec = sc->sc_blkno - 1;
		}
	else
		sc->sc_blkno = dbtofsb(bp->b_blkno);
	return (MBN_RETRY);
}

htread(dev)
	dev_t dev;
{

	htphys(dev);
	if (u.u_error)
		return;
	physio(htstrategy, &rhtbuf[HTUNIT(dev)], dev, B_READ, minphys);
}

htwrite(dev)
{

	htphys(dev);
	if (u.u_error)
		return;
	physio(htstrategy, &rhtbuf[HTUNIT(dev)], dev, B_WRITE, minphys);
}

htphys(dev)
	dev_t dev;
{
	register int unit;
	register struct ht_softc *sc;
	daddr_t a;

	unit = HTUNIT(dev);
	if (unit >= NHT) {
		u.u_error = ENXIO;
		return;
	}
	a = u.u_offset >> 9;
	sc = &ht_softc[unit];
	sc->sc_blkno = dbtofsb(a);
	sc->sc_nxrec = dbtofsb(a)+1;
}

/*ARGSUSED*/
htioctl(dev, cmd, addr, flag)
	dev_t dev;
	int cmd;
	caddr_t addr;
	int flag;
{
	register unit = HTUNIT(dev);
	register struct ht_softc *sc = &ht_softc[unit];
	register struct buf *bp = &chtbuf[unit];
	register callcount;
	int fcount;
	struct mtop mtop;
	struct mtget mtget;
	/* we depend of the values and order of the MT codes here */
	static htops[] =
   {HT_WEOF,HT_SFORW,HT_SREV,HT_SFORW,HT_SREV,HT_REW,HT_REWOFFL,HT_SENSE};

	switch (cmd) {
		case MTIOCTOP:	/* tape operation */
		if (copyin((caddr_t)addr, (caddr_t)&mtop, sizeof(mtop))) {
			u.u_error = EFAULT;
			return;
		}
		switch(mtop.mt_op) {
		case MTWEOF:
			callcount = mtop.mt_count;
			fcount = 1;
			break;
		case MTFSF: case MTBSF:
			callcount = mtop.mt_count;
			fcount = INF;
			break;
		case MTFSR: case MTBSR:
			callcount = 1;
			fcount = mtop.mt_count;
			break;
		case MTREW: case MTOFFL:
			callcount = 1;
			fcount = 1;
			break;
		default:
			u.u_error = ENXIO;
			return;
		}
		if (callcount <= 0 || fcount <= 0) {
			u.u_error = ENXIO;
			return;
		}
		while (--callcount >= 0) {
			htcommand(dev, htops[mtop.mt_op], fcount);
			if ((mtop.mt_op == MTFSR || mtop.mt_op == MTBSR) &&
			    bp->b_resid) {
				u.u_error = EIO;
				break;
			}
			if ((chtbuf[HTUNIT(bp->b_dev)].b_flags&B_ERROR) ||
			    sc->sc_dsreg&HTDS_BOT)
				break;
		}
		geterror(bp);
		return;
	case MTIOCGET:
		mtget.mt_dsreg = sc->sc_dsreg;
		mtget.mt_erreg = sc->sc_erreg;
		mtget.mt_resid = sc->sc_resid;
		if (copyout((caddr_t)&mtget, addr, sizeof(mtget)))
			u.u_error = EFAULT;
		return;
	default:
		u.u_error = ENXIO;
	}
}

#define	DBSIZE	20

htdump()
{
	register struct mba_device *mi;
	register struct mba_regs *mp;
	register struct htdevice *htaddr;
	int blk, num;
	int start;

	start = 0;
	num = maxfree;
#define	phys(a,b)		((b)((int)(a)&0x7fffffff))
	if (htinfo[0] == 0)
		return (ENXIO);
	mi = phys(htinfo[0], struct mba_device *);
	mp = phys(mi->mi_hd, struct mba_hd *)->mh_physmba;
#if VAX780
	if (cpu == VAX780)
		mbainit(mp);
#endif
	htaddr = (struct htdevice *)&mp->mba_drv[mi->mi_drive];
	htaddr->httc = HTTC_PDP11|HTTC_1600BPI;
	htaddr->htcs1 = HT_DCLR|HT_GO;
	while (num > 0) {
		blk = num > DBSIZE ? DBSIZE : num;
		htdwrite(start, blk, htaddr, mp);
		start += blk;
		num -= blk;
	}
	htwait(htaddr);
	htaddr->htcs1 = HT_REW|HT_GO;
	hteof(htaddr);
	hteof(htaddr);
}

htdwrite(dbuf, num, htaddr, mp)
	register dbuf, num;
	register struct htdevice *htaddr;
	struct mba_regs *mp;
{
	register struct pte *io;
	register int i;

	htwait(htaddr);
	io = mp->mba_map;
	for (i = 0; i < num; i++)
		*(int *)io++ = dbuf++ | PG_V;
	htaddr->htfc = -(num*NBPG);
	mp->mba_sr = -1;
	mp->mba_bcr = -(num*NBPG);
	mp->mba_var = 0;
	htaddr->htcs1 = HT_WCOM|HT_GO;
}

htwait(htaddr)
	struct htdevice *htaddr;
{
	register s;

	do
		s = htaddr->htds;
	while ((s & HTDS_DRY) == 0);
}

hteof(htaddr)
	struct htdevice *htaddr;
{

	htwait(htaddr);
	htaddr->htcs1 = HT_WEOF|HT_GO;
}
#endif
Commit	Line	Data
89bd2f01	1	/* ht.c 4.8 81/03/07 */
0deaf016	2
89bd2f01	3	#include "tu.h"
a5cc519e	4	#if NHT > 0
786dff00	5	/*
fcc37d29	6	* TM03/TU?? tape driver
786dff00	7	*/
786dff00 BJ	8	#include "../h/param.h"
	9	#include "../h/systm.h"
	10	#include "../h/buf.h"
	11	#include "../h/conf.h"
	12	#include "../h/dir.h"
	13	#include "../h/file.h"
	14	#include "../h/user.h"
	15	#include "../h/map.h"
80e7c811	16	#include "../h/pte.h"
89bd2f01 BJ	17	#include "../h/mbareg.h"
89bd2f01 BJ	18	#include "../h/mbavar.h"
fcc37d29 BJ	19	#include "../h/mtio.h"
fcc37d29 BJ	20	#include "../h/ioctl.h"
f0a3ddbd	21	#include "../h/cmap.h"
0deaf016	22	#include "../h/cpu.h"
786dff00	23
fcc37d29 BJ	24	#include "../h/htreg.h"
	25
	26	struct buf rhtbuf[NHT];
	27	struct buf chtbuf[NHT];
	28
	29	short httypes[] =
	30	{ MBDT_TE16, MBDT_TU45, MBDT_TU77, 0 };
89bd2f01 BJ	31	struct mba_device *htinfo[NHT];
89bd2f01 BJ	32	int htdkinit(), htattach(), htslave(), htustart(), htndtint(), htdtint();
fcc37d29	33	struct mba_driver htdriver =
89bd2f01 BJ	34	{ htattach, htslave, htustart, 0, htdtint, htndtint,
89bd2f01 BJ	35	httypes, "ht", "tu", htinfo };
fcc37d29 BJ	36
	37	#define MASKREG(r) ((r) & 0xffff)
	38
	39	/* bits in minor device */
89bd2f01	40	#define TUUNIT(dev) (minor(dev)&03)
fcc37d29 BJ	41	#define H_NOREWIND 04
fcc37d29 BJ	42	#define H_1600BPI 08
786dff00	43
89bd2f01 BJ	44	#define HTUNIT(dev) (htunit[TUUNIT(dev)])
89bd2f01 BJ	45
fcc37d29 BJ	46	#define INF (daddr_t)1000000L /* a block number that wont exist */
	47
	48	struct ht_softc {
	49	char sc_openf;
	50	char sc_flags;
	51	daddr_t sc_blkno;
	52	daddr_t sc_nxrec;
	53	u_short sc_erreg;
	54	u_short sc_dsreg;
	55	short sc_resid;
	56	short sc_dens;
89bd2f01 BJ	57	struct mba_device *sc_mi;
	58	int sc_slave;
	59	} ht_softc[NTU];
	60	short htunit[NTU];
fcc37d29	61
fcc37d29 BJ	62	/*
	63	* Bits for sc_flags.
	64	*/
	65	#define H_WRITTEN 1 /* last operation was a write */
	66	#define H_ERASED 2 /* last write retry was an erase gap */
	67	#define H_REWIND 4 /* last unit start was a rewind */
786dff00	68
fcc37d29	69	/ARGSUSED/
89bd2f01 BJ	70	htattach(mi)
	71	struct mba_device *mi;
	72	{
	73
	74	}
	75
	76	htslave(mi, ms)
	77	struct mba_device *mi;
	78	struct mba_slave *ms;
fcc37d29	79	{
89bd2f01	80	register struct ht_softc *sc = &ht_softc[ms->ms_unit];
fcc37d29	81
89bd2f01 BJ	82	sc->sc_mi = mi;
	83	sc->sc_slave = ms->ms_slave;
	84	htunit[ms->ms_unit] = mi->mi_unit;
fcc37d29	85	}
786dff00 BJ	86
786dff00 BJ	87	htopen(dev, flag)
fcc37d29 BJ	88	dev_t dev;
fcc37d29 BJ	89	int flag;
786dff00	90	{
fcc37d29	91	register int unit;
89bd2f01	92	register struct mba_device *mi;
fcc37d29	93	register struct ht_softc *sc;
786dff00	94
89bd2f01 BJ	95	unit = TUUNIT(dev);
	96	if (unit >= NTU \|\| (sc = &ht_softc[unit])->sc_openf \|\|
	97	(mi = htinfo[HTUNIT(dev)]) == 0 \|\| mi->mi_alive == 0) {
786dff00 BJ	98	u.u_error = ENXIO;
	99	return;
	100	}
fcc37d29 BJ	101	/*
	102	* The NOP below serves two purposes:
	103	* 1. To get a recent copy of the status registers.
	104	* 2. To ensure that any outstanding rewinds are truly finished
fcc37d29 BJ	105	*/
	106	htcommand(dev, HT_SENSE, 1);
	107	if ((sc->sc_dsreg & HTDS_MOL) == 0 \|\|
	108	(flag & (FREAD\|FWRITE)) == FWRITE && sc->sc_dsreg&HTDS_WRL) {
	109	u.u_error = EIO;
	110	return;
	111	}
	112	sc->sc_dens =
0deaf016	113	((minor(dev)&H_1600BPI)?HTTC_1600BPI:HTTC_800BPI)\|
89bd2f01	114	HTTC_PDP11\|sc->sc_slave;
fcc37d29 BJ	115	sc->sc_openf = 1;
	116	sc->sc_blkno = (daddr_t)0;
	117	sc->sc_nxrec = INF;
	118	sc->sc_flags = 0;
786dff00 BJ	119	}
	120
	121	htclose(dev, flag)
fcc37d29 BJ	122	register dev_t dev;
fcc37d29 BJ	123	register flag;
786dff00	124	{
89bd2f01	125	register struct ht_softc *sc = &ht_softc[TUUNIT(dev)];
786dff00	126
fcc37d29 BJ	127	if (flag == FWRITE \|\| ((flag&FWRITE) && (sc->sc_flags&H_WRITTEN))) {
	128	htcommand(dev, HT_WEOF, 1);
	129	htcommand(dev, HT_WEOF, 1);
	130	htcommand(dev, HT_SREV, 1);
786dff00	131	}
fcc37d29 BJ	132	if ((minor(dev)&H_NOREWIND) == 0)
	133	/* 0 as third arg means don't wait */
	134	htcommand(dev, HT_REW, 0);
	135	sc->sc_openf = 0;
786dff00 BJ	136	}
786dff00 BJ	137
fcc37d29 BJ	138	/*
	139	* Do a non-data-transfer command.
	140	*
	141	* N.B.: Count should be zero ONLY for rewind during close.
	142	*/
	143	htcommand(dev, com, count)
	144	dev_t dev;
	145	int com, count;
786dff00 BJ	146	{
	147	register struct buf *bp;
	148
fcc37d29	149	bp = &chtbuf[HTUNIT(dev)];
81263dba	150	(void) spl5();
fcc37d29	151	while (bp->b_flags&B_BUSY) {
89bd2f01 BJ	152	if (bp->b_command == H_REWIND && bp->b_repcnt == 0 &&
	153	(bp->b_flags&B_DONE))
	154	break;
786dff00 BJ	155	bp->b_flags \|= B_WANTED;
	156	sleep((caddr_t)bp, PRIBIO);
	157	}
dc637456	158	bp->b_flags = B_BUSY\|B_READ;
81263dba	159	(void) spl0();
786dff00	160	bp->b_dev = dev;
fcc37d29 BJ	161	bp->b_command = com;
fcc37d29 BJ	162	bp->b_repcnt = count;
786dff00	163	bp->b_blkno = 0;
786dff00	164	htstrategy(bp);
fcc37d29 BJ	165	if (count == 0)
fcc37d29 BJ	166	return;
786dff00	167	iowait(bp);
fcc37d29	168	if (bp->b_flags&B_WANTED)
786dff00	169	wakeup((caddr_t)bp);
fcc37d29	170	bp->b_flags &= B_ERROR;
786dff00 BJ	171	}
	172
	173	htstrategy(bp)
fcc37d29	174	register struct buf *bp;
786dff00	175	{
fcc37d29	176	register int unit = HTUNIT(bp->b_dev);
89bd2f01	177	register struct mba_device *mi = htinfo[unit];
fcc37d29	178	register struct buf *dp;
786dff00	179
786dff00	180	bp->av_forw = NULL;
fcc37d29	181	dp = &mi->mi_tab;
81263dba	182	(void) spl5();
fcc37d29 BJ	183	if (dp->b_actf == NULL)
fcc37d29 BJ	184	dp->b_actf = bp;
786dff00	185	else
fcc37d29 BJ	186	dp->b_actl->av_forw = bp;
	187	dp->b_actl = bp;
	188	if (dp->b_active == 0)
	189	mbustart(mi);
81263dba	190	(void) spl0();
786dff00 BJ	191	}
786dff00 BJ	192
fcc37d29	193	htustart(mi)
89bd2f01	194	register struct mba_device *mi;
786dff00	195	{
fcc37d29 BJ	196	register struct htdevice *htaddr =
	197	(struct htdevice *)mi->mi_drv;
	198	register struct buf *bp = mi->mi_tab.b_actf;
89bd2f01	199	int unit = TUUNIT(bp->b_dev);
fcc37d29	200	register struct ht_softc *sc = &ht_softc[unit];
786dff00 BJ	201	daddr_t blkno;
786dff00 BJ	202
fcc37d29 BJ	203	htaddr->httc = sc->sc_dens;
	204	sc->sc_dsreg = htaddr->htds;
	205	sc->sc_erreg = htaddr->hter;
	206	sc->sc_resid = htaddr->htfc;
	207	sc->sc_flags &= ~(H_WRITTEN\|H_REWIND);
	208	if ((htaddr->htdt & HTDT_SPR) == 0 \|\| (htaddr->htds & HTDS_MOL) == 0)
	209	if (sc->sc_openf > 0)
	210	sc->sc_openf = -1;
	211	if (sc->sc_openf < 0) {
	212	bp->b_flags \|= B_ERROR;
	213	return (MBU_NEXT);
	214	}
	215	if (bp != &chtbuf[unit]) {
	216	if (dbtofsb(bp->b_blkno) > sc->sc_nxrec) {
	217	bp->b_flags \|= B_ERROR;
	218	bp->b_error = ENXIO;
0deaf016	219	return (MBU_NEXT);
fcc37d29 BJ	220	} else if (dbtofsb(bp->b_blkno) == sc->sc_nxrec &&
	221	bp->b_flags&B_READ) {
	222	bp->b_resid = bp->b_bcount;
	223	clrbuf(bp);
0deaf016	224	return (MBU_NEXT);
fcc37d29 BJ	225	} else if ((bp->b_flags&B_READ)==0)
	226	sc->sc_nxrec = dbtofsb(bp->b_blkno) + 1;
	227	} else {
0deaf016	228	if (bp->b_command == HT_SENSE)
fcc37d29 BJ	229	return (MBU_NEXT);
	230	if (bp->b_command == HT_REW)
	231	sc->sc_flags \|= H_REWIND;
	232	else
	233	htaddr->htfc = -bp->b_bcount;
	234	htaddr->htcs1 = bp->b_command\|HT_GO;
	235	return (MBU_STARTED);
	236	}
	237	if ((blkno = sc->sc_blkno) == dbtofsb(bp->b_blkno)) {
	238	htaddr->htfc = -bp->b_bcount;
	239	if ((bp->b_flags&B_READ) == 0) {
	240	if (mi->mi_tab.b_errcnt)
	241	if (sc->sc_flags & H_ERASED)
	242	sc->sc_flags &= ~H_ERASED;
	243	else {
	244	sc->sc_flags \|= H_ERASED;
	245	htaddr->htcs1 = HT_ERASE \| HT_GO;
	246	return (MBU_STARTED);
	247	}
	248	if (htaddr->htds & HTDS_EOT) {
	249	bp->b_resid = bp->b_bcount;
	250	return (MBU_NEXT);
	251	}
786dff00	252	}
fcc37d29	253	return (MBU_DODATA);
786dff00	254	}
fcc37d29 BJ	255	if (blkno < dbtofsb(bp->b_blkno)) {
	256	htaddr->htfc = blkno - dbtofsb(bp->b_blkno);
	257	htaddr->htcs1 = HT_SFORW\|HT_GO;
786dff00	258	} else {
fcc37d29 BJ	259	htaddr->htfc = dbtofsb(bp->b_blkno) - blkno;
fcc37d29 BJ	260	htaddr->htcs1 = HT_SREV\|HT_GO;
786dff00	261	}
fcc37d29	262	return (MBU_STARTED);
786dff00 BJ	263	}
786dff00 BJ	264
fcc37d29 BJ	265	/*
	266	* data transfer interrupt - must be read or write
	267	*/
786dff00	268	/ARGSUSED/
fcc37d29	269	htdtint(mi, mbasr)
89bd2f01	270	register struct mba_device *mi;
fcc37d29	271	int mbasr;
786dff00	272	{
fcc37d29 BJ	273	register struct htdevice htaddr = (struct htdevice )mi->mi_drv;
	274	register struct buf *bp = mi->mi_tab.b_actf;
	275	register struct ht_softc *sc;
0deaf016	276	int ds, er, mbs;
786dff00	277
89bd2f01	278	sc = &ht_softc[TUUNIT(bp->b_dev)];
fcc37d29 BJ	279	ds = sc->sc_dsreg = MASKREG(htaddr->htds);
	280	er = sc->sc_erreg = MASKREG(htaddr->hter);
	281	sc->sc_resid = MASKREG(htaddr->htfc);
0deaf016	282	mbs = mbasr;
fcc37d29 BJ	283	sc->sc_blkno++;
	284	if((bp->b_flags & B_READ) == 0)
	285	sc->sc_flags \|= H_WRITTEN;
	286	if ((ds&(HTDS_ERR\|HTDS_MOL)) != HTDS_MOL \|\|
0deaf016	287	mbs & MBAEBITS) {
fcc37d29	288	htaddr->htcs1 = HT_DCLR\|HT_GO;
0deaf016 BJ	289	mbclrattn(mi);
0deaf016 BJ	290	if (bp == &rhtbuf[HTUNIT(bp->b_dev)]) {
fcc37d29	291	er &= ~HTER_FCE;
0deaf016 BJ	292	mbs &= ~(MBS_DTABT\|MBS_MBEXC);
0deaf016 BJ	293	}
fcc37d29 BJ	294	if (bp->b_flags & B_READ && ds & HTDS_PES)
	295	er &= ~(HTER_CSITM\|HTER_CORCRC);
	296	if (er&HTER_HARD \|\|
0deaf016 BJ	297	mbs&MBAEBITS \|\| (ds&HTDS_MOL) == 0 \|\|
0deaf016 BJ	298	er && ++mi->mi_tab.b_errcnt >= 7) {
fcc37d29 BJ	299	if ((ds & HTDS_MOL) == 0 && sc->sc_openf > 0)
fcc37d29 BJ	300	sc->sc_openf = -1;
89bd2f01 BJ	301	printf("tu%d: hard error bn%d mbasr=%b er=%b\n",
89bd2f01 BJ	302	TUUNIT(bp->b_dev), bp->b_blkno,
fcc37d29 BJ	303	mbasr, mbasr_bits,
fcc37d29 BJ	304	MASKREG(htaddr->hter), HTER_BITS);
786dff00	305	bp->b_flags \|= B_ERROR;
fcc37d29	306	return (MBD_DONE);
786dff00	307	}
fcc37d29 BJ	308	if (er)
fcc37d29 BJ	309	return (MBD_RETRY);
786dff00	310	}
fcc37d29 BJ	311	bp->b_resid = 0;
	312	if (bp->b_flags & B_READ)
	313	if (ds&HTDS_TM) { /* must be a read, right? */
	314	bp->b_resid = bp->b_bcount;
	315	sc->sc_nxrec = dbtofsb(bp->b_blkno);
	316	} else if(bp->b_bcount > MASKREG(htaddr->htfc))
	317	bp->b_resid = bp->b_bcount - MASKREG(htaddr->htfc);
	318	return (MBD_DONE);
	319	}
786dff00	320
fcc37d29 BJ	321	/*
	322	* non-data-transfer interrupt
	323	*/
	324	htndtint(mi)
89bd2f01	325	register struct mba_device *mi;
fcc37d29 BJ	326	{
	327	register struct htdevice htaddr = (struct htdevice )mi->mi_drv;
	328	register struct buf *bp = mi->mi_tab.b_actf;
	329	register struct ht_softc *sc;
	330	int er, ds, fc;
786dff00	331
89bd2f01 BJ	332	if (bp == 0)
	333	return (MBN_SKIP);
	334	sc = &ht_softc[TUUNIT(bp->b_dev)];
fcc37d29 BJ	335	ds = sc->sc_dsreg = MASKREG(htaddr->htds);
fcc37d29 BJ	336	er = sc->sc_erreg = MASKREG(htaddr->hter);
0deaf016 BJ	337	fc = sc->sc_resid = MASKREG(htaddr->htfc);
0deaf016 BJ	338	if (sc->sc_erreg) {
fcc37d29	339	htaddr->htcs1 = HT_DCLR\|HT_GO;
0deaf016 BJ	340	mbclrattn(mi);
0deaf016 BJ	341	}
89bd2f01 BJ	342	if (sc->sc_flags&H_REWIND) {
	343	sc->sc_flags &= ~H_REWIND;
	344	return (MBN_CONT);
	345	}
	346	if (bp == &chtbuf[TUUNIT(bp->b_dev)]) {
fcc37d29 BJ	347	if (bp->b_command == HT_REWOFFL)
	348	/* offline is on purpose; don't do anything special */
	349	ds \|= HTDS_MOL;
	350	else if (bp->b_resid == HT_SREV &&
	351	er == (HTER_NEF\|HTER_FCE) &&
	352	ds&HTDS_BOT && bp->b_bcount == INF)
	353	er &= ~HTER_NEF;
	354	er &= ~HTER_FCE;
	355	if (er == 0)
	356	ds &= ~HTDS_ERR;
	357	}
	358	if ((ds & (HTDS_ERR\|HTDS_MOL)) != HTDS_MOL) {
	359	if ((ds & HTDS_MOL) == 0 && sc->sc_openf > 0)
	360	sc->sc_openf = -1;
89bd2f01 BJ	361	printf("tu%d: hard error bn%d er=%b ds=%b\n",
89bd2f01 BJ	362	TUUNIT(bp->b_dev), bp->b_blkno,
fcc37d29 BJ	363	sc->sc_erreg, HTER_BITS, sc->sc_dsreg, HTDS_BITS);
	364	bp->b_flags \|= B_ERROR;
	365	return (MBN_DONE);
786dff00	366	}
89bd2f01	367	if (bp == &chtbuf[TUUNIT(bp->b_dev)]) {
fcc37d29 BJ	368	if (sc->sc_flags & H_REWIND)
	369	return (ds & HTDS_BOT ? MBN_DONE : MBN_RETRY);
	370	bp->b_resid = -sc->sc_resid;
	371	return (MBN_DONE);
	372	}
	373	if (ds & HTDS_TM)
	374	if (sc->sc_blkno > dbtofsb(bp->b_blkno)) {/* reversing */
	375	sc->sc_nxrec = dbtofsb(bp->b_blkno) - fc;
	376	sc->sc_blkno = sc->sc_nxrec;
	377	} else { /* spacing forward */
	378	sc->sc_blkno = dbtofsb(bp->b_blkno) + fc;
	379	sc->sc_nxrec = sc->sc_blkno - 1;
	380	}
	381	else
	382	sc->sc_blkno = dbtofsb(bp->b_blkno);
	383	return (MBN_RETRY);
786dff00 BJ	384	}
	385
	386	htread(dev)
fcc37d29	387	dev_t dev;
786dff00	388	{
fcc37d29	389
786dff00	390	htphys(dev);
fcc37d29 BJ	391	if (u.u_error)
	392	return;
	393	physio(htstrategy, &rhtbuf[HTUNIT(dev)], dev, B_READ, minphys);
786dff00 BJ	394	}
	395
	396	htwrite(dev)
	397	{
fcc37d29	398
786dff00	399	htphys(dev);
fcc37d29 BJ	400	if (u.u_error)
	401	return;
	402	physio(htstrategy, &rhtbuf[HTUNIT(dev)], dev, B_WRITE, minphys);
786dff00 BJ	403	}
	404
	405	htphys(dev)
fcc37d29	406	dev_t dev;
786dff00	407	{
fcc37d29 BJ	408	register int unit;
fcc37d29 BJ	409	register struct ht_softc *sc;
786dff00 BJ	410	daddr_t a;
786dff00 BJ	411
fcc37d29 BJ	412	unit = HTUNIT(dev);
	413	if (unit >= NHT) {
	414	u.u_error = ENXIO;
	415	return;
786dff00	416	}
fcc37d29 BJ	417	a = u.u_offset >> 9;
	418	sc = &ht_softc[unit];
	419	sc->sc_blkno = dbtofsb(a);
	420	sc->sc_nxrec = dbtofsb(a)+1;
786dff00	421	}
f0a3ddbd	422
fcc37d29 BJ	423	/ARGSUSED/
	424	htioctl(dev, cmd, addr, flag)
	425	dev_t dev;
	426	int cmd;
	427	caddr_t addr;
	428	int flag;
	429	{
	430	register unit = HTUNIT(dev);
	431	register struct ht_softc *sc = &ht_softc[unit];
	432	register struct buf *bp = &chtbuf[unit];
	433	register callcount;
	434	int fcount;
	435	struct mtop mtop;
	436	struct mtget mtget;
	437	/* we depend of the values and order of the MT codes here */
	438	static htops[] =
	439	{HT_WEOF,HT_SFORW,HT_SREV,HT_SFORW,HT_SREV,HT_REW,HT_REWOFFL,HT_SENSE};
	440
	441	switch (cmd) {
	442	case MTIOCTOP: /* tape operation */
	443	if (copyin((caddr_t)addr, (caddr_t)&mtop, sizeof(mtop))) {
	444	u.u_error = EFAULT;
	445	return;
	446	}
	447	switch(mtop.mt_op) {
	448	case MTWEOF:
	449	callcount = mtop.mt_count;
	450	fcount = 1;
	451	break;
	452	case MTFSF: case MTBSF:
	453	callcount = mtop.mt_count;
	454	fcount = INF;
	455	break;
	456	case MTFSR: case MTBSR:
	457	callcount = 1;
	458	fcount = mtop.mt_count;
	459	break;
	460	case MTREW: case MTOFFL:
	461	callcount = 1;
	462	fcount = 1;
	463	break;
	464	default:
	465	u.u_error = ENXIO;
	466	return;
	467	}
	468	if (callcount <= 0 \|\| fcount <= 0) {
	469	u.u_error = ENXIO;
	470	return;
	471	}
	472	while (--callcount >= 0) {
	473	htcommand(dev, htops[mtop.mt_op], fcount);
	474	if ((mtop.mt_op == MTFSR \|\| mtop.mt_op == MTBSR) &&
	475	bp->b_resid) {
	476	u.u_error = EIO;
	477	break;
	478	}
	479	if ((chtbuf[HTUNIT(bp->b_dev)].b_flags&B_ERROR) \|\|
	480	sc->sc_dsreg&HTDS_BOT)
	481	break;
	482	}
	483	geterror(bp);
	484	return;
	485	case MTIOCGET:
	486	mtget.mt_dsreg = sc->sc_dsreg;
487	mtget.mt_erreg = sc->sc_erreg;
488	mtget.mt_resid = sc->sc_resid;
489	if (copyout((caddr_t)&mtget, addr, sizeof(mtget)))
490	u.u_error = EFAULT;
491	return;
492	default:
493	u.u_error = ENXIO;
494	}
495	}
f0a3ddbd BJ	496
	497	#define DBSIZE 20
	498
fcc37d29	499	htdump()
f0a3ddbd	500	{
89bd2f01	501	register struct mba_device *mi;
fcc37d29 BJ	502	register struct mba_regs *mp;
	503	register struct htdevice *htaddr;
	504	int blk, num;
	505	int start;
	506
	507	start = 0;
	508	num = maxfree;
	509	#define phys(a,b) ((b)((int)(a)&0x7fffffff))
	510	if (htinfo[0] == 0)
	511	return (ENXIO);
89bd2f01	512	mi = phys(htinfo[0], struct mba_device *);
fcc37d29 BJ	513	mp = phys(mi->mi_hd, struct mba_hd *)->mh_physmba;
fcc37d29 BJ	514	#if VAX780
0deaf016 BJ	515	if (cpu == VAX780)
	516	mbainit(mp);
	517	#endif
fcc37d29 BJ	518	htaddr = (struct htdevice *)&mp->mba_drv[mi->mi_drive];
	519	htaddr->httc = HTTC_PDP11\|HTTC_1600BPI;
	520	htaddr->htcs1 = HT_DCLR\|HT_GO;
f0a3ddbd BJ	521	while (num > 0) {
f0a3ddbd BJ	522	blk = num > DBSIZE ? DBSIZE : num;
fcc37d29 BJ	523	htdwrite(start, blk, htaddr, mp);
fcc37d29 BJ	524	start += blk;
f0a3ddbd BJ	525	num -= blk;
f0a3ddbd BJ	526	}
fcc37d29 BJ	527	htwait(htaddr);
	528	htaddr->htcs1 = HT_REW\|HT_GO;
	529	hteof(htaddr);
	530	hteof(htaddr);
f0a3ddbd BJ	531	}
f0a3ddbd BJ	532
fcc37d29 BJ	533	htdwrite(dbuf, num, htaddr, mp)
	534	register dbuf, num;
	535	register struct htdevice *htaddr;
	536	struct mba_regs *mp;
f0a3ddbd	537	{
fcc37d29	538	register struct pte *io;
f0a3ddbd BJ	539	register int i;
f0a3ddbd BJ	540
fcc37d29 BJ	541	htwait(htaddr);
fcc37d29 BJ	542	io = mp->mba_map;
f0a3ddbd	543	for (i = 0; i < num; i++)
fcc37d29 BJ	544	(int )io++ = dbuf++ \| PG_V;
	545	htaddr->htfc = -(num*NBPG);
	546	mp->mba_sr = -1;
	547	mp->mba_bcr = -(num*NBPG);
	548	mp->mba_var = 0;
	549	htaddr->htcs1 = HT_WCOM\|HT_GO;
f0a3ddbd BJ	550	}
f0a3ddbd BJ	551
fcc37d29 BJ	552	htwait(htaddr)
fcc37d29 BJ	553	struct htdevice *htaddr;
f0a3ddbd BJ	554	{
	555	register s;
	556
	557	do
fcc37d29 BJ	558	s = htaddr->htds;
fcc37d29 BJ	559	while ((s & HTDS_DRY) == 0);
f0a3ddbd BJ	560	}
f0a3ddbd BJ	561
fcc37d29 BJ	562	hteof(htaddr)
fcc37d29 BJ	563	struct htdevice *htaddr;
f0a3ddbd BJ	564	{
f0a3ddbd BJ	565
fcc37d29 BJ	566	htwait(htaddr);
fcc37d29 BJ	567	htaddr->htcs1 = HT_WEOF\|HT_GO;
f0a3ddbd	568	}
a5cc519e	569	#endif