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1 | /*- |
2 | * Copyright (c) 1990 The Regents of the University of California. | |
3 | * All rights reserved. | |
4 | * | |
5 | * This code is derived from software contributed to Berkeley by | |
6 | * William Jolitz. | |
7 | * | |
8 | * Redistribution and use in source and binary forms, with or without | |
9 | * modification, are permitted provided that the following conditions | |
10 | * are met: | |
11 | * 1. Redistributions of source code must retain the above copyright | |
12 | * notice, this list of conditions and the following disclaimer. | |
13 | * 2. Redistributions in binary form must reproduce the above copyright | |
14 | * notice, this list of conditions and the following disclaimer in the | |
15 | * documentation and/or other materials provided with the distribution. | |
16 | * 3. All advertising materials mentioning features or use of this software | |
17 | * must display the following acknowledgement: | |
18 | * This product includes software developed by the University of | |
19 | * California, Berkeley and its contributors. | |
20 | * 4. Neither the name of the University nor the names of its contributors | |
21 | * may be used to endorse or promote products derived from this software | |
22 | * without specific prior written permission. | |
23 | * | |
24 | * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND | |
25 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
27 | * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE | |
28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS | |
30 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | |
31 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT | |
32 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY | |
33 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF | |
34 | * SUCH DAMAGE. | |
35 | * | |
36 | * @(#)icu.h 5.6 (Berkeley) 5/9/91 | |
37 | */ | |
38 | ||
39 | /* | |
40 | * AT/386 Interrupt Control constants | |
41 | * W. Jolitz 8/89 | |
42 | */ | |
43 | ||
44 | #ifndef __ICU__ | |
45 | #define __ICU__ | |
46 | ||
47 | #ifndef LOCORE | |
48 | ||
49 | /* | |
50 | * Interrupt "level" mechanism variables, masks, and macros | |
51 | */ | |
52 | extern unsigned short imen; /* interrupt mask enable */ | |
53 | extern unsigned short cpl; /* current priority level mask */ | |
54 | ||
55 | extern unsigned short highmask; /* group of interrupts masked with splhigh() */ | |
56 | extern unsigned short ttymask; /* group of interrupts masked with spltty() */ | |
57 | extern unsigned short biomask; /* group of interrupts masked with splbio() */ | |
58 | extern unsigned short netmask; /* group of interrupts masked with splimp() */ | |
59 | ||
60 | #define INTREN(s) imen &= ~(s) | |
61 | #define INTRDIS(s) imen |= (s) | |
62 | #define INTRMASK(msk,s) msk |= (s) | |
63 | ||
64 | #else | |
65 | ||
66 | /* | |
67 | * Macro's for interrupt level priority masks (used in interrupt vector entry) | |
68 | */ | |
69 | ||
70 | /* Mask a group of interrupts atomically */ | |
71 | #define INTR(unit,mask,offst) \ | |
72 | pushl $0 ; \ | |
73 | pushl $ T_ASTFLT ; \ | |
74 | pushal ; \ | |
75 | nop ; \ | |
76 | inb $0x84, %al ; /* ... ASAP */ \ | |
77 | movb $0x20, %al ; /* next, as soon as possible send EOI ... */ \ | |
78 | outb %al, $ IO_ICU1 ; /* ... so in service bit may be cleared ...*/ \ | |
79 | inb $0x84, %al ; /* ... ASAP */ \ | |
80 | movb $0x20, %al ; /* likewise, the other one as well */ \ | |
81 | outb %al,$ IO_ICU2 ; \ | |
82 | inb $0x84,%al ; \ | |
83 | pushl %ds ; /* save our data and extra segments ... */ \ | |
84 | pushl %es ; \ | |
85 | movw $0x10, %ax ; /* ... and reload with kernel's own */ \ | |
86 | movw %ax, %ds ; \ | |
87 | movw %ax, %es ; \ | |
88 | incl _cnt+V_INTR ; /* tally interrupts */ \ | |
89 | incl _isa_intr + offst * 4 ; \ | |
90 | inb $0x84,%al ; \ | |
91 | movzwl _cpl,%eax ; \ | |
92 | pushl %eax ; \ | |
93 | pushl $ unit ; \ | |
94 | orw mask ,%ax ; \ | |
95 | movw %ax,_cpl ; \ | |
96 | orw _imen,%ax ; \ | |
97 | outb %al,$ IO_ICU1+1 ; \ | |
98 | inb $0x84,%al ; \ | |
99 | movb %ah,%al ; \ | |
100 | outb %al,$ IO_ICU2+1 ; \ | |
101 | inb $0x84,%al ; \ | |
102 | sti | |
103 | ||
104 | /* Mask a group of interrupts atomically */ | |
105 | #define INTRSTRAY(unit,mask,offst) \ | |
106 | pushl $0 ; \ | |
107 | pushl $ T_ASTFLT ; \ | |
108 | pushal ; \ | |
109 | nop ; \ | |
110 | inb $0x84, %al ; /* ... ASAP */ \ | |
111 | movb $3, %al ; /* look at ISR ... */ \ | |
112 | outb %al, $ IO_ICU1 ; /* ... ...*/ \ | |
113 | inb $0x84, %al ; /* ... ASAP */ \ | |
114 | movb $3, %al ; /* look at ISR ... */ \ | |
115 | outb %al, $ IO_ICU2 ; /* ... ...*/ \ | |
116 | inb $0x84, %al ; /* ... ASAP */ \ | |
117 | inb $ IO_ICU1, %al ; /* grab ISR */ \ | |
118 | movb %al, %dl ; /* grab ISR */ \ | |
119 | inb $0x84, %al ; /* ... ASAP */ \ | |
120 | movb $2, %al ; /* back to look at IRR ... */ \ | |
121 | outb %al, $ IO_ICU1 ; /* ... ...*/ \ | |
122 | inb $0x84, %al ; /* ... ASAP */ \ | |
123 | movb $2, %al ; /* back to look at IRR ... */ \ | |
124 | outb %al, $ IO_ICU2 ; /* ... ...*/ \ | |
125 | inb $0x84, %al ; /* ... ASAP */ \ | |
126 | inb $ IO_ICU2, %al ; /* grab ISR */ \ | |
127 | movb %al, %dh ; /* grab ISR */ \ | |
128 | inb $0x84, %al ; /* ... ASAP */ \ | |
129 | movb $0x20, %al ; /* next, as soon as possible send EOI ... */ \ | |
130 | outb %al, $ IO_ICU1 ; /* ... so in service bit may be cleared ...*/ \ | |
131 | inb $0x84, %al ; /* ... ASAP */ \ | |
132 | movb $0x20, %al ; /* likewise, the other one as well */ \ | |
133 | outb %al,$ IO_ICU2 ; \ | |
134 | inb $0x84,%al ; \ | |
135 | pushl %ds ; /* save our data and extra segments ... */ \ | |
136 | pushl %es ; \ | |
137 | movw $0x10, %ax ; /* ... and reload with kernel's own */ \ | |
138 | movw %ax, %ds ; \ | |
139 | movw %ax, %es ; \ | |
140 | inb $0x84,%al ; \ | |
141 | movzwl _cpl,%eax ; \ | |
142 | pushl %eax ; \ | |
143 | movzwl %dx,%eax ; \ | |
144 | shll $8,%eax ; \ | |
145 | movb $ unit , %al ; \ | |
146 | pushl %eax ; \ | |
147 | orw mask ,%ax ; \ | |
148 | movw %ax,_cpl ; \ | |
149 | orw _imen,%ax ; \ | |
150 | outb %al,$ IO_ICU1+1 ; \ | |
151 | inb $0x84,%al ; \ | |
152 | movb %ah,%al ; \ | |
153 | outb %al,$ IO_ICU2+1 ; \ | |
154 | inb $0x84,%al ; \ | |
155 | sti | |
156 | ||
157 | /* Interrupt vector exit macros */ | |
158 | ||
159 | /* First eight interrupts (ICU1) */ | |
160 | #define INTREXIT1 \ | |
161 | jmp doreti | |
162 | ||
163 | /* Second eight interrupts (ICU2) */ | |
164 | #define INTREXIT2 \ | |
165 | jmp doreti | |
166 | ||
167 | #endif | |
168 | ||
169 | /* | |
170 | * Interrupt enable bits -- in order of priority | |
171 | */ | |
172 | #define IRQ0 0x0001 /* highest priority - timer */ | |
173 | #define IRQ1 0x0002 | |
174 | #define IRQ_SLAVE 0x0004 | |
175 | #define IRQ8 0x0100 | |
176 | #define IRQ9 0x0200 | |
177 | #define IRQ2 IRQ9 | |
178 | #define IRQ10 0x0400 | |
179 | #define IRQ11 0x0800 | |
180 | #define IRQ12 0x1000 | |
181 | #define IRQ13 0x2000 | |
182 | #define IRQ14 0x4000 | |
183 | #define IRQ15 0x8000 | |
184 | #define IRQ3 0x0008 | |
185 | #define IRQ4 0x0010 | |
186 | #define IRQ5 0x0020 | |
187 | #define IRQ6 0x0040 | |
188 | #define IRQ7 0x0080 /* lowest - parallel printer */ | |
189 | ||
190 | /* | |
191 | * Interrupt Control offset into Interrupt descriptor table (IDT) | |
192 | */ | |
193 | #define ICU_OFFSET 32 /* 0-31 are processor exceptions */ | |
194 | #define ICU_LEN 16 /* 32-47 are ISA interrupts */ | |
195 | ||
196 | #endif __ICU__ |