[unix-history] / usr / src / sys / vax / if / if_enreg.h

/*	if_enreg.h	4.2	81/11/07	*/

/*
 * Xerox experimental ethernet registers.
 *
 * N.B.: status register and device address are read/write,
 * device address is read-only, rest are WRITE ONLY!
 */
struct endevice {
	short	en_owc;		/* output word count (10 bits) */
	short	en_oba;		/* output buffer address */
	short	en_ostat;	/* output control and status */
	short	en_odelay;	/* output start delay, 25usec units  */
	short	en_iwc;		/* input word count */
	short	en_iba;		/* input buffer address */
	short	en_istat;	/* input csr */
	short	en_addr;	/* ~device address (low 8 bits) */
};

/*
 * Control and status bits.
 */
#define EN_IERROR	0x8000		/* CRC error, buf ovflo or overrun */
#define	EN_OERROR	0x8000		/* collision or output underrun */
#define EN_OPDONE	0x0080		/* previous operation completed */
#define EN_IEN		0x0040		/* enable interrupt when DONE */
#define	EN_PROMISCUOUS	0x0002		/* promiscuous, input any packet */
#define EN_GO		0x0001		/* start op bit */

#define	EN_BITS	"\10\20ERR\10OPDONE\7IEN\2PROM\1GO"

#define	spl_enet()	spl5()
Commit	Line	Data
d996953a	1	/* if_enreg.h 4.2 81/11/07 */
2de6e6d5 BJ	2
	3	/*
	4	* Xerox experimental ethernet registers.
	5	*
	6	* N.B.: status register and device address are read/write,
	7	* device address is read-only, rest are WRITE ONLY!
	8	*/
	9	struct endevice {
	10	short en_owc; /* output word count (10 bits) */
	11	short en_oba; /* output buffer address */
	12	short en_ostat; /* output control and status */
	13	short en_odelay; /* output start delay, 25usec units */
	14	short en_iwc; /* input word count */
	15	short en_iba; /* input buffer address */
	16	short en_istat; /* input csr */
	17	short en_addr; /* ~device address (low 8 bits) */
	18	};
	19
	20	/*
	21	* Control and status bits.
	22	*/
	23	#define EN_IERROR 0x8000 /* CRC error, buf ovflo or overrun */
	24	#define EN_OERROR 0x8000 /* collision or output underrun */
	25	#define EN_OPDONE 0x0080 /* previous operation completed */
	26	#define EN_IEN 0x0040 /* enable interrupt when DONE */
d996953a	27	#define EN_PROMISCUOUS 0x0002 /* promiscuous, input any packet */
2de6e6d5 BJ	28	#define EN_GO 0x0001 /* start op bit */
	29
	30	#define EN_BITS "\10\20ERR\10OPDONE\7IEN\2PROM\1GO"
	31
	32	#define spl_enet() spl5()