[unix-history] / usr / src / sys / hp300 / include / cpu.h

/*
 * Copyright (c) 1988 University of Utah.
 * Copyright (c) 1982, 1990 The Regents of the University of California.
 * All rights reserved.
 *
 * This code is derived from software contributed to Berkeley by
 * the Systems Programming Group of the University of Utah Computer
 * Science Department.
 *
 * %sccs.include.redist.c%
 *
 * from: Utah $Hdr: cpu.h 1.16 91/03/25$
 *
 *	@(#)cpu.h	7.13 (Berkeley) %G%
 */

/*
 * Exported definitions unique to hp300/68k cpu support.
 */

/*
 * definitions of cpu-dependent requirements
 * referenced in generic code
 */
#define	COPY_SIGCODE		/* copy sigcode above user stack in exec */

#define	cpu_exec(p)	/* nothing */
#define	cpu_wait(p)	/* nothing */
#define cpu_setstack(p, ap) \
	(p)->p_md.md_regs[SP] = ap

/*
 * Arguments to hardclock and gatherstats encapsulate the previous
 * machine state in an opaque clockframe.  One the hp300, we use
 * what the hardware pushes on an interrupt (frame format 0).
 */
struct clockframe {
	u_short	sr;		/* sr at time of interrupt */
	u_long	pc;		/* pc at time of interrupt */
	u_short	vo;		/* vector offset (4-word frame) */
};

#define	CLKF_USERMODE(framep)	(((framep)->sr & PSL_S) == 0)
#define	CLKF_BASEPRI(framep)	(((framep)->sr & PSL_IPL) == 0)
#define	CLKF_PC(framep)		((framep)->pc)
#if 0
/* We would like to do it this way... */
#define	CLKF_INTR(framep)	(((framep)->sr & PSL_M) == 0)
#else
/* but until we start using PSL_M, we have to do this instead */
#define	CLKF_INTR(framep)	(0)	/* XXX */
#endif


/*
 * Preempt the current process if in interrupt from user mode,
 * or after the current trap/syscall if in system mode.
 */
#define	need_resched()	{ want_resched++; aston(); }

/*
 * Give a profiling tick to the current process when the user profiling
 * buffer pages are invalid.  On the hp300, request an ast to send us
 * through trap, marking the proc as needing a profiling tick.
 */
#define	need_proftick(p)	{ (p)->p_flag |= SOWEUPC; aston(); }

/*
 * Notify the current process (p) that it has a signal pending,
 * process as soon as possible.
 */
#define	signotify(p)	aston()

#define aston() (astpending++)

int	astpending;		/* need to trap before returning to user mode */
int	want_resched;		/* resched() was called */


/*
 * simulated software interrupt register
 */
extern unsigned char ssir;

#define SIR_NET		0x1
#define SIR_CLOCK	0x2

#define siroff(x)	ssir &= ~(x)
#define setsoftnet()	ssir |= SIR_NET
#define setsoftclock()	ssir |= SIR_CLOCK


/*
 * The rest of this should probably be moved to ../hp300/hp300cpu.h,
 * although some of it could probably be put into generic 68k headers.
 */

/* values for machineid */
#define	HP_320		0	/* 16Mhz 68020+HP MMU+16K external cache */
#define	HP_330		1	/* 16Mhz 68020+68851 MMU */
#define	HP_350		2	/* 25Mhz 68020+HP MMU+32K external cache */
#define	HP_360		3	/* 25Mhz 68030 */
#define	HP_370		4	/* 33Mhz 68030+64K external cache */
#define	HP_340		5	/* 16Mhz 68030 */
#define	HP_375		6	/* 50Mhz 68030+32K external cache */
#define	HP_380		7	/* 25Mhz 68040 */
#define HP_433		8	/* 33Mhz 68040 */

/* values for mmutype (assigned for quick testing) */
#define	MMU_68040	-2	/* 68040 on-chip MMU */
#define	MMU_68030	-1	/* 68030 on-chip subset of 68851 */
#define	MMU_HP		0	/* HP proprietary */
#define	MMU_68851	1	/* Motorola 68851 */

/* values for ectype */
#define	EC_PHYS		-1	/* external physical address cache */
#define	EC_NONE		0	/* no external cache */
#define	EC_VIRT		1	/* external virtual address cache */

/* values for cpuspeed (not really related to clock speed due to caches) */
#define	MHZ_8		1
#define	MHZ_16		2
#define	MHZ_25		3
#define	MHZ_33		4
#define	MHZ_50		6

#ifdef KERNEL
extern	int machineid, mmutype, ectype;
extern	char *intiobase, *intiolimit;

/* what is this supposed to do? i.e. how is it different than startrtclock? */
#define	enablertclock()

#endif

/* physical memory sections */
#define	ROMBASE		(0x00000000)
#define	INTIOBASE	(0x00400000)
#define	INTIOTOP	(0x00600000)
#define	EXTIOBASE	(0x00600000)
#define	EXTIOTOP	(0x20000000)
#define	MAXADDR		(0xFFFFF000)

/*
 * Internal IO space:
 *
 * Ranges from 0x400000 to 0x600000 (IIOMAPSIZE).
 *
 * Internal IO space is mapped in the kernel from ``intiobase'' to
 * ``intiolimit'' (defined in locore.s).  Since it is always mapped,
 * conversion between physical and kernel virtual addresses is easy.
 */
#define	ISIIOVA(va) \
	((char *)(va) >= intiobase && (char *)(va) < intiolimit)
#define	IIOV(pa)	((int)(pa)-INTIOBASE+(int)intiobase)
#define	IIOP(va)	((int)(va)-(int)intiobase+INTIOBASE)
#define	IIOPOFF(pa)	((int)(pa)-INTIOBASE)
#define	IIOMAPSIZE	btoc(INTIOTOP-INTIOBASE)	/* 2mb */

/*
 * External IO space:
 *
 * DIO ranges from select codes 0-63 at physical addresses given by:
 *	0x600000 + (sc - 32) * 0x10000
 * DIO cards are addressed in the range 0-31 [0x600000-0x800000) for
 * their control space and the remaining areas, [0x200000-0x400000) and
 * [0x800000-0x1000000), are for additional space required by a card;
 * e.g. a display framebuffer.
 *
 * DIO-II ranges from select codes 132-255 at physical addresses given by:
 *	0x1000000 + (sc - 132) * 0x400000
 * The address range of DIO-II space is thus [0x1000000-0x20000000).
 *
 * DIO/DIO-II space is too large to map in its entirety, instead devices
 * are mapped into kernel virtual address space allocated from a range
 * of EIOMAPSIZE pages (vmparam.h) starting at ``extiobase''.
 */
#define	DIOBASE		(0x600000)
#define	DIOTOP		(0x1000000)
#define	DIOCSIZE	(0x10000)
#define	DIOIIBASE	(0x01000000)
#define	DIOIITOP	(0x20000000)
#define	DIOIICSIZE	(0x00400000)

/*
 * HP MMU
 */
#define	MMUBASE		IIOPOFF(0x5F4000)
#define	MMUSSTP		0x0
#define	MMUUSTP		0x4
#define	MMUTBINVAL	0x8
#define	MMUSTAT		0xC
#define	MMUCMD		MMUSTAT

#define	MMU_UMEN	0x0001	/* enable user mapping */
#define	MMU_SMEN	0x0002	/* enable supervisor mapping */
#define	MMU_CEN		0x0004	/* enable data cache */
#define	MMU_BERR	0x0008	/* bus error */
#define	MMU_IEN		0x0020	/* enable instruction cache */
#define	MMU_FPE		0x0040	/* enable 68881 FP coprocessor */
#define	MMU_WPF		0x2000	/* write protect fault */
#define	MMU_PF		0x4000	/* page fault */
#define	MMU_PTF		0x8000	/* page table fault */

#define	MMU_FAULT	(MMU_PTF|MMU_PF|MMU_WPF|MMU_BERR)
#define	MMU_ENAB	(MMU_UMEN|MMU_SMEN|MMU_IEN|MMU_FPE)

/*
 * 68851 and 68030 MMU
 */
#define	PMMU_LVLMASK	0x0007
#define	PMMU_INV	0x0400
#define	PMMU_WP		0x0800
#define	PMMU_ALV	0x1000
#define	PMMU_SO		0x2000
#define	PMMU_LV		0x4000
#define	PMMU_BE		0x8000
#define	PMMU_FAULT	(PMMU_WP|PMMU_INV)

/*
 * 68040 MMU
 */
#define	MMU4_RES	0x001
#define	MMU4_TTR	0x002
#define	MMU4_WP		0x004
#define	MMU4_MOD	0x010
#define	MMU4_CMMASK	0x060
#define	MMU4_SUP	0x080
#define	MMU4_U0		0x100
#define	MMU4_U1		0x200
#define	MMU4_GLB	0x400
#define	MMU4_BE		0x800

/* 680X0 function codes */
#define	FC_USERD	1	/* user data space */
#define	FC_USERP	2	/* user program space */
#define	FC_PURGE	3	/* HPMMU: clear TLB entries */
#define	FC_SUPERD	5	/* supervisor data space */
#define	FC_SUPERP	6	/* supervisor program space */
#define	FC_CPU		7	/* CPU space */

/* fields in the 68020 cache control register */
#define	IC_ENABLE	0x0001	/* enable instruction cache */
#define	IC_FREEZE	0x0002	/* freeze instruction cache */
#define	IC_CE		0x0004	/* clear instruction cache entry */
#define	IC_CLR		0x0008	/* clear entire instruction cache */

/* additional fields in the 68030 cache control register */
#define	IC_BE		0x0010	/* instruction burst enable */
#define	DC_ENABLE	0x0100	/* data cache enable */
#define	DC_FREEZE	0x0200	/* data cache freeze */
#define	DC_CE		0x0400	/* clear data cache entry */
#define	DC_CLR		0x0800	/* clear entire data cache */
#define	DC_BE		0x1000	/* data burst enable */
#define	DC_WA		0x2000	/* write allocate */

#define	CACHE_ON	(DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE)
#define	CACHE_OFF	(DC_CLR|IC_CLR)
#define	CACHE_CLR	(CACHE_ON)
#define	IC_CLEAR	(DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE)
#define	DC_CLEAR	(DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE)

/* 68040 cache control register */
#define	IC4_ENABLE	0x8000		/* instruction cache enable bit */
#define	DC4_ENABLE	0x80000000	/* data cache enable bit */

#define	CACHE4_ON	(IC4_ENABLE|DC4_ENABLE)
#define	CACHE4_OFF	(0)
Commit	Line	Data
88a7e859 KM	1	/*
	2	* Copyright (c) 1988 University of Utah.
	3	* Copyright (c) 1982, 1990 The Regents of the University of California.
	4	* All rights reserved.
	5	*
	6	* This code is derived from software contributed to Berkeley by
	7	* the Systems Programming Group of the University of Utah Computer
	8	* Science Department.
	9	*
	10	* %sccs.include.redist.c%
	11	*
9e153d67	12	* from: Utah $Hdr: cpu.h 1.16 91/03/25$
88a7e859	13	*
98967f47	14	* @(#)cpu.h 7.13 (Berkeley) %G%
ba327c15 MK	15	*/
ba327c15 MK	16
ba327c15 MK	17	/*
	18	* Exported definitions unique to hp300/68k cpu support.
	19	*/
	20
	21	/*
	22	* definitions of cpu-dependent requirements
	23	* referenced in generic code
	24	*/
	25	#define COPY_SIGCODE /* copy sigcode above user stack in exec */
	26
ba327c15	27	#define cpu_exec(p) /* nothing */
54ba99e8	28	#define cpu_wait(p) /* nothing */
ec183d9e KM	29	#define cpu_setstack(p, ap) \
ec183d9e KM	30	(p)->p_md.md_regs[SP] = ap
ba327c15 MK	31
ba327c15 MK	32	/*
e19239c3 CT	33	* Arguments to hardclock and gatherstats encapsulate the previous
e19239c3 CT	34	* machine state in an opaque clockframe. One the hp300, we use
98967f47	35	* what the hardware pushes on an interrupt (frame format 0).
ba327c15	36	*/
cf8f54d4	37	struct clockframe {
cf8f54d4 CT	38	u_short sr; /* sr at time of interrupt */
	39	u_long pc; /* pc at time of interrupt */
	40	u_short vo; /* vector offset (4-word frame) */
	41	};
ba327c15	42
cf8f54d4 CT	43	#define CLKF_USERMODE(framep) (((framep)->sr & PSL_S) == 0)
cf8f54d4 CT	44	#define CLKF_BASEPRI(framep) (((framep)->sr & PSL_IPL) == 0)
ba327c15	45	#define CLKF_PC(framep) ((framep)->pc)
cf8f54d4 CT	46	#if 0
	47	/* We would like to do it this way... */
	48	#define CLKF_INTR(framep) (((framep)->sr & PSL_M) == 0)
	49	#else
	50	/* but until we start using PSL_M, we have to do this instead */
	51	#define CLKF_INTR(framep) (0) /* XXX */
	52	#endif
ba327c15 MK	53
	54
	55	/*
	56	* Preempt the current process if in interrupt from user mode,
	57	* or after the current trap/syscall if in system mode.
	58	*/
	59	#define need_resched() { want_resched++; aston(); }
	60
ba327c15	61	/*
cf8f54d4 CT	62	* Give a profiling tick to the current process when the user profiling
	63	* buffer pages are invalid. On the hp300, request an ast to send us
	64	* through trap, marking the proc as needing a profiling tick.
ba327c15	65	*/
cf8f54d4	66	#define need_proftick(p) { (p)->p_flag \|= SOWEUPC; aston(); }
ba327c15	67
600bf028 MK	68	/*
	69	* Notify the current process (p) that it has a signal pending,
	70	* process as soon as possible.
	71	*/
	72	#define signotify(p) aston()
	73
	74	#define aston() (astpending++)
	75
	76	int astpending; /* need to trap before returning to user mode */
ba327c15 MK	77	int want_resched; /* resched() was called */
	78
	79
	80	/*
	81	* simulated software interrupt register
	82	*/
	83	extern unsigned char ssir;
	84
	85	#define SIR_NET 0x1
	86	#define SIR_CLOCK 0x2
	87
	88	#define siroff(x) ssir &= ~(x)
	89	#define setsoftnet() ssir \|= SIR_NET
	90	#define setsoftclock() ssir \|= SIR_CLOCK
	91
	92
	93
	94	/*
	95	* The rest of this should probably be moved to ../hp300/hp300cpu.h,
	96	* although some of it could probably be put into generic 68k headers.
88a7e859 KM	97	*/
	98
	99	/* values for machineid */
4534a638 KM	100	#define HP_320 0 /* 16Mhz 68020+HP MMU+16K external cache */
	101	#define HP_330 1 /* 16Mhz 68020+68851 MMU */
	102	#define HP_350 2 /* 25Mhz 68020+HP MMU+32K external cache */
	103	#define HP_360 3 /* 25Mhz 68030 */
	104	#define HP_370 4 /* 33Mhz 68030+64K external cache */
	105	#define HP_340 5 /* 16Mhz 68030 */
	106	#define HP_375 6 /* 50Mhz 68030+32K external cache */
9acfa6cd	107	#define HP_380 7 /* 25Mhz 68040 */
98967f47	108	#define HP_433 8 /* 33Mhz 68040 */
88a7e859 KM	109
88a7e859 KM	110	/* values for mmutype (assigned for quick testing) */
9acfa6cd	111	#define MMU_68040 -2 /* 68040 on-chip MMU */
4534a638 KM	112	#define MMU_68030 -1 /* 68030 on-chip subset of 68851 */
	113	#define MMU_HP 0 /* HP proprietary */
	114	#define MMU_68851 1 /* Motorola 68851 */
88a7e859 KM	115
88a7e859 KM	116	/* values for ectype */
4534a638 KM	117	#define EC_PHYS -1 /* external physical address cache */
	118	#define EC_NONE 0 /* no external cache */
	119	#define EC_VIRT 1 /* external virtual address cache */
88a7e859 KM	120
88a7e859 KM	121	/* values for cpuspeed (not really related to clock speed due to caches) */
4534a638 KM	122	#define MHZ_8 1
	123	#define MHZ_16 2
	124	#define MHZ_25 3
	125	#define MHZ_33 4
	126	#define MHZ_50 6
88a7e859 KM	127
	128	#ifdef KERNEL
	129	extern int machineid, mmutype, ectype;
9e153d67	130	extern char intiobase, intiolimit;
88a7e859 KM	131
	132	/* what is this supposed to do? i.e. how is it different than startrtclock? */
	133	#define enablertclock()
	134
	135	#endif
	136
	137	/* physical memory sections */
4534a638	138	#define ROMBASE (0x00000000)
9e153d67 MH	139	#define INTIOBASE (0x00400000)
	140	#define INTIOTOP (0x00600000)
	141	#define EXTIOBASE (0x00600000)
	142	#define EXTIOTOP (0x20000000)
4534a638 KM	143	#define MAXADDR (0xFFFFF000)
4534a638 KM	144
9e153d67 MH	145	/*
	146	* Internal IO space:
	147	*
	148	* Ranges from 0x400000 to 0x600000 (IIOMAPSIZE).
	149	*
	150	* Internal IO space is mapped in the kernel from ``intiobase'' to
	151	* ``intiolimit'' (defined in locore.s). Since it is always mapped,
	152	* conversion between physical and kernel virtual addresses is easy.
	153	*/
	154	#define ISIIOVA(va) \
	155	((char )(va) >= intiobase && (char )(va) < intiolimit)
	156	#define IIOV(pa) ((int)(pa)-INTIOBASE+(int)intiobase)
	157	#define IIOP(va) ((int)(va)-(int)intiobase+INTIOBASE)
	158	#define IIOPOFF(pa) ((int)(pa)-INTIOBASE)
	159	#define IIOMAPSIZE btoc(INTIOTOP-INTIOBASE) /* 2mb */
88a7e859	160
9e153d67 MH	161	/*
	162	* External IO space:
	163	*
	164	* DIO ranges from select codes 0-63 at physical addresses given by:
	165	* 0x600000 + (sc - 32) * 0x10000
	166	* DIO cards are addressed in the range 0-31 [0x600000-0x800000) for
	167	* their control space and the remaining areas, [0x200000-0x400000) and
	168	* [0x800000-0x1000000), are for additional space required by a card;
	169	* e.g. a display framebuffer.
	170	*
	171	* DIO-II ranges from select codes 132-255 at physical addresses given by:
	172	* 0x1000000 + (sc - 132) * 0x400000
	173	* The address range of DIO-II space is thus [0x1000000-0x20000000).
	174	*
	175	* DIO/DIO-II space is too large to map in its entirety, instead devices
	176	* are mapped into kernel virtual address space allocated from a range
	177	* of EIOMAPSIZE pages (vmparam.h) starting at ``extiobase''.
	178	*/
	179	#define DIOBASE (0x600000)
	180	#define DIOTOP (0x1000000)
	181	#define DIOCSIZE (0x10000)
4534a638 KM	182	#define DIOIIBASE (0x01000000)
	183	#define DIOIITOP (0x20000000)
	184	#define DIOIICSIZE (0x00400000)
	185
9e153d67 MH	186	/*
	187	* HP MMU
	188	*/
	189	#define MMUBASE IIOPOFF(0x5F4000)
4534a638 KM	190	#define MMUSSTP 0x0
	191	#define MMUUSTP 0x4
	192	#define MMUTBINVAL 0x8
	193	#define MMUSTAT 0xC
88a7e859 KM	194	#define MMUCMD MMUSTAT
88a7e859 KM	195
4534a638 KM	196	#define MMU_UMEN 0x0001 /* enable user mapping */
	197	#define MMU_SMEN 0x0002 /* enable supervisor mapping */
	198	#define MMU_CEN 0x0004 /* enable data cache */
	199	#define MMU_BERR 0x0008 /* bus error */
	200	#define MMU_IEN 0x0020 /* enable instruction cache */
	201	#define MMU_FPE 0x0040 /* enable 68881 FP coprocessor */
	202	#define MMU_WPF 0x2000 /* write protect fault */
	203	#define MMU_PF 0x4000 /* page fault */
	204	#define MMU_PTF 0x8000 /* page table fault */
	205
	206	#define MMU_FAULT (MMU_PTF\|MMU_PF\|MMU_WPF\|MMU_BERR)
	207	#define MMU_ENAB (MMU_UMEN\|MMU_SMEN\|MMU_IEN\|MMU_FPE)
	208
9e153d67 MH	209	/*
	210	* 68851 and 68030 MMU
	211	*/
4534a638 KM	212	#define PMMU_LVLMASK 0x0007
	213	#define PMMU_INV 0x0400
	214	#define PMMU_WP 0x0800
	215	#define PMMU_ALV 0x1000
	216	#define PMMU_SO 0x2000
	217	#define PMMU_LV 0x4000
	218	#define PMMU_BE 0x8000
4534a638 KM	219	#define PMMU_FAULT (PMMU_WP\|PMMU_INV)
4534a638 KM	220
9acfa6cd MH	221	/*
	222	* 68040 MMU
	223	*/
	224	#define MMU4_RES 0x001
	225	#define MMU4_TTR 0x002
	226	#define MMU4_WP 0x004
	227	#define MMU4_MOD 0x010
	228	#define MMU4_CMMASK 0x060
	229	#define MMU4_SUP 0x080
	230	#define MMU4_U0 0x100
	231	#define MMU4_U1 0x200
	232	#define MMU4_GLB 0x400
	233	#define MMU4_BE 0x800
	234
4534a638 KM	235	/* 680X0 function codes */
	236	#define FC_USERD 1 /* user data space */
	237	#define FC_USERP 2 /* user program space */
	238	#define FC_PURGE 3 /* HPMMU: clear TLB entries */
	239	#define FC_SUPERD 5 /* supervisor data space */
	240	#define FC_SUPERP 6 /* supervisor program space */
	241	#define FC_CPU 7 /* CPU space */
88a7e859 KM	242
88a7e859 KM	243	/* fields in the 68020 cache control register */
4534a638 KM	244	#define IC_ENABLE 0x0001 /* enable instruction cache */
	245	#define IC_FREEZE 0x0002 /* freeze instruction cache */
	246	#define IC_CE 0x0004 /* clear instruction cache entry */
	247	#define IC_CLR 0x0008 /* clear entire instruction cache */
88a7e859 KM	248
88a7e859 KM	249	/* additional fields in the 68030 cache control register */
4534a638 KM	250	#define IC_BE 0x0010 /* instruction burst enable */
	251	#define DC_ENABLE 0x0100 /* data cache enable */
	252	#define DC_FREEZE 0x0200 /* data cache freeze */
	253	#define DC_CE 0x0400 /* clear data cache entry */
	254	#define DC_CLR 0x0800 /* clear entire data cache */
	255	#define DC_BE 0x1000 /* data burst enable */
	256	#define DC_WA 0x2000 /* write allocate */
	257
	258	#define CACHE_ON (DC_WA\|DC_BE\|DC_CLR\|DC_ENABLE\|IC_BE\|IC_CLR\|IC_ENABLE)
	259	#define CACHE_OFF (DC_CLR\|IC_CLR)
	260	#define CACHE_CLR (CACHE_ON)
	261	#define IC_CLEAR (DC_WA\|DC_BE\|DC_ENABLE\|IC_BE\|IC_CLR\|IC_ENABLE)
	262	#define DC_CLEAR (DC_WA\|DC_BE\|DC_CLR\|DC_ENABLE\|IC_BE\|IC_ENABLE)
9acfa6cd MH	263
	264	/* 68040 cache control register */
	265	#define IC4_ENABLE 0x8000 /* instruction cache enable bit */
	266	#define DC4_ENABLE 0x80000000 /* data cache enable bit */
	267
	268	#define CACHE4_ON (IC4_ENABLE\|DC4_ENABLE)
	269	#define CACHE4_OFF (0)