[unix-history] / usr / src / sys / tahoe / include / mtpr.h

/*	mtpr.h	1.1	86/01/05	*/
/*	mtpr.h	4.5	82/11/05	*/

/*
 * TAHOE processor register numbers
 */

#define	SBR	0x0		/* system base register */
#define	SLR	0x1		/* system length register */
#define	P0BR	0x2		/* p0 base register */
#define	P0LR	0x3		/* p0 length register */
#define	P1BR	0x4		/* p1 base register */
#define	P1LR	0x5		/* p1 length register */
#define	P2BR	0x6		/* p2 base register */
#define	P2LR	0x7		/* p2 length register */
#define	IPL	0x8 		/* interrupt priority level */
#define	MME  	0x9		/* memory management enable */
#define	TBIA	0xa		/* translation buffer invalidate all */
#define	TBIS	0xb		/* translation buffer invalidate single */
#define DCK	0xc		/* data cache key */
#define CCK	0xd		/* code cache key */
#define	PCBB	0xe		/* process control block base */
#define	ISP	0xf		/* interrupt stack pointer */
#define	SIRR	0x10		/* software interrupt request */
#define	SISR	0x11		/* software interrupt summary */
#define	SCBB	0x12		/* system control block base */
#define	KSP	0x13		/* kernelack pointer */
#define	USP	0x14		/* user stack pointer */
#define CPMDCB	0x15		/* CP master DCM pointer */
#define PACC	0x17		/* purge all code cache */
#define P1DC	0x18		/* purge one data cache */
#define PADC	0x19		/* purge all data cache */
#define HISR	0x1a		/* hardware interrupt summery register */
#define DCR	0x1b		/* diagnostic control register */
#define PDCS	0x1c		/* purge data cache slot */
Commit	Line	Data
c5acbbc5 SL	1	/* mtpr.h 1.1 86/01/05 */
	2	/* mtpr.h 4.5 82/11/05 */
	3
	4	/*
	5	* TAHOE processor register numbers
	6	*/
	7
	8	#define SBR 0x0 /* system base register */
	9	#define SLR 0x1 /* system length register */
	10	#define P0BR 0x2 /* p0 base register */
	11	#define P0LR 0x3 /* p0 length register */
	12	#define P1BR 0x4 /* p1 base register */
	13	#define P1LR 0x5 /* p1 length register */
	14	#define P2BR 0x6 /* p2 base register */
	15	#define P2LR 0x7 /* p2 length register */
	16	#define IPL 0x8 /* interrupt priority level */
	17	#define MME 0x9 /* memory management enable */
	18	#define TBIA 0xa /* translation buffer invalidate all */
	19	#define TBIS 0xb /* translation buffer invalidate single */
	20	#define DCK 0xc /* data cache key */
	21	#define CCK 0xd /* code cache key */
	22	#define PCBB 0xe /* process control block base */
	23	#define ISP 0xf /* interrupt stack pointer */
	24	#define SIRR 0x10 /* software interrupt request */
	25	#define SISR 0x11 /* software interrupt summary */
	26	#define SCBB 0x12 /* system control block base */
	27	#define KSP 0x13 /* kernelack pointer */
	28	#define USP 0x14 /* user stack pointer */
	29	#define CPMDCB 0x15 /* CP master DCM pointer */
	30	#define PACC 0x17 /* purge all code cache */
	31	#define P1DC 0x18 /* purge one data cache */
	32	#define PADC 0x19 /* purge all data cache */
	33	#define HISR 0x1a /* hardware interrupt summery register */
	34	#define DCR 0x1b /* diagnostic control register */
	35	#define PDCS 0x1c /* purge data cache slot */