Commit | Line | Data |
---|---|---|
a0eab615 | 1 | /* uba.c 4.21 %G% */ |
c14fd247 BJ |
2 | |
3 | #include "../h/param.h" | |
3f3a34c3 BJ |
4 | #include "../h/systm.h" |
5 | #include "../h/cpu.h" | |
c14fd247 BJ |
6 | #include "../h/map.h" |
7 | #include "../h/pte.h" | |
c14fd247 | 8 | #include "../h/buf.h" |
b7333467 | 9 | #include "../h/vm.h" |
5ab42896 BJ |
10 | #include "../h/ubareg.h" |
11 | #include "../h/ubavar.h" | |
c14fd247 BJ |
12 | #include "../h/dir.h" |
13 | #include "../h/user.h" | |
14 | #include "../h/proc.h" | |
2e74ef16 | 15 | #include "../h/conf.h" |
868a6a95 | 16 | #include "../h/mtpr.h" |
3f3a34c3 | 17 | #include "../h/nexus.h" |
b7333467 BJ |
18 | #include "../h/dk.h" |
19 | ||
5af3f3f7 BJ |
20 | #if VAX780 |
21 | char ubasr_bits[] = UBASR_BITS; | |
22 | #endif | |
23 | ||
b7333467 BJ |
24 | /* |
25 | * Do transfer on device argument. The controller | |
26 | * and uba involved are implied by the device. | |
27 | * We queue for resource wait in the uba code if necessary. | |
28 | * We return 1 if the transfer was started, 0 if it was not. | |
29 | * If you call this routine with the head of the queue for a | |
30 | * UBA, it will automatically remove the device from the UBA | |
31 | * queue before it returns. If some other device is given | |
32 | * as argument, it will be added to the request queue if the | |
33 | * request cannot be started immediately. This means that | |
34 | * passing a device which is on the queue but not at the head | |
35 | * of the request queue is likely to be a disaster. | |
36 | */ | |
37 | ubago(ui) | |
5ab42896 | 38 | register struct uba_device *ui; |
b7333467 | 39 | { |
5ab42896 | 40 | register struct uba_ctlr *um = ui->ui_mi; |
b7333467 BJ |
41 | register struct uba_hd *uh; |
42 | register int s, unit; | |
43 | ||
44 | uh = &uba_hd[um->um_ubanum]; | |
45 | s = spl6(); | |
28ca05a9 | 46 | if (um->um_driver->ud_xclu && uh->uh_users > 0 || uh->uh_xclu) |
0801d37f | 47 | goto rwait; |
b7333467 BJ |
48 | um->um_ubinfo = ubasetup(um->um_ubanum, um->um_tab.b_actf->b_actf, |
49 | UBA_NEEDBDP|UBA_CANTWAIT); | |
0801d37f BJ |
50 | if (um->um_ubinfo == 0) |
51 | goto rwait; | |
0801d37f | 52 | uh->uh_users++; |
28ca05a9 | 53 | if (um->um_driver->ud_xclu) |
0801d37f | 54 | uh->uh_xclu = 1; |
b7333467 BJ |
55 | splx(s); |
56 | if (ui->ui_dk >= 0) { | |
57 | unit = ui->ui_dk; | |
58 | dk_busy |= 1<<unit; | |
59 | } | |
60 | if (uh->uh_actf == ui) | |
61 | uh->uh_actf = ui->ui_forw; | |
62 | (*um->um_driver->ud_dgo)(um); | |
63 | if (ui->ui_dk >= 0) { | |
64 | dk_xfer[unit]++; | |
65 | dk_wds[unit] += um->um_tab.b_actf->b_bcount>>6; | |
66 | } | |
67 | return (1); | |
0801d37f BJ |
68 | rwait: |
69 | if (uh->uh_actf != ui) { | |
70 | ui->ui_forw = NULL; | |
71 | if (uh->uh_actf == NULL) | |
72 | uh->uh_actf = ui; | |
73 | else | |
74 | uh->uh_actl->ui_forw = ui; | |
75 | uh->uh_actl = ui; | |
76 | } | |
77 | splx(s); | |
78 | return (0); | |
79 | } | |
80 | ||
81 | ubadone(um) | |
5ab42896 | 82 | register struct uba_ctlr *um; |
0801d37f BJ |
83 | { |
84 | register struct uba_hd *uh = &uba_hd[um->um_ubanum]; | |
85 | ||
28ca05a9 | 86 | if (um->um_driver->ud_xclu) |
0801d37f BJ |
87 | uh->uh_xclu = 0; |
88 | uh->uh_users--; | |
0801d37f | 89 | ubarelse(um->um_ubanum, &um->um_ubinfo); |
b7333467 | 90 | } |
c14fd247 BJ |
91 | |
92 | /* | |
3f3a34c3 BJ |
93 | * Allocate and setup UBA map registers, and bdp's |
94 | * Flags says whether bdp is needed, whether the caller can't | |
95 | * wait (e.g. if the caller is at interrupt level). | |
c14fd247 | 96 | * |
b7333467 | 97 | * Return value: |
c14fd247 BJ |
98 | * Bits 0-8 Byte offset |
99 | * Bits 9-17 Start map reg. no. | |
100 | * Bits 18-27 No. mapping reg's | |
101 | * Bits 28-31 BDP no. | |
102 | */ | |
3f3a34c3 BJ |
103 | ubasetup(uban, bp, flags) |
104 | struct buf *bp; | |
c14fd247 | 105 | { |
3f3a34c3 | 106 | register struct uba_hd *uh = &uba_hd[uban]; |
c14fd247 BJ |
107 | register int temp, i; |
108 | int npf, reg, bdp; | |
109 | unsigned v; | |
110 | register struct pte *pte, *io; | |
111 | struct proc *rp; | |
112 | int a, o, ubinfo; | |
113 | ||
114 | v = btop(bp->b_un.b_addr); | |
115 | o = (int)bp->b_un.b_addr & PGOFSET; | |
116 | npf = btoc(bp->b_bcount + o) + 1; | |
117 | a = spl6(); | |
c84ff1f9 | 118 | while ((reg = rmalloc(uh->uh_map, npf)) == 0) { |
3f3a34c3 BJ |
119 | if (flags & UBA_CANTWAIT) |
120 | return (0); | |
121 | uh->uh_mrwant++; | |
122 | sleep((caddr_t)uh->uh_map, PSWP); | |
c14fd247 | 123 | } |
c14fd247 | 124 | bdp = 0; |
3f3a34c3 BJ |
125 | if (flags & UBA_NEEDBDP) { |
126 | while ((bdp = ffs(uh->uh_bdpfree)) == 0) { | |
127 | if (flags & UBA_CANTWAIT) { | |
c84ff1f9 | 128 | rmfree(uh->uh_map, npf, reg); |
3f3a34c3 BJ |
129 | return (0); |
130 | } | |
131 | uh->uh_bdpwant++; | |
132 | sleep((caddr_t)uh->uh_map, PSWP); | |
c14fd247 | 133 | } |
658110d5 | 134 | uh->uh_bdpfree &= ~(1 << (bdp-1)); |
3f3a34c3 | 135 | } |
c14fd247 | 136 | splx(a); |
658110d5 | 137 | reg--; |
c14fd247 | 138 | ubinfo = (bdp << 28) | (npf << 18) | (reg << 9) | o; |
3f3a34c3 | 139 | io = &uh->uh_uba->uba_map[reg]; |
5ab42896 | 140 | temp = (bdp << 21) | UBAMR_MRV; |
c14fd247 BJ |
141 | rp = bp->b_flags&B_DIRTY ? &proc[2] : bp->b_proc; |
142 | if (bdp && (o & 01)) | |
5ab42896 | 143 | temp |= UBAMR_BO; |
c14fd247 BJ |
144 | if (bp->b_flags & B_UAREA) { |
145 | for (i = UPAGES - bp->b_bcount / NBPG; i < UPAGES; i++) { | |
146 | if (rp->p_addr[i].pg_pfnum == 0) | |
147 | panic("uba: zero upage"); | |
148 | *(int *)io++ = rp->p_addr[i].pg_pfnum | temp; | |
149 | } | |
150 | } else if ((bp->b_flags & B_PHYS) == 0) { | |
da1392b6 | 151 | pte = &Sysmap[btop(((int)bp->b_un.b_addr)&0x7fffffff)]; |
c14fd247 | 152 | while (--npf != 0) |
da1392b6 | 153 | *(int *)io++ = pte++->pg_pfnum | temp; |
c14fd247 BJ |
154 | } else { |
155 | if (bp->b_flags & B_PAGET) | |
156 | pte = &Usrptmap[btokmx((struct pte *)bp->b_un.b_addr)]; | |
157 | else | |
158 | pte = vtopte(rp, v); | |
159 | while (--npf != 0) { | |
160 | if (pte->pg_pfnum == 0) | |
161 | panic("uba zero uentry"); | |
162 | *(int *)io++ = pte++->pg_pfnum | temp; | |
163 | } | |
164 | } | |
165 | *(int *)io++ = 0; | |
166 | return (ubinfo); | |
167 | } | |
168 | ||
c14fd247 | 169 | /* |
b7333467 | 170 | * Non buffer setup interface... set up a buffer and call ubasetup. |
c14fd247 | 171 | */ |
3f3a34c3 | 172 | uballoc(uban, addr, bcnt, flags) |
a0eab615 | 173 | int uban; |
c14fd247 | 174 | caddr_t addr; |
a0eab615 | 175 | int bcnt, flags; |
c14fd247 | 176 | { |
89e0f717 | 177 | struct buf ubabuf; |
c14fd247 | 178 | |
c14fd247 BJ |
179 | ubabuf.b_un.b_addr = addr; |
180 | ubabuf.b_flags = B_BUSY; | |
181 | ubabuf.b_bcount = bcnt; | |
89e0f717 | 182 | /* that's all the fields ubasetup() needs */ |
3f3a34c3 | 183 | return (ubasetup(uban, &ubabuf, flags)); |
c14fd247 BJ |
184 | } |
185 | ||
b28deaf8 | 186 | /* |
b7333467 BJ |
187 | * Release resources on uba uban, and then unblock resource waiters. |
188 | * The map register parameter is by value since we need to block | |
189 | * against uba resets on 11/780's. | |
b28deaf8 | 190 | */ |
3f3a34c3 | 191 | ubarelse(uban, amr) |
b28deaf8 | 192 | int *amr; |
c14fd247 | 193 | { |
3f3a34c3 | 194 | register struct uba_hd *uh = &uba_hd[uban]; |
b7333467 | 195 | register int bdp, reg, npf, s; |
b28deaf8 | 196 | int mr; |
c14fd247 | 197 | |
b7333467 BJ |
198 | /* |
199 | * Carefully see if we should release the space, since | |
200 | * it may be released asynchronously at uba reset time. | |
201 | */ | |
202 | s = spl6(); | |
b28deaf8 BJ |
203 | mr = *amr; |
204 | if (mr == 0) { | |
b7333467 BJ |
205 | /* |
206 | * A ubareset() occurred before we got around | |
207 | * to releasing the space... no need to bother. | |
208 | */ | |
209 | splx(s); | |
b28deaf8 BJ |
210 | return; |
211 | } | |
88149598 | 212 | *amr = 0; |
b7333467 | 213 | splx(s); /* let interrupts in, we're safe for a while */ |
c14fd247 BJ |
214 | bdp = (mr >> 28) & 0x0f; |
215 | if (bdp) { | |
27bf6b55 | 216 | switch (cpu) { |
5aa9d5ea RE |
217 | #if VAX780 |
218 | case VAX_780: | |
5ab42896 | 219 | uh->uh_uba->uba_dpr[bdp] |= UBADPR_BNE; |
5aa9d5ea RE |
220 | break; |
221 | #endif | |
222 | #if VAX750 | |
223 | case VAX_750: | |
5ab42896 BJ |
224 | uh->uh_uba->uba_dpr[bdp] |= |
225 | UBADPR_PURGE|UBADPR_NXM|UBADPR_UCE; | |
5aa9d5ea RE |
226 | break; |
227 | #endif | |
228 | } | |
b7333467 | 229 | uh->uh_bdpfree |= 1 << (bdp-1); /* atomic */ |
3f3a34c3 BJ |
230 | if (uh->uh_bdpwant) { |
231 | uh->uh_bdpwant = 0; | |
232 | wakeup((caddr_t)uh->uh_map); | |
c14fd247 BJ |
233 | } |
234 | } | |
b7333467 BJ |
235 | /* |
236 | * Put back the registers in the resource map. | |
237 | * The map code must not be reentered, so we do this | |
238 | * at high ipl. | |
239 | */ | |
c14fd247 BJ |
240 | npf = (mr >> 18) & 0x3ff; |
241 | reg = ((mr >> 9) & 0x1ff) + 1; | |
b7333467 | 242 | s = spl6(); |
c84ff1f9 | 243 | rmfree(uh->uh_map, npf, reg); |
b7333467 BJ |
244 | splx(s); |
245 | ||
246 | /* | |
247 | * Wakeup sleepers for map registers, | |
248 | * and also, if there are processes blocked in dgo(), | |
249 | * give them a chance at the UNIBUS. | |
250 | */ | |
3f3a34c3 BJ |
251 | if (uh->uh_mrwant) { |
252 | uh->uh_mrwant = 0; | |
253 | wakeup((caddr_t)uh->uh_map); | |
c14fd247 | 254 | } |
b7333467 BJ |
255 | while (uh->uh_actf && ubago(uh->uh_actf)) |
256 | ; | |
c14fd247 BJ |
257 | } |
258 | ||
27bf6b55 | 259 | ubapurge(um) |
5ab42896 | 260 | register struct uba_ctlr *um; |
27bf6b55 BJ |
261 | { |
262 | register struct uba_hd *uh = um->um_hd; | |
263 | register int bdp = (um->um_ubinfo >> 28) & 0x0f; | |
264 | ||
265 | switch (cpu) { | |
266 | #if VAX780 | |
267 | case VAX_780: | |
5ab42896 | 268 | uh->uh_uba->uba_dpr[bdp] |= UBADPR_BNE; |
27bf6b55 BJ |
269 | break; |
270 | #endif | |
271 | #if VAX750 | |
272 | case VAX_750: | |
5ab42896 | 273 | uh->uh_uba->uba_dpr[bdp] |= UBADPR_PURGE|UBADPR_NXM|UBADPR_UCE; |
27bf6b55 BJ |
274 | break; |
275 | #endif | |
276 | } | |
277 | } | |
278 | ||
b7333467 BJ |
279 | /* |
280 | * Generate a reset on uba number uban. Then | |
281 | * call each device in the character device table, | |
282 | * giving it a chance to clean up so as to be able to continue. | |
283 | */ | |
3f3a34c3 | 284 | ubareset(uban) |
b7333467 | 285 | int uban; |
2e74ef16 | 286 | { |
2e74ef16 | 287 | register struct cdevsw *cdp; |
a3cb8f60 | 288 | register struct uba_hd *uh = &uba_hd[uban]; |
49c84d3f | 289 | int s; |
2e74ef16 | 290 | |
4ea0bfc4 | 291 | s = spl6(); |
a3cb8f60 BJ |
292 | uh->uh_users = 0; |
293 | uh->uh_zvcnt = 0; | |
294 | uh->uh_xclu = 0; | |
295 | uh->uh_hangcnt = 0; | |
296 | uh->uh_actf = uh->uh_actl = 0; | |
297 | uh->uh_bdpwant = 0; | |
298 | uh->uh_mrwant = 0; | |
299 | wakeup((caddr_t)&uh->uh_bdpwant); | |
300 | wakeup((caddr_t)&uh->uh_mrwant); | |
5ab42896 BJ |
301 | printf("uba%d: reset", uban); |
302 | ubainit(uh->uh_uba); | |
2e74ef16 | 303 | for (cdp = cdevsw; cdp->d_open; cdp++) |
3f3a34c3 | 304 | (*cdp->d_reset)(uban); |
2e74ef16 | 305 | printf("\n"); |
4ea0bfc4 | 306 | splx(s); |
2e74ef16 | 307 | } |
3f3a34c3 | 308 | |
b7333467 BJ |
309 | /* |
310 | * Init a uba. This is called with a pointer | |
311 | * rather than a virtual address since it is called | |
312 | * by code which runs with memory mapping disabled. | |
313 | * In these cases we really don't need the interrupts | |
314 | * enabled, but since we run with ipl high, we don't care | |
315 | * if they are, they will never happen anyways. | |
316 | */ | |
5aa9d5ea RE |
317 | ubainit(uba) |
318 | register struct uba_regs *uba; | |
3f3a34c3 BJ |
319 | { |
320 | ||
5ab42896 BJ |
321 | switch (cpu) { |
322 | #if VAX780 | |
323 | case VAX780: | |
324 | uba->uba_cr = UBACR_ADINIT; | |
325 | uba->uba_cr = UBACR_IFS|UBACR_BRIE|UBACR_USEFIE|UBACR_SUEFIE; | |
326 | while ((uba->uba_cnfgr & UBACNFGR_UBIC) == 0) | |
327 | ; | |
328 | break; | |
329 | #endif | |
330 | #if VAX750 | |
331 | case VAX750: | |
332 | mtpr(IUR, 1); | |
333 | /* give devices time to recover from power fail */ | |
334 | DELAY(5000000); | |
335 | break; | |
336 | #endif | |
337 | } | |
3f3a34c3 BJ |
338 | } |
339 | ||
5ab42896 | 340 | #if VAX780 |
b7333467 BJ |
341 | /* |
342 | * Check to make sure the UNIBUS adaptor is not hung, | |
343 | * with an interrupt in the register to be presented, | |
344 | * but not presenting it for an extended period (5 seconds). | |
345 | */ | |
3f3a34c3 BJ |
346 | unhang() |
347 | { | |
348 | register int uban; | |
349 | ||
350 | for (uban = 0; uban < numuba; uban++) { | |
351 | register struct uba_hd *uh = &uba_hd[uban]; | |
352 | register struct uba_regs *up = uh->uh_uba; | |
353 | ||
354 | if (up->uba_sr == 0) | |
355 | return; | |
356 | uh->uh_hangcnt++; | |
7780575a | 357 | if (uh->uh_hangcnt > 5*hz) { |
3f3a34c3 | 358 | uh->uh_hangcnt = 0; |
5af3f3f7 | 359 | printf("uba%d: hung\n", uban); |
3f3a34c3 BJ |
360 | ubareset(uban); |
361 | } | |
362 | } | |
363 | } | |
364 | ||
b7333467 BJ |
365 | /* |
366 | * This is a timeout routine which decrements the ``i forgot to | |
367 | * interrupt'' counts, on an 11/780. This prevents slowly growing | |
368 | * counts from causing a UBA reset since we are interested only | |
369 | * in hang situations. | |
370 | */ | |
3f3a34c3 BJ |
371 | ubawatch() |
372 | { | |
373 | register struct uba_hd *uh; | |
374 | register int uban; | |
375 | ||
c84ff1f9 BJ |
376 | if (panicstr) |
377 | return; | |
3f3a34c3 BJ |
378 | for (uban = 0; uban < numuba; uban++) { |
379 | uh = &uba_hd[uban]; | |
380 | if (uh->uh_hangcnt) | |
381 | uh->uh_hangcnt--; | |
382 | } | |
383 | } | |
384 | ||
b7333467 BJ |
385 | /* |
386 | * This routine is called by the locore code to | |
387 | * process a UBA error on an 11/780. The arguments are passed | |
388 | * on the stack, and value-result (through some trickery). | |
389 | * In particular, the uvec argument is used for further | |
390 | * uba processing so the result aspect of it is very important. | |
391 | * It must not be declared register. | |
392 | */ | |
5aa9d5ea | 393 | /*ARGSUSED*/ |
3f3a34c3 BJ |
394 | ubaerror(uban, uh, xx, uvec, uba) |
395 | register int uban; | |
396 | register struct uba_hd *uh; | |
397 | int uvec; | |
398 | register struct uba_regs *uba; | |
399 | { | |
400 | register sr, s; | |
401 | ||
402 | if (uvec == 0) { | |
403 | uh->uh_zvcnt++; | |
404 | if (uh->uh_zvcnt > 250000) { | |
5af3f3f7 | 405 | printf("uba%d: too many zero vectors\n"); |
3f3a34c3 BJ |
406 | ubareset(uban); |
407 | } | |
408 | uvec = 0; | |
409 | return; | |
410 | } | |
411 | if (uba->uba_cnfgr & NEX_CFGFLT) { | |
5af3f3f7 BJ |
412 | printf("uba%d: sbi fault sr=%b cnfgr=%b\n", |
413 | uban, uba->uba_sr, ubasr_bits, | |
414 | uba->uba_cnfgr, nexflt_bits); | |
3f3a34c3 BJ |
415 | ubareset(uban); |
416 | uvec = 0; | |
417 | return; | |
418 | } | |
419 | sr = uba->uba_sr; | |
420 | s = spl7(); | |
5af3f3f7 | 421 | printf("uba%d: uba error sr=%x fmer=%x fubar=%o\n", |
7e00c42b | 422 | uban, uba->uba_sr, uba->uba_fmer, 4*uba->uba_fubar); |
3f3a34c3 BJ |
423 | splx(s); |
424 | uba->uba_sr = sr; | |
5ab42896 | 425 | uvec &= UBABRRVR_DIV; |
3f3a34c3 BJ |
426 | return; |
427 | } | |
428 | #endif |