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c49dc82a AF |
1 | /* |
2 | * Copyright (c) 1988 University of Utah. | |
3 | * Copyright (c) 1992 OMRON Corporation. | |
fb98374d KB |
4 | * Copyright (c) 1982, 1990, 1992, 1993 |
5 | * The Regents of the University of California. All rights reserved. | |
c49dc82a AF |
6 | * |
7 | * This code is derived from software contributed to Berkeley by | |
8 | * the Systems Programming Group of the University of Utah Computer | |
9 | * Science Department. | |
10 | * | |
11 | * %sccs.include.redist.c% | |
12 | * | |
13 | * from: Utah $Hdr: cpu.h 1.16 91/03/25$ | |
5ccec412 | 14 | * from: hp300/include/cpu.h 7.14 (Berkeley) 5/20/93 |
c49dc82a | 15 | * |
cf5ef508 | 16 | * @(#)cpu.h 8.2 (Berkeley) %G% |
c49dc82a AF |
17 | */ |
18 | ||
19 | /* | |
c2353cee AF |
20 | * Exported definitions unique to luna/68k cpu support, |
21 | * taken from hp300/68k. | |
c49dc82a AF |
22 | */ |
23 | ||
24 | /* | |
25 | * definitions of cpu-dependent requirements | |
26 | * referenced in generic code | |
27 | */ | |
28 | #define COPY_SIGCODE /* copy sigcode above user stack in exec */ | |
29 | ||
c49dc82a AF |
30 | #define cpu_exec(p) /* nothing */ |
31 | #define cpu_wait(p) /* nothing */ | |
32 | #define cpu_setstack(p, ap) \ | |
33 | (p)->p_md.md_regs[SP] = ap | |
34 | ||
35 | /* | |
c4b4b65a AF |
36 | * Arguments to hardclock and gatherstats encapsulate the previous |
37 | * machine state in an opaque clockframe. One the 68k, we use | |
38 | * what the hardware pushes on an interrupt (but we pad the sr to a | |
39 | * longword boundary). | |
c49dc82a | 40 | */ |
c4b4b65a | 41 | struct clockframe { |
c4b4b65a AF |
42 | u_short sr; /* sr at time of interrupt */ |
43 | u_long pc; /* pc at time of interrupt */ | |
44 | u_short vo; /* vector offset (4-word frame) */ | |
45 | }; | |
46 | ||
47 | #define CLKF_USERMODE(framep) (((framep)->sr & PSL_S) == 0) | |
48 | #define CLKF_BASEPRI(framep) (((framep)->sr & PSL_IPL) == 0) | |
c49dc82a | 49 | #define CLKF_PC(framep) ((framep)->pc) |
c4b4b65a AF |
50 | #if 0 |
51 | /* We would like to do it this way... */ | |
52 | #define CLKF_INTR(framep) (((framep)->sr & PSL_M) == 0) | |
53 | #else | |
54 | /* but until we start using PSL_M, we have to do this instead */ | |
55 | #define CLKF_INTR(framep) (0) /* XXX */ | |
56 | #endif | |
c49dc82a AF |
57 | |
58 | ||
59 | /* | |
60 | * Preempt the current process if in interrupt from user mode, | |
61 | * or after the current trap/syscall if in system mode. | |
62 | */ | |
63 | #define need_resched() { want_resched++; aston(); } | |
64 | ||
65 | /* | |
c4b4b65a AF |
66 | * Give a profiling tick to the current process when the user profiling |
67 | * buffer pages are invalid. On the 68k, request an ast to send us | |
68 | * through trap, marking the proc as needing a profiling tick. | |
c49dc82a | 69 | */ |
cf5ef508 | 70 | #define need_proftick(p) { (p)->p_flag |= P_OWEUPC; aston(); } |
c49dc82a AF |
71 | |
72 | /* | |
73 | * Notify the current process (p) that it has a signal pending, | |
74 | * process as soon as possible. | |
75 | */ | |
76 | #define signotify(p) aston() | |
77 | ||
78 | #define aston() (astpending++) | |
79 | ||
80 | int astpending; /* need to trap before returning to user mode */ | |
81 | int want_resched; /* resched() was called */ | |
82 | ||
83 | ||
84 | /* | |
85 | * simulated software interrupt register | |
86 | */ | |
87 | extern unsigned char ssir; | |
88 | ||
89 | #define SIR_NET 0x1 | |
90 | #define SIR_CLOCK 0x2 | |
91 | ||
92 | #define siroff(x) ssir &= ~(x) | |
93 | #define setsoftnet() ssir |= SIR_NET | |
94 | #define setsoftclock() ssir |= SIR_CLOCK | |
95 | ||
5ccec412 AF |
96 | /* |
97 | * CTL_MACHDEP definitions. | |
98 | */ | |
99 | #define CPU_CONSDEV 1 /* dev_t: console terminal device */ | |
100 | #define CPU_MAXID 2 /* number of valid machdep ids */ | |
101 | ||
102 | #define CTL_MACHDEP_NAMES { \ | |
103 | { 0, 0 }, \ | |
104 | { "console_device", CTLTYPE_STRUCT }, \ | |
105 | } | |
106 | ||
98213947 AF |
107 | #ifdef KERNEL |
108 | extern int mmutype, machineid; | |
109 | #endif | |
110 | ||
111 | /* values for machineid */ | |
112 | #define LUNA_I 1 /* 20Mhz 68030 */ | |
113 | #define LUNA_II 2 /* 25Mhz 68040 */ | |
114 | ||
c49dc82a AF |
115 | /* values for mmutype (assigned for quick testing) */ |
116 | #define MMU_68040 -2 /* 68040 on-chip MMU */ | |
117 | #define MMU_68030 -1 /* 68030 on-chip subset of 68851 */ | |
118 | ||
119 | /* values for cpuspeed (not really related to clock speed due to caches) */ | |
120 | #define MHZ_8 1 | |
121 | #define MHZ_16 2 | |
122 | #define MHZ_25 3 | |
123 | #define MHZ_33 4 | |
124 | #define MHZ_50 6 | |
125 | ||
126 | /* | |
127 | * 68851 and 68030 MMU | |
128 | */ | |
129 | #define PMMU_LVLMASK 0x0007 | |
130 | #define PMMU_INV 0x0400 | |
131 | #define PMMU_WP 0x0800 | |
132 | #define PMMU_ALV 0x1000 | |
133 | #define PMMU_SO 0x2000 | |
134 | #define PMMU_LV 0x4000 | |
135 | #define PMMU_BE 0x8000 | |
136 | #define PMMU_FAULT (PMMU_WP|PMMU_INV) | |
137 | ||
138 | /* | |
139 | * 68040 MMU | |
140 | */ | |
141 | #define MMU4_RES 0x001 | |
142 | #define MMU4_TTR 0x002 | |
143 | #define MMU4_WP 0x004 | |
144 | #define MMU4_MOD 0x010 | |
145 | #define MMU4_CMMASK 0x060 | |
146 | #define MMU4_SUP 0x080 | |
147 | #define MMU4_U0 0x100 | |
148 | #define MMU4_U1 0x200 | |
149 | #define MMU4_GLB 0x400 | |
150 | #define MMU4_BE 0x800 | |
151 | ||
152 | /* 680X0 function codes */ | |
153 | #define FC_USERD 1 /* user data space */ | |
154 | #define FC_USERP 2 /* user program space */ | |
155 | #define FC_PURGE 3 /* HPMMU: clear TLB entries */ | |
156 | #define FC_SUPERD 5 /* supervisor data space */ | |
157 | #define FC_SUPERP 6 /* supervisor program space */ | |
158 | #define FC_CPU 7 /* CPU space */ | |
159 | ||
160 | /* fields in the 68020 cache control register */ | |
161 | #define IC_ENABLE 0x0001 /* enable instruction cache */ | |
162 | #define IC_FREEZE 0x0002 /* freeze instruction cache */ | |
163 | #define IC_CE 0x0004 /* clear instruction cache entry */ | |
164 | #define IC_CLR 0x0008 /* clear entire instruction cache */ | |
165 | ||
166 | /* additional fields in the 68030 cache control register */ | |
167 | #define IC_BE 0x0010 /* instruction burst enable */ | |
168 | #define DC_ENABLE 0x0100 /* data cache enable */ | |
169 | #define DC_FREEZE 0x0200 /* data cache freeze */ | |
170 | #define DC_CE 0x0400 /* clear data cache entry */ | |
171 | #define DC_CLR 0x0800 /* clear entire data cache */ | |
172 | #define DC_BE 0x1000 /* data burst enable */ | |
173 | #define DC_WA 0x2000 /* write allocate */ | |
174 | ||
175 | #define CACHE_ON (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) | |
176 | #define CACHE_OFF (DC_CLR|IC_CLR) | |
177 | #define CACHE_CLR (CACHE_ON) | |
178 | #define IC_CLEAR (DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) | |
179 | #define DC_CLEAR (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE) | |
180 | ||
181 | /* 68040 cache control register */ | |
182 | #define IC4_ENABLE 0x8000 /* instruction cache enable bit */ | |
183 | #define DC4_ENABLE 0x80000000 /* data cache enable bit */ | |
184 | ||
185 | #define CACHE4_ON (IC4_ENABLE|DC4_ENABLE) | |
186 | #define CACHE4_OFF (0) |