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60f56dfc KM |
1 | /* |
2 | * Copyright (c) 1982, 1990 The Regents of the University of California. | |
3 | * All rights reserved. | |
4 | * | |
5 | * %sccs.include.redist.c% | |
6 | * | |
7 | * @(#)dmareg.h 7.1 (Berkeley) %G% | |
8 | */ | |
9 | ||
10 | /* | |
11 | * Hardware layout for the 98620[ABC]: | |
12 | * 98620A (old 320s?): byte/word DMA in up to 64K chunks | |
13 | * 98620B (320s only): 98620A with programmable IPL | |
14 | * 98620C (all others): byte/word/longword DMA in up to 4Gb chunks | |
15 | */ | |
16 | #define v_char volatile char | |
17 | #define v_int volatile int | |
18 | #define vu_char volatile u_char | |
19 | #define vu_short volatile u_short | |
20 | #define vu_int volatile u_int | |
21 | ||
22 | struct dmaBdevice { | |
23 | v_char *dmaB_addr; | |
24 | vu_short dmaB_count; | |
25 | vu_short dmaB_cmd; | |
26 | #define dmaB_stat dmaB_cmd | |
27 | }; | |
28 | ||
29 | struct dmadevice { | |
30 | v_char *dma_addr; | |
31 | vu_int dma_count; | |
32 | vu_short dma_cmd; | |
33 | vu_short dma_stat; | |
34 | }; | |
35 | ||
36 | struct dmareg { | |
37 | struct dmaBdevice dma_Bchan0; | |
38 | struct dmaBdevice dma_Bchan1; | |
39 | /* the rest are 98620C specific */ | |
40 | v_char dma_id[4]; | |
41 | vu_char dma_cr; | |
42 | char dma_pad1[0xEB]; | |
43 | struct dmadevice dma_chan0; | |
44 | char dma_pad2[0xF4]; | |
45 | struct dmadevice dma_chan1; | |
46 | }; | |
47 | ||
48 | #define NDMA 2 | |
49 | ||
50 | /* intr level must be >= level of any device using dma. i.e., splbio */ | |
51 | #define DMAINTLVL 5 | |
52 | ||
53 | /* addresses */ | |
54 | #define DMA_BASE IOV(0x500000) | |
55 | ||
56 | /* command bits */ | |
57 | #define DMA_ENAB 0x0001 | |
58 | #define DMA_WORD 0x0002 | |
59 | #define DMA_WRT 0x0004 | |
60 | #define DMA_PRI 0x0008 | |
61 | #define DMA_IPL(x) (((x) - 3) << 4) | |
62 | #define DMA_LWORD 0x0100 | |
63 | #define DMA_START 0x8000 | |
64 | ||
65 | /* status bits */ | |
66 | #define DMA_ARMED 0x01 | |
67 | #define DMA_INTR 0x02 | |
68 | #define DMA_ACC 0x04 | |
69 | #define DMA_HALT 0x08 | |
70 | #define DMA_BERR 0x10 | |
71 | #define DMA_ALIGN 0x20 | |
72 | #define DMA_WRAP 0x40 | |
73 | ||
74 | #ifdef KERNEL | |
75 | /* | |
76 | * Macros to attempt to hide the HW differences between the 98620B DMA | |
77 | * board and the 1TQ4-0401 DMA chip (68020C "board"). The latter | |
78 | * includes emulation registers for the former but you need to access | |
79 | * the "native-mode" registers directly in order to do 32-bit DMA. | |
80 | * | |
81 | * DMA_CLEAR: Clear interrupt on DMA board. We just use the | |
82 | * emulation registers on the 98620C as that is easiest. | |
83 | * DMA_STAT: Read status register. Again, we always read the | |
84 | * emulation register. Someday we might want to | |
85 | * look at the 98620C status to get the extended bits. | |
86 | * DMA_ARM: Load address, count and kick-off DMA. | |
87 | */ | |
88 | #define DMA_CLEAR(dc) { v_int dmaclr = (int)dc->sc_Bhwaddr->dmaB_addr; } | |
89 | #define DMA_STAT(dc) dc->sc_Bhwaddr->dmaB_stat | |
90 | ||
91 | #if defined(HP320) | |
92 | #define DMA_ARM(dc, ix) \ | |
93 | if (dc->sc_type == DMA_B) { \ | |
94 | register struct dmaBdevice *dma = dc->sc_Bhwaddr; \ | |
95 | dma->dmaB_addr = dc->sc_addr[ix]; \ | |
96 | dma->dmaB_count = dc->sc_count[ix] - 1; \ | |
97 | dma->dmaB_cmd = dc->sc_cmd; \ | |
98 | } else { \ | |
99 | register struct dmadevice *dma = dc->sc_hwaddr; \ | |
100 | dma->dma_addr = dc->sc_addr[ix]; \ | |
101 | dma->dma_count = dc->sc_count[ix] - 1; \ | |
102 | dma->dma_cmd = dc->sc_cmd; \ | |
103 | } | |
104 | #else | |
105 | #define DMA_ARM(dc, ix) \ | |
106 | { \ | |
107 | register struct dmadevice *dma = dc->sc_hwaddr; \ | |
108 | dma->dma_addr = dc->sc_addr[ix]; \ | |
109 | dma->dma_count = dc->sc_count[ix] - 1; \ | |
110 | dma->dma_cmd = dc->sc_cmd; \ | |
111 | } | |
112 | #endif | |
113 | #endif |