projects / unix-history / blame
| Commit | Line | Data |
|---|---|---|
| 60f56dfc KM |
1 | /* |
| 2 | * Copyright (c) 1988 University of Utah. | |
| 3 | * Copyright (c) 1990 The Regents of the University of California. | |
| 4 | * All rights reserved. | |
| 5 | * | |
| 6 | * This code is derived from software contributed to Berkeley by | |
| 7 | * the Systems Programming Group of the University of Utah Computer | |
| 8 | * Science Department. | |
| 9 | * | |
| 10 | * %sccs.include.redist.c% | |
| 11 | * | |
| 12 | * from: Utah $Hdr: grf_dvreg.h 1.4 89/08/25$ | |
| 13 | * | |
| 14 | * @(#)grf_dvreg.h 7.1 (Berkeley) %G% | |
| 15 | */ | |
| 16 | ||
| 17 | /* | |
| 18 | * Map of the DaVinci frame buffer controller chip in memory ... | |
| 19 | */ | |
| 20 | ||
| 21 | #define db_waitbusy(regaddr) \ | |
| 22 | while (((struct dvboxfb *)(regaddr))->wbusy || \ | |
| 23 | ((struct dvboxfb *)(regaddr))->as_busy) DELAY(100) | |
| 24 | ||
| 25 | #define vu_char volatile u_char | |
| 26 | #define vu_short volatile u_short | |
| 27 | #define vu_int volatile u_int | |
| 28 | ||
| 29 | struct rgb { | |
| 30 | u_char :8, :8, :8; | |
| 31 | vu_char red; | |
| 32 | u_char :8, :8, :8; | |
| 33 | vu_char green; | |
| 34 | u_char :8, :8, :8; | |
| 35 | vu_char blue; | |
| 36 | }; | |
| 37 | ||
| 38 | struct dvboxfb { | |
| 39 | u_char :8; | |
| 40 | vu_char reset; /* reset register 0x01 */ | |
| 41 | u_char fb_address; /* frame buffer address 0x02 */ | |
| 42 | vu_char interrupt; /* interrupt register 0x03 */ | |
| 43 | u_char :8; | |
| 44 | vu_char fbwmsb; /* frame buffer width MSB 0x05 */ | |
| 45 | u_char :8; | |
| 46 | vu_char fbwlsb; /* frame buffer width MSB 0x07 */ | |
| 47 | u_char :8; | |
| 48 | vu_char fbhmsb; /* frame buffer height MSB 0x09 */ | |
| 49 | u_char :8; | |
| 50 | vu_char fbhlsb; /* frame buffer height MSB 0x0b */ | |
| 51 | u_char :8; | |
| 52 | vu_char dwmsb; /* display width MSB 0x0d */ | |
| 53 | u_char :8; | |
| 54 | vu_char dwlsb; /* display width MSB 0x0f */ | |
| 55 | u_char :8; | |
| 56 | vu_char dhmsb; /* display height MSB 0x11 */ | |
| 57 | u_char :8; | |
| 58 | vu_char dhlsb; /* display height MSB 0x13 */ | |
| 59 | u_char :8; | |
| 60 | vu_char fbid; /* frame buffer id 0x15 */ | |
| 61 | u_char f1[0x47]; | |
| 62 | vu_char fbomsb; /* frame buffer offset MSB 0x5d */ | |
| 63 | u_char :8; | |
| 64 | vu_char fbolsb; /* frame buffer offset LSB 0x5f */ | |
| 65 | u_char f2[16359]; | |
| 66 | vu_char wbusy; /* Window move in progress 0x4047 */ | |
| 67 | u_char f3[0x405b-0x4047-1]; | |
| 68 | vu_char as_busy; /* Scan accessing frame buf. 0x405B */ | |
| 69 | u_char f4[0x4090-0x405b-1]; | |
| 70 | vu_int fbwen; /* Frame buffer write enable 0x4090 */ | |
| 71 | u_char f5[0x409f-0x4090-4]; | |
| 72 | vu_char wmove; /* Initiate window move. 0x409F */ | |
| 73 | u_char f6[0x40b3-0x409f-1]; | |
| 74 | vu_char fold; /* Byte/longword per pixel 0x40B3 */ | |
| 75 | u_char f7[0x40b7-0x40b3-1]; | |
| 76 | vu_char opwen; /* Overlay plane write enable 0x40B7 */ | |
| 77 | u_char f8[0x40bf-0x40b7-1]; | |
| 78 | vu_char drive; /* Select FB vs. Overlay. 0x40BF */ | |
| 79 | ||
| 80 | u_char f8a[0x40cb-0x40bf-1]; | |
| 81 | vu_char zconfig; /* Z buffer configuration 0x40CB */ | |
| 82 | u_char f8b[0x40cf-0x40cb-1]; | |
| 83 | vu_char alt_rr; /* Alternate replacement rule 0x40CF */ | |
| 84 | u_char f8c[0x40d3-0x40cf-1]; | |
| 85 | vu_char zrr; /* Z replacement rule 0x40D3 */ | |
| 86 | ||
| 87 | u_char f9[0x40d7-0x40d3-1]; | |
| 88 | vu_char en_scan; /* Enable scan DTACK. 0x40D7 */ | |
| 89 | u_char f10[0x40ef-0x40d7-1]; | |
| 90 | vu_char rep_rule; /* Replacement rule 0x40EF */ | |
| 91 | u_char f11[0x40f2-0x40ef-1]; | |
| 92 | vu_short source_x; /* Window source X origin 0x40F2 */ | |
| 93 | u_char f12[0x40f6-0x40f2-2]; | |
| 94 | vu_short source_y; /* Window source Y origin 0x40F6 */ | |
| 95 | u_char f13[0x40fa-0x40f6-2]; | |
| 96 | vu_short dest_x; /* Window dest X origin 0x40FA */ | |
| 97 | u_char f14[0x40fe-0x40fa-2]; | |
| 98 | vu_short dest_y; /* Window dest Y origin 0x40FE */ | |
| 99 | u_char f15[0x4102-0x40fe-2]; | |
| 100 | vu_short wwidth; /* Window width 0x4102 */ | |
| 101 | u_char f16[0x4106-0x4102-2]; | |
| 102 | vu_short wheight; /* Window height 0x4106 */ | |
| 103 | u_char f17[0x6003-0x4106-2]; | |
| 104 | vu_char cmapbank; /* Bank select (0 or 1) 0x6003 */ | |
| 105 | u_char f18[0x6007-0x6003-1]; | |
| 106 | vu_char dispen; /* Display enable 0x6007 */ | |
| 107 | ||
| 108 | u_char f18a[0x600B-0x6007-1]; | |
| 109 | vu_char fbvenp; /* Frame buffer video enable 0x600B */ | |
| 110 | u_char f18b[0x6017-0x600B-1]; | |
| 111 | vu_char fbvens; /* fbvenp blink counterpart 0x6017 */ | |
| 112 | ||
| 113 | u_char f19[0x6023-0x6017-1]; | |
| 114 | vu_char vdrive; /* Video display mode 0x6023 */ | |
| 115 | u_char f20[0x6083-0x6023-1]; | |
| 116 | vu_char panxh; /* Pan display in X (high) 0x6083 */ | |
| 117 | u_char f21[0x6087-0x6083-1]; | |
| 118 | vu_char panxl; /* Pan display in X (low) 0x6087 */ | |
| 119 | u_char f22[0x608b-0x6087-1]; | |
| 120 | vu_char panyh; /* Pan display in Y (high) 0x608B */ | |
| 121 | u_char f23[0x608f-0x608b-1]; | |
| 122 | vu_char panyl; /* Pan display in Y (low) 0x608F */ | |
| 123 | u_char f24[0x6093-0x608f-1]; | |
| 124 | vu_char zoom; /* Zoom factor 0x6093 */ | |
| 125 | u_char f25[0x6097-0x6093-1]; | |
| 126 | vu_char pz_trig; /* Pan & zoom trigger 0x6097 */ | |
| 127 | u_char f26[0x609b-0x6097-1]; | |
| 128 | vu_char ovly0p; /* Overlay 0 primary map 0x609B */ | |
| 129 | u_char f27[0x609f-0x609b-1]; | |
| 130 | vu_char ovly1p; /* Overlay 1 primary map 0x609F */ | |
| 131 | u_char f28[0x60a3-0x609f-1]; | |
| 132 | vu_char ovly0s; /* Overlay 0 secondary map 0x60A3 */ | |
| 133 | u_char f29[0x60a7-0x60a3-1]; | |
| 134 | vu_char ovly1s; /* Overlay 1 secondary map 0x60A7 */ | |
| 135 | u_char f30[0x60ab-0x60a7-1]; | |
| 136 | vu_char opvenp; /* Overlay video enable 0x60AB */ | |
| 137 | u_char f31[0x60af-0x60ab-1]; | |
| 138 | vu_char opvens; /* Overlay blink enable 0x60AF */ | |
| 139 | u_char f32[0x60b3-0x60af-1]; | |
| 140 | vu_char fv_trig; /* Trigger control registers 0x60B3 */ | |
| 141 | u_char f33[0x60b7-0x60b3-1]; | |
| 142 | vu_char cdwidth; /* Iris cdwidth timing reg. 0x60B7 */ | |
| 143 | u_char f34[0x60bb-0x60b7-1]; | |
| 144 | vu_char chstart; /* Iris chstart timing reg. 0x60BB */ | |
| 145 | u_char f35[0x60bf-0x60bb-1]; | |
| 146 | vu_char cvwidth; /* Iris cvwidth timing reg. 0x60BF */ | |
| 147 | u_char f36[0x6100-0x60bf-1]; | |
| 148 | struct rgb rgb[8]; /* overlay color map */ | |
| 149 | u_char f37[0x6403-0x6100-sizeof(struct rgb)*8]; | |
| 150 | vu_char red0; | |
| 151 | u_char f38[0x6803-0x6403-1]; | |
| 152 | vu_char green0; | |
| 153 | u_char f39[0x6c03-0x6803-1]; | |
| 154 | vu_char blue0; | |
| 155 | u_char f40[0x7403-0x6c03-1]; | |
| 156 | vu_char red1; | |
| 157 | u_char f41[0x7803-0x7403-1]; | |
| 158 | vu_char green1; | |
| 159 | u_char f42[0x7c03-0x7803-1]; | |
| 160 | vu_char blue1; | |
| 161 | u_char f43[0x8012-0x7c03-1]; | |
| 162 | vu_short status1; /* Master Status register 0x8012 */ | |
| 163 | u_char f44[0xC226-0x8012-2]; | |
| 164 | vu_short trans; /* Transparency 0xC226 */ | |
| 165 | u_char f45[0xC23E-0xC226-2]; | |
| 166 | vu_short pstop; /* Pace value control 0xc23e */ | |
| 167 | }; |