[unix-history] / usr / src / sys / news3400 / sio / sccreg.h

/*
 * Copyright (c) 1992, 1993
 *	The Regents of the University of California.  All rights reserved.
 *
 * This code is derived from software contributed to Berkeley by
 * Sony Corp. and Kazumasa Utashiro of Software Research Associates, Inc.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *	This product includes software developed by the University of
 *	California, Berkeley and its contributors.
 * 4. Neither the name of the University nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 * from: $Hdr: sccreg.h,v 4.300 91/06/09 06:44:58 root Rel41 $ SONY
 *
 *	@(#)sccreg.h	8.1 (Berkeley) 6/11/93
 */

#ifndef _SCCREG_
#define _SCCREG_

/*
 *	SCC register
 */

struct scc_reg {
	u_char	ctrl;			/* control register	*/
	u_char	data;			/* data    register	*/
};

/*
 *	SCC read register
 */

#define	RR0		0
#define	RR1		1
#define	RR2		2
#define	RR3		3
#define	RR10		10
#define	RR12		12
#define	RR13		13
#define	RR15		15

#define	R0_BREAK	0x80		/* Break/Abort		*/
#define	R0_UDRUN	0x40		/* Tx Underrun/EOM	*/
#define	R0_CTS		0x20		/* CTS			*/
#define	R0_SYNC		0x10		/* Sync/Hunt		*/
#define	R0_DCD		0x08		/* DCD			*/
#define	R0_TxBE		0x04		/* Tx buffer empty	*/
#define	R0_ZERO		0x02		/* Zero count		*/
#define	R0_RxCA		0x01		/* Rx char. available	*/

#define	R1_EOF		0x80		/* End Of Frame (SDLC)	*/
#define	R1_CRC		0x40		/* CRC/Framing Error	*/
#define	R1_OVRUN	0x20		/* Rx Overrun		*/
#define	R1_PARITY	0x10		/* Parity Error		*/
#define	R1_RESID	0x0e		/* Residue code		*/
#define	R1_SENT		0x01		/* All sent		*/

#define	R3_RxA		0x20		/* Channel A Rx IP	*/
#define	R3_TxA		0x10		/* Channel A Tx IP	*/
#define	R3_EXTA		0x08		/* Channel A EXT/STAT	*/
#define	R3_RxB		0x20		/* Channel B Rx IP	*/
#define	R3_TxB		0x10		/* Channel B Tx IP	*/
#define	R3_EXTB		0x08		/* Channel B EXT/STAT	*/

#define	R10_ONEC	0x80		/* One clock missing	*/
#define	R10_TWOC	0x40		/* Two clock missing	*/
#define	R10_LOOP	0x10		/* Loop Sending		*/
#define	R10_ONLOOP	0x02		/* On Loop		*/

#define	R15_BREAK	0x80		/* Break/Abort IE	*/
#define	R15_UDRUN	0x40		/* Tx Underrun IE	*/
#define	R15_CTS		0x20		/* CTS IE		*/
#define	R15_SYNC	0x10		/* Sync/Hunt IE		*/
#define	R15_DCD		0x08		/* DCD IE		*/
#define	R15_ZERO	0x02		/* Zero count IE	*/

/*
 *	SCC write register
 */

#define	WR0		0
#define	WR1		1
#define	WR2		2
#define	WR3		3
#define	WR4		4
#define	WR5		5
#define	WR6		6
#define	WR7		7
#define	WR9		9
#define	WR10		10
#define	WR11		11
#define	WR12		12
#define	WR13		13
#define	WR14		14
#define	WR15		15

#define	W0_RES_UDRUN	0xc0		/* Reset Tx Underrun/EOM	*/
#define	W0_RES_TxCRC	0x80		/* Reset Tx CRC generator	*/
#define	W0_RES_RxCRC	0x40		/* Reset Rx CRC checker		*/
#define	W0_RES_IUS	0x38		/* Reset Highest IUS		*/
#define	W0_RES_ERROR	0x30		/* Error reset			*/
#define	W0_RES_TxINT	0x28		/* Reset TxINT pending		*/
#define	W0_RxINTE	0x20		/* Enable RxINT on next char.	*/
#define	W0_SND_ABORT	0x18		/* Send Abort (SDLC)		*/
#define	W0_RES_EXT	0x10		/* Reset EXT/STAT interrupts	*/

#define	W1_EN_WAIT	0x80		/* WAIT/DMA request enable	*/
#define	W1_WAIT_FUNC	0x40		/* WAIT/DMA request function	*/
#define	W1_WAIT_REQ	0x20		/* WAIT/DMA request on Rx/Tx	*/

#define	W1_RxINT_SC	0x18		/* Rx INT on special condition	*/
#define	W1_RxINT_ALL	0x10		/* Rx INT on all character	*/
#define	W1_RxINT_FRST	0x08		/* Rx INT on first character	*/
#define	W1_PARITY	0x04		/* Parity is special condition	*/
#define	W1_TxINTE	0x02		/* Tx INT enable		*/
#define	W1_EXTINTE	0x01		/* EXT INT enable		*/

#define	W3_Rx8BIT	0xc0		/* Rx 8 bits/character		*/
#define	W3_Rx6BIT	0x80		/* Rx 6 bits/character		*/
#define	W3_Rx7BIT	0x40		/* Rx 7 bits/character		*/
#define	W3_Rx5BIT	0x00		/* Rx 5 bits/character		*/

#define	W3_AUTO		0x20		/* Auto enable			*/
#define	W3_HUNT		0x10		/* Enter Hunt mode		*/
#define	W3_RxCRC	0x08		/* Rx CRC enable		*/
#define	W3_ADDR		0x04		/* Address search mode (SDLC)	*/
#define	W3_SYNCI	0x02		/* Sync char. load inhibit	*/
#define	W3_RxE		0x01		/* Rx enable			*/

#define	W4_X64		0xc0		/* X64 clock mode		*/
#define	W4_X32		0x80		/* X32 clock mode		*/
#define	W4_X16		0x40		/* X16 clock mode		*/
#define	W4_X1		0x00		/* X1 clock mode		*/

#define	W4_EXTSYNC	0x30		/* External Sync mode		*/
#define	W4_SDLC		0x20		/* SDLC mode			*/
#define	W4_SYNC16	0x10		/* 16 bit sync character	*/
#define	W4_SYNC8	0x00		/* 8 bit sync character		*/

#define	W4_STOP2	0x0c		/* 2 stop bits/character	*/
#define	W4_STOP1_5	0x08		/* 1.5 stop bits/character	*/
#define	W4_STOP1	0x04		/* 1 stop bit/character		*/
#define	W4_SYNC		0x00		/* Sync mode enable		*/

#define	W4_EVEN		0x02		/* Parity Even			*/
#define	W4_PARITY	0x01		/* Parity enable		*/

#define	W5_DTR		0x80		/* DTR				*/

#define	W5_Tx8BIT	0x60		/* Tx 8 bits/character		*/
#define	W5_Tx6BIT	0x40		/* Tx 6 bits/character		*/
#define	W5_Tx7BIT	0x20		/* Tx 7 bits/character		*/
#define	W5_Tx5BIT	0x00		/* Tx 5 bits/character		*/

#define	W5_BREAK	0x10		/* Send Break			*/
#define	W5_TxE		0x08		/* Tx enable			*/
#define	W5_CRC16	0x04		/* SDLC/CRC-16			*/
#define	W5_RTS		0x02		/* RTS				*/
#define	W5_TxCRC	0x01		/* Tx CRC enable		*/

#define	W9_RESET	0xc0		/* Force hardware reset		*/
#define	W9_RES_A	0x80		/* Channel reset A		*/
#define	W9_RES_B	0x40		/* Channel reset B		*/

#define	W9_STAT_HIGH	0x10		/* Staus High/Low		*/
#define	W9_MIE		0x08		/* Master Int. enable		*/
#define	W9_DLC		0x04		/* Disable lower chain		*/
#define	W9_NV		0x02		/* Non Vector			*/
#define	W9_VIS		0x01		/* Vector Include Status	*/

#define	W10_CRC_PRESET	0x80		/* CRC preset I/O		*/

#define	W10_FM0		0x60		/* FM0 (transition = 0)		*/
#define	W10_FM1		0x40		/* FM1 (transition = 1)		*/
#define	W10_NRZI	0x20		/* NRZI				*/
#define	W10_NRZ		0x00		/* NRZ				*/

#define	W10_POLL	0x10		/* Go active on poll		*/
#define	W10_MARK	0x08		/* Mark/Flag idle		*/
#define	W10_ABORT	0x04		/* Abort/Flag on underrun	*/
#define	W10_LOOP	0x02		/* Loop mode			*/
#define	W10_SYNC6	0x01		/* 6 bit/8 bit sync		*/

#define	W11_RTxC_XTAL	0x80		/* RTxC Xtal			*/

#define	W11_RxC_DPLL	0x60		/* RxC = DPLL output		*/
#define	W11_RxC_BRG	0x40		/* RxC = BR Gen. output		*/
#define	W11_RxC_TRxC	0x20		/* RxC = TRxC pin		*/
#define	W11_RxC_RTxC	0x00		/* RxC = RTxC pin		*/

#define	W11_TxC_DPLL	0x18		/* TxC = DPLL output		*/
#define	W11_TxC_BRG	0x10		/* TxC = BR Gen. output		*/
#define	W11_TxC_TRxC	0x08		/* TxC = TRxC pin		*/
#define	W11_TxC_RTxC	0x00		/* TxC = RTxC pin		*/

#define	W11_TRxC_O	0x04		/* TRxC O/I			*/

#define	W11_TRxC_DPLL	0x03		/* TRxC = DPLL output		*/
#define	W11_TRxC_BRG	0x02		/* TRxC = BR Gen output		*/
#define	W11_TRxC_TxC	0x01		/* TRxC = Transmit clock	*/
#define	W11_TRxC_XTAL	0x00		/* TRxC = Xtal output		*/

#define	W14_NRZI	0xe0		/* Set NRZI mode		*/
#define	W14_FM		0xc0		/* Set FM mode			*/
#define	W14_RTxC	0xa0		/* Set source = RTxC		*/
#define	W14_BRG		0x80		/* Set source = BR Gen.		*/
#define	W14_DIS_DPLL	0x60		/* Disable DPLL			*/
#define	W14_RES_CLK	0x40		/* Reset missing clock		*/
#define	W14_SEARCH	0x20		/* Enter search mode		*/

#define	W14_LOCAL	0x10		/* Local loopback mode		*/
#define	W14_ECHO	0x08		/* Auto echo			*/
#define	W14_DTR		0x04		/* DTR/Request function		*/
#define	W14_BRG_SRC	0x02		/* BR Gen. source		*/
#define	W14_BRGE	0x01		/* BR Gen. enable		*/

#define	W15_BREAK	0x80		/* Break/Abort IE		*/
#define	W15_UDRUN	0x40		/* Tx underrun/EOM IE		*/
#define	W15_CTS		0x20		/* CTS IE			*/
#define	W15_SYNC	0x10		/* Sync/Hunt IE			*/
#define	W15_DCD		0x08		/* DCD IE			*/
#define	W15_ZERO	0x02		/* Zero count IE		*/

#endif /* _SCCREG_ */
Commit	Line	Data
af5295ff	1	/*
ad787160 C	2	* Copyright (c) 1992, 1993
ad787160 C	3	* The Regents of the University of California. All rights reserved.
af5295ff KM	4	*
	5	* This code is derived from software contributed to Berkeley by
	6	* Sony Corp. and Kazumasa Utashiro of Software Research Associates, Inc.
	7	*
ad787160 C	8	* Redistribution and use in source and binary forms, with or without
	9	* modification, are permitted provided that the following conditions
	10	* are met:
	11	* 1. Redistributions of source code must retain the above copyright
	12	* notice, this list of conditions and the following disclaimer.
	13	* 2. Redistributions in binary form must reproduce the above copyright
	14	* notice, this list of conditions and the following disclaimer in the
	15	* documentation and/or other materials provided with the distribution.
	16	* 3. All advertising materials mentioning features or use of this software
	17	* must display the following acknowledgement:
	18	* This product includes software developed by the University of
	19	* California, Berkeley and its contributors.
	20	* 4. Neither the name of the University nor the names of its contributors
	21	* may be used to endorse or promote products derived from this software
	22	* without specific prior written permission.
	23	*
	24	* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
	25	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
	27	* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
	30	* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
	31	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
	32	* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
	33	* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
	34	* SUCH DAMAGE.
af5295ff KM	35	*
	36	* from: $Hdr: sccreg.h,v 4.300 91/06/09 06:44:58 root Rel41 $ SONY
	37	*
ad787160	38	* @(#)sccreg.h 8.1 (Berkeley) 6/11/93
af5295ff KM	39	*/
	40
	41	#ifndef _SCCREG_
	42	#define _SCCREG_
	43
	44	/*
	45	* SCC register
	46	*/
	47
	48	struct scc_reg {
	49	u_char ctrl; /* control register */
	50	u_char data; /* data register */
	51	};
	52
	53	/*
	54	* SCC read register
	55	*/
	56
	57	#define RR0 0
	58	#define RR1 1
	59	#define RR2 2
	60	#define RR3 3
	61	#define RR10 10
	62	#define RR12 12
	63	#define RR13 13
	64	#define RR15 15
	65
	66	#define R0_BREAK 0x80 /* Break/Abort */
	67	#define R0_UDRUN 0x40 /* Tx Underrun/EOM */
	68	#define R0_CTS 0x20 /* CTS */
	69	#define R0_SYNC 0x10 /* Sync/Hunt */
	70	#define R0_DCD 0x08 /* DCD */
	71	#define R0_TxBE 0x04 /* Tx buffer empty */
	72	#define R0_ZERO 0x02 /* Zero count */
	73	#define R0_RxCA 0x01 /* Rx char. available */
	74
	75	#define R1_EOF 0x80 /* End Of Frame (SDLC) */
	76	#define R1_CRC 0x40 /* CRC/Framing Error */
	77	#define R1_OVRUN 0x20 /* Rx Overrun */
	78	#define R1_PARITY 0x10 /* Parity Error */
	79	#define R1_RESID 0x0e /* Residue code */
	80	#define R1_SENT 0x01 /* All sent */
	81
	82	#define R3_RxA 0x20 /* Channel A Rx IP */
	83	#define R3_TxA 0x10 /* Channel A Tx IP */
	84	#define R3_EXTA 0x08 /* Channel A EXT/STAT */
	85	#define R3_RxB 0x20 /* Channel B Rx IP */
	86	#define R3_TxB 0x10 /* Channel B Tx IP */
	87	#define R3_EXTB 0x08 /* Channel B EXT/STAT */
	88
	89	#define R10_ONEC 0x80 /* One clock missing */
	90	#define R10_TWOC 0x40 /* Two clock missing */
	91	#define R10_LOOP 0x10 /* Loop Sending */
	92	#define R10_ONLOOP 0x02 /* On Loop */
	93
	94	#define R15_BREAK 0x80 /* Break/Abort IE */
	95	#define R15_UDRUN 0x40 /* Tx Underrun IE */
	96	#define R15_CTS 0x20 /* CTS IE */
	97	#define R15_SYNC 0x10 /* Sync/Hunt IE */
	98	#define R15_DCD 0x08 /* DCD IE */
	99	#define R15_ZERO 0x02 /* Zero count IE */
	100
	101	/*
	102	* SCC write register
103	*/
104
105	#define WR0 0
106	#define WR1 1
107	#define WR2 2
108	#define WR3 3
109	#define WR4 4
110	#define WR5 5
111	#define WR6 6
112	#define WR7 7
113	#define WR9 9
114	#define WR10 10
115	#define WR11 11
116	#define WR12 12
117	#define WR13 13
118	#define WR14 14
119	#define WR15 15
120
121	#define W0_RES_UDRUN 0xc0 /* Reset Tx Underrun/EOM */
122	#define W0_RES_TxCRC 0x80 /* Reset Tx CRC generator */
123	#define W0_RES_RxCRC 0x40 /* Reset Rx CRC checker */
124	#define W0_RES_IUS 0x38 /* Reset Highest IUS */
125	#define W0_RES_ERROR 0x30 /* Error reset */
126	#define W0_RES_TxINT 0x28 /* Reset TxINT pending */
127	#define W0_RxINTE 0x20 /* Enable RxINT on next char. */
128	#define W0_SND_ABORT 0x18 /* Send Abort (SDLC) */
129	#define W0_RES_EXT 0x10 /* Reset EXT/STAT interrupts */
130
131	#define W1_EN_WAIT 0x80 /* WAIT/DMA request enable */
132	#define W1_WAIT_FUNC 0x40 /* WAIT/DMA request function */
133	#define W1_WAIT_REQ 0x20 /* WAIT/DMA request on Rx/Tx */
134
135	#define W1_RxINT_SC 0x18 /* Rx INT on special condition */
136	#define W1_RxINT_ALL 0x10 /* Rx INT on all character */
137	#define W1_RxINT_FRST 0x08 /* Rx INT on first character */
138	#define W1_PARITY 0x04 /* Parity is special condition */
139	#define W1_TxINTE 0x02 /* Tx INT enable */
140	#define W1_EXTINTE 0x01 /* EXT INT enable */
141
142	#define W3_Rx8BIT 0xc0 /* Rx 8 bits/character */
143	#define W3_Rx6BIT 0x80 /* Rx 6 bits/character */
144	#define W3_Rx7BIT 0x40 /* Rx 7 bits/character */
145	#define W3_Rx5BIT 0x00 /* Rx 5 bits/character */
146
147	#define W3_AUTO 0x20 /* Auto enable */
148	#define W3_HUNT 0x10 /* Enter Hunt mode */
149	#define W3_RxCRC 0x08 /* Rx CRC enable */
150	#define W3_ADDR 0x04 /* Address search mode (SDLC) */
151	#define W3_SYNCI 0x02 /* Sync char. load inhibit */
152	#define W3_RxE 0x01 /* Rx enable */
153
154	#define W4_X64 0xc0 /* X64 clock mode */
155	#define W4_X32 0x80 /* X32 clock mode */
156	#define W4_X16 0x40 /* X16 clock mode */
157	#define W4_X1 0x00 /* X1 clock mode */
158
159	#define W4_EXTSYNC 0x30 /* External Sync mode */
160	#define W4_SDLC 0x20 /* SDLC mode */
161	#define W4_SYNC16 0x10 /* 16 bit sync character */
162	#define W4_SYNC8 0x00 /* 8 bit sync character */
163
164	#define W4_STOP2 0x0c /* 2 stop bits/character */
165	#define W4_STOP1_5 0x08 /* 1.5 stop bits/character */
166	#define W4_STOP1 0x04 /* 1 stop bit/character */
167	#define W4_SYNC 0x00 /* Sync mode enable */
168
169	#define W4_EVEN 0x02 /* Parity Even */
170	#define W4_PARITY 0x01 /* Parity enable */
171
172	#define W5_DTR 0x80 /* DTR */
173
174	#define W5_Tx8BIT 0x60 /* Tx 8 bits/character */
175	#define W5_Tx6BIT 0x40 /* Tx 6 bits/character */
176	#define W5_Tx7BIT 0x20 /* Tx 7 bits/character */
177	#define W5_Tx5BIT 0x00 /* Tx 5 bits/character */
178
179	#define W5_BREAK 0x10 /* Send Break */
180	#define W5_TxE 0x08 /* Tx enable */
181	#define W5_CRC16 0x04 /* SDLC/CRC-16 */
182	#define W5_RTS 0x02 /* RTS */
183	#define W5_TxCRC 0x01 /* Tx CRC enable */
184
185	#define W9_RESET 0xc0 /* Force hardware reset */
186	#define W9_RES_A 0x80 /* Channel reset A */
187	#define W9_RES_B 0x40 /* Channel reset B */
188
189	#define W9_STAT_HIGH 0x10 /* Staus High/Low */
190	#define W9_MIE 0x08 /* Master Int. enable */
191	#define W9_DLC 0x04 /* Disable lower chain */
192	#define W9_NV 0x02 /* Non Vector */
193	#define W9_VIS 0x01 /* Vector Include Status */
194
195	#define W10_CRC_PRESET 0x80 /* CRC preset I/O */
196
197	#define W10_FM0 0x60 /* FM0 (transition = 0) */
198	#define W10_FM1 0x40 /* FM1 (transition = 1) */
199	#define W10_NRZI 0x20 /* NRZI */
200	#define W10_NRZ 0x00 /* NRZ */
201
202	#define W10_POLL 0x10 /* Go active on poll */
203	#define W10_MARK 0x08 /* Mark/Flag idle */
204	#define W10_ABORT 0x04 /* Abort/Flag on underrun */
205	#define W10_LOOP 0x02 /* Loop mode */
206	#define W10_SYNC6 0x01 /* 6 bit/8 bit sync */
207
208	#define W11_RTxC_XTAL 0x80 /* RTxC Xtal */
209
210	#define W11_RxC_DPLL 0x60 /* RxC = DPLL output */
211	#define W11_RxC_BRG 0x40 /* RxC = BR Gen. output */
212	#define W11_RxC_TRxC 0x20 /* RxC = TRxC pin */
213	#define W11_RxC_RTxC 0x00 /* RxC = RTxC pin */
214
215	#define W11_TxC_DPLL 0x18 /* TxC = DPLL output */
216	#define W11_TxC_BRG 0x10 /* TxC = BR Gen. output */
217	#define W11_TxC_TRxC 0x08 /* TxC = TRxC pin */
218	#define W11_TxC_RTxC 0x00 /* TxC = RTxC pin */
219
220	#define W11_TRxC_O 0x04 /* TRxC O/I */
221
222	#define W11_TRxC_DPLL 0x03 /* TRxC = DPLL output */
223	#define W11_TRxC_BRG 0x02 /* TRxC = BR Gen output */
224	#define W11_TRxC_TxC 0x01 /* TRxC = Transmit clock */
225	#define W11_TRxC_XTAL 0x00 /* TRxC = Xtal output */
226
227	#define W14_NRZI 0xe0 /* Set NRZI mode */
228	#define W14_FM 0xc0 /* Set FM mode */
229	#define W14_RTxC 0xa0 /* Set source = RTxC */
230	#define W14_BRG 0x80 /* Set source = BR Gen. */
231	#define W14_DIS_DPLL 0x60 /* Disable DPLL */
232	#define W14_RES_CLK 0x40 /* Reset missing clock */
233	#define W14_SEARCH 0x20 /* Enter search mode */
234
235	#define W14_LOCAL 0x10 /* Local loopback mode */
236	#define W14_ECHO 0x08 /* Auto echo */
237	#define W14_DTR 0x04 /* DTR/Request function */
238	#define W14_BRG_SRC 0x02 /* BR Gen. source */
239	#define W14_BRGE 0x01 /* BR Gen. enable */
240
241	#define W15_BREAK 0x80 /* Break/Abort IE */
242	#define W15_UDRUN 0x40 /* Tx underrun/EOM IE */
243	#define W15_CTS 0x20 /* CTS IE */
244	#define W15_SYNC 0x10 /* Sync/Hunt IE */
245	#define W15_DCD 0x08 /* DCD IE */
246	#define W15_ZERO 0x02 /* Zero count IE */
247
248	#endif /* _SCCREG_ */