projects / unix-history / blame
| Commit | Line | Data |
|---|---|---|
| da7c5cc6 | 1 | /* |
| 0880b18e | 2 | * Copyright (c) 1982, 1986 Regents of the University of California. |
| b5939d91 | 3 | * All rights reserved. |
| da7c5cc6 | 4 | * |
| c0567266 KB |
5 | * Redistribution and use in source and binary forms, with or without |
| 6 | * modification, are permitted provided that the following conditions | |
| 7 | * are met: | |
| 8 | * 1. Redistributions of source code must retain the above copyright | |
| 9 | * notice, this list of conditions and the following disclaimer. | |
| 10 | * 2. Redistributions in binary form must reproduce the above copyright | |
| 11 | * notice, this list of conditions and the following disclaimer in the | |
| 12 | * documentation and/or other materials provided with the distribution. | |
| 13 | * 3. All advertising materials mentioning features or use of this software | |
| 14 | * must display the following acknowledgement: | |
| 15 | * This product includes software developed by the University of | |
| 16 | * California, Berkeley and its contributors. | |
| 17 | * 4. Neither the name of the University nor the names of its contributors | |
| 18 | * may be used to endorse or promote products derived from this software | |
| 19 | * without specific prior written permission. | |
| 20 | * | |
| 21 | * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND | |
| 22 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
| 23 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
| 24 | * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE | |
| 25 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
| 26 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS | |
| 27 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | |
| 28 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT | |
| 29 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY | |
| 30 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF | |
| 31 | * SUCH DAMAGE. | |
| ad787160 C |
32 | * |
| 33 | * @(#)if_accreg.h 7.3 (Berkeley) 6/28/90 | |
| da7c5cc6 | 34 | */ |
| 227cbec0 BJ |
35 | |
| 36 | /* | |
| 37 | * ACC LH/DH-11 interface | |
| 38 | */ | |
| 39 | ||
| 40 | struct accdma { | |
| 41 | short csr; /* control and status */ | |
| 42 | short db; /* data buffer */ | |
| 43 | u_short ba; /* buss address */ | |
| 44 | short wc; /* word count */ | |
| 45 | }; | |
| 46 | ||
| 47 | struct accdevice { | |
| 48 | struct accdma input; | |
| 49 | struct accdma output; | |
| 50 | }; | |
| 51 | ||
| 52 | #define icsr input.csr | |
| 53 | #define iba input.ba | |
| 54 | #define iwc input.wc | |
| 55 | #define ocsr output.csr | |
| 56 | #define oba output.ba | |
| 57 | #define owc output.wc | |
| 58 | ||
| 59 | /* | |
| 60 | * Bits Common to both input and out CSR's | |
| 61 | */ | |
| 62 | #define ACC_ERR 0x8000 /* error present */ | |
| 63 | #define ACC_NXM 0x4000 /* non-existant memory */ | |
| 64 | #define ACC_RDY 0x0080 /* ready */ | |
| 12ef2795 | 65 | #define ACC_IE 0x0040 /* interrupt enable */ |
| 227cbec0 BJ |
66 | #define ACC_RESET 0x0002 /* reset interface */ |
| 67 | #define ACC_GO 0x0001 /* start operation */ | |
| 68 | ||
| 69 | /* | |
| 70 | * Input Control Status Register | |
| 71 | */ | |
| 72 | #define IN_EOM 0x2000 /* end-of-message recieved */ | |
| 73 | #define IN_HRDY 0x0800 /* host ready */ | |
| 74 | #define IN_IMPBSY 0x0400 /* IMP not ready */ | |
| 75 | #define IN_RMR 0x0200 /* receive master ready error */ | |
| 76 | #define IN_IBF 0x0100 /* input data buffer full */ | |
| 77 | #define IN_WEN 0x0008 /* write enable */ | |
| 78 | #define IN_MRDY 0x0004 /* master ready */ | |
| 79 | ||
| 80 | #define ACC_INBITS \ | |
| 81 | "\20\20ERR\17NXM\16EOM\14HRDY\13IMPBSY\12RMR\11IBF\10RDY\7IE\ | |
| 82 | \4WEN\3MRDY\2RESET\1GO" | |
| 83 | ||
| 84 | /* | |
| 85 | * Output Control Status Register | |
| 86 | */ | |
| 87 | #define OUT_TMR 0x0200 /* transmit master ready error */ | |
| 88 | #define OUT_BBACK 0x0008 /* bus back */ | |
| 89 | #define OUT_ENLB 0x0004 /* enable last bit */ | |
| 90 | ||
| 91 | #define ACC_OUTBITS \ | |
| 92 | "\20\20ERR\17NXM\12TMR\10RDY\7IE\4BBACK\3ENLB\2RESET\1GO" |