[unix-history] / usr / src / sys / vax / uba / uba.c

/*	uba.c	4.13	%G%	*/

#define	DELAY(N)	{ register int d; d = N; while (--d > 0); }

#include "../h/param.h"
#include "../h/systm.h"
#include "../h/cpu.h"
#include "../h/map.h"
#include "../h/pte.h"
#include "../h/buf.h"
#include "../h/vm.h"
#include "../h/uba.h"
#include "../h/dir.h"
#include "../h/user.h"
#include "../h/proc.h"
#include "../h/conf.h"
#include "../h/mtpr.h"
#include "../h/nexus.h"
#include "../h/dk.h"

/*
 * Do transfer on device argument.  The controller
 * and uba involved are implied by the device.
 * We queue for resource wait in the uba code if necessary.
 * We return 1 if the transfer was started, 0 if it was not.
 * If you call this routine with the head of the queue for a
 * UBA, it will automatically remove the device from the UBA
 * queue before it returns.  If some other device is given
 * as argument, it will be added to the request queue if the
 * request cannot be started immediately.  This means that
 * passing a device which is on the queue but not at the head
 * of the request queue is likely to be a disaster.
 */
ubago(ui)
	register struct uba_dinfo *ui;
{
	register struct uba_minfo *um = ui->ui_mi;
	register struct uba_hd *uh;
	register int s, unit;

	uh = &uba_hd[um->um_ubanum];
	s = spl6();
	if (um->um_driver->ud_xclu && uh->uh_users > 0 || uh->uh_xclu)
		goto rwait;
	um->um_ubinfo = ubasetup(um->um_ubanum, um->um_tab.b_actf->b_actf,
	    UBA_NEEDBDP|UBA_CANTWAIT);
	if (um->um_ubinfo == 0)
		goto rwait;
	uh->uh_users++;
	if (um->um_driver->ud_xclu)
		uh->uh_xclu = 1;
	splx(s);
	if (ui->ui_dk >= 0) {
		unit = ui->ui_dk;
		dk_busy |= 1<<unit;
	}
	if (uh->uh_actf == ui)
		uh->uh_actf = ui->ui_forw;
	(*um->um_driver->ud_dgo)(um);
	if (ui->ui_dk >= 0) {
		dk_xfer[unit]++;
		dk_wds[unit] += um->um_tab.b_actf->b_bcount>>6;
	}
	return (1);
rwait:
	if (uh->uh_actf != ui) {
		ui->ui_forw = NULL;
		if (uh->uh_actf == NULL)
			uh->uh_actf = ui;
		else
			uh->uh_actl->ui_forw = ui;
		uh->uh_actl = ui;
	}
	splx(s);
	return (0);
}

ubadone(um)
	register struct uba_minfo *um;
{
	register struct uba_hd *uh = &uba_hd[um->um_ubanum];

	if (um->um_driver->ud_xclu)
		uh->uh_xclu = 0;
	uh->uh_users--;
	ubarelse(um->um_ubanum, &um->um_ubinfo);
}

/*
 * Allocate and setup UBA map registers, and bdp's
 * Flags says whether bdp is needed, whether the caller can't
 * wait (e.g. if the caller is at interrupt level).
 *
 * Return value:
 *	Bits 0-8	Byte offset
 *	Bits 9-17	Start map reg. no.
 *	Bits 18-27	No. mapping reg's
 *	Bits 28-31	BDP no.
 */
ubasetup(uban, bp, flags)
	struct buf *bp;
{
	register struct uba_hd *uh = &uba_hd[uban];
	register int temp, i;
	int npf, reg, bdp;
	unsigned v;
	register struct pte *pte, *io;
	struct proc *rp;
	int a, o, ubinfo;

	v = btop(bp->b_un.b_addr);
	o = (int)bp->b_un.b_addr & PGOFSET;
	npf = btoc(bp->b_bcount + o) + 1;
	a = spl6();
	while ((reg = malloc(uh->uh_map, npf)) == 0) {
		if (flags & UBA_CANTWAIT)
			return (0);
		uh->uh_mrwant++;
		sleep((caddr_t)uh->uh_map, PSWP);
	}
	bdp = 0;
	if (flags & UBA_NEEDBDP) {
		while ((bdp = ffs(uh->uh_bdpfree)) == 0) {
			if (flags & UBA_CANTWAIT) {
				mfree(uh->uh_map, npf, reg);
				return (0);
			}
			uh->uh_bdpwant++;
			sleep((caddr_t)uh->uh_map, PSWP);
		}
		uh->uh_bdpfree &= ~(1 << (bdp-1));
	}
	splx(a);
	reg--;
	ubinfo = (bdp << 28) | (npf << 18) | (reg << 9) | o;
	io = &uh->uh_uba->uba_map[reg];
	temp = (bdp << 21) | UBA_MRV;
	rp = bp->b_flags&B_DIRTY ? &proc[2] : bp->b_proc;
	if (bdp && (o & 01))
		temp |= UBA_BO;
	if (bp->b_flags & B_UAREA) {
		for (i = UPAGES - bp->b_bcount / NBPG; i < UPAGES; i++) {
			if (rp->p_addr[i].pg_pfnum == 0)
				panic("uba: zero upage");
			*(int *)io++ = rp->p_addr[i].pg_pfnum | temp;
		}
	} else if ((bp->b_flags & B_PHYS) == 0) {
		pte = &Sysmap[btop(((int)bp->b_un.b_addr)&0x7fffffff)];
		while (--npf != 0)
			*(int *)io++ = pte++->pg_pfnum | temp;
	} else {
		if (bp->b_flags & B_PAGET)
			pte = &Usrptmap[btokmx((struct pte *)bp->b_un.b_addr)];
		else
			pte = vtopte(rp, v);
		while (--npf != 0) {
			if (pte->pg_pfnum == 0)
				panic("uba zero uentry");
			*(int *)io++ = pte++->pg_pfnum | temp;
		}
	}
	*(int *)io++ = 0;
	return (ubinfo);
}

/*
 * Non buffer setup interface... set up a buffer and call ubasetup.
 */
uballoc(uban, addr, bcnt, flags)
	caddr_t addr;
	unsigned short bcnt;
{
	struct buf ubabuf;

	ubabuf.b_un.b_addr = addr;
	ubabuf.b_flags = B_BUSY;
	ubabuf.b_bcount = bcnt;
	/* that's all the fields ubasetup() needs */
	return (ubasetup(uban, &ubabuf, flags));
}
 
/*
 * Release resources on uba uban, and then unblock resource waiters.
 * The map register parameter is by value since we need to block
 * against uba resets on 11/780's.
 */
ubarelse(uban, amr)
	int *amr;
{
	register struct uba_hd *uh = &uba_hd[uban];
	register int bdp, reg, npf, s;
	int mr;
 
	/*
	 * Carefully see if we should release the space, since
	 * it may be released asynchronously at uba reset time.
	 */
	s = spl6();
	mr = *amr;
	if (mr == 0) {
		/*
		 * A ubareset() occurred before we got around
		 * to releasing the space... no need to bother.
		 */
		splx(s);
		return;
	}
	*amr = 0;
	splx(s);		/* let interrupts in, we're safe for a while */
	bdp = (mr >> 28) & 0x0f;
	if (bdp) {
		switch (cpu)
		{
#if VAX780
		case VAX_780:
			uh->uh_uba->uba_dpr[bdp] |= UBA_BNE;
			break;
#endif
#if VAX750
		case VAX_750:
			uh->uh_uba->uba_dpr[bdp] |= UBA_PURGE|UBA_NXM|UBA_UCE;
			break;
#endif
		}
		uh->uh_bdpfree |= 1 << (bdp-1);		/* atomic */
		if (uh->uh_bdpwant) {
			uh->uh_bdpwant = 0;
			wakeup((caddr_t)uh->uh_map);
		}
	}
	/*
	 * Put back the registers in the resource map.
	 * The map code must not be reentered, so we do this
	 * at high ipl.
	 */
	npf = (mr >> 18) & 0x3ff;
	reg = ((mr >> 9) & 0x1ff) + 1;
	s = spl6();
	mfree(uh->uh_map, npf, reg);
	splx(s);

	/*
	 * Wakeup sleepers for map registers,
	 * and also, if there are processes blocked in dgo(),
	 * give them a chance at the UNIBUS.
	 */
	if (uh->uh_mrwant) {
		uh->uh_mrwant = 0;
		wakeup((caddr_t)uh->uh_map);
	}
	while (uh->uh_actf && ubago(uh->uh_actf))
		;
}

/*
 * Generate a reset on uba number uban.  Then
 * call each device in the character device table,
 * giving it a chance to clean up so as to be able to continue.
 */
ubareset(uban)
	int uban;
{
	register struct cdevsw *cdp;
	int s;

	s = spl6();
	switch (cpu) {
#if VAX==780
	case VAX_780:
		printf("UBA RESET %d:", uban);
		ubainit(uba_hd[uban].uh_uba);
		break;
#endif
#if VAX==750
	case VAX_750:
		printf("UNIBUS INIT:");
		mtpr(IUR, 1);
		DELAY(100000);
		break;
#endif
	}
	for (cdp = cdevsw; cdp->d_open; cdp++)
		(*cdp->d_reset)(uban);
	printf("\n");
	splx(s);
}

/*
 * Init a uba.  This is called with a pointer
 * rather than a virtual address since it is called
 * by code which runs with memory mapping disabled.
 * In these cases we really don't need the interrupts
 * enabled, but since we run with ipl high, we don't care
 * if they are, they will never happen anyways.
 */
ubainit(uba)
	register struct uba_regs *uba;
{

	uba->uba_cr = UBA_ADINIT;
	uba->uba_cr = UBA_IFS|UBA_BRIE|UBA_USEFIE|UBA_SUEFIE;
	while ((uba->uba_cnfgr & UBA_UBIC) == 0)
		;
}

#if VAX780
/*
 * Check to make sure the UNIBUS adaptor is not hung,
 * with an interrupt in the register to be presented,
 * but not presenting it for an extended period (5 seconds).
 */
unhang()
{
	register int uban;

	for (uban = 0; uban < numuba; uban++) {
		register struct uba_hd *uh = &uba_hd[uban];
		register struct uba_regs *up = uh->uh_uba;

		if (up->uba_sr == 0)
			return;
		uh->uh_hangcnt++;
		if (uh->uh_hangcnt > 5*HZ) {
			uh->uh_hangcnt = 0;
			printf("HANG ");
			ubareset(uban);
		}
	}
}

/*
 * This is a timeout routine which decrements the ``i forgot to
 * interrupt'' counts, on an 11/780.  This prevents slowly growing
 * counts from causing a UBA reset since we are interested only
 * in hang situations.
 */
ubawatch()
{
	register struct uba_hd *uh;
	register int uban;

	for (uban = 0; uban < numuba; uban++) {
		uh = &uba_hd[uban];
		if (uh->uh_hangcnt)
			uh->uh_hangcnt--;
	}
}

/*
 * This routine is called by the locore code to
 * process a UBA error on an 11/780.  The arguments are passed
 * on the stack, and value-result (through some trickery).
 * In particular, the uvec argument is used for further
 * uba processing so the result aspect of it is very important.
 * It must not be declared register.
 */
/*ARGSUSED*/
ubaerror(uban, uh, xx, uvec, uba)
	register int uban;
	register struct uba_hd *uh;
	int uvec;
	register struct uba_regs *uba;
{
	register sr, s;

	if (uvec == 0) {
		uh->uh_zvcnt++;
		if (uh->uh_zvcnt > 250000) {
			printf("ZERO VECTOR ");
			ubareset(uban);
		}
		uvec = 0;
		return;
	}
	if (uba->uba_cnfgr & NEX_CFGFLT) {
		printf("UBA%d SBI FAULT sr %x cnfgr %x\n",
		    uban, uba->uba_sr, uba->uba_cnfgr);
		ubareset(uban);
		uvec = 0;
		return;
	}
	sr = uba->uba_sr;
	s = spl7();
	printf("UBA%d ERROR SR %x FMER %x FUBAR %o\n",
	    uban, uba->uba_sr, uba->uba_fmer, 4*uba->uba_fubar);
	splx(s);
	uba->uba_sr = sr;
	uvec &= UBA_DIV;
	return;
}
#endif
Commit	Line	Data
28ca05a9	1	/* uba.c 4.13 %G% */
b7333467 BJ	2
b7333467 BJ	3	#define DELAY(N) { register int d; d = N; while (--d > 0); }
c14fd247 BJ	4
c14fd247 BJ	5	#include "../h/param.h"
3f3a34c3 BJ	6	#include "../h/systm.h"
3f3a34c3 BJ	7	#include "../h/cpu.h"
c14fd247 BJ	8	#include "../h/map.h"
c14fd247 BJ	9	#include "../h/pte.h"
c14fd247	10	#include "../h/buf.h"
b7333467	11	#include "../h/vm.h"
3f3a34c3	12	#include "../h/uba.h"
c14fd247 BJ	13	#include "../h/dir.h"
	14	#include "../h/user.h"
	15	#include "../h/proc.h"
2e74ef16	16	#include "../h/conf.h"
868a6a95	17	#include "../h/mtpr.h"
3f3a34c3	18	#include "../h/nexus.h"
b7333467 BJ	19	#include "../h/dk.h"
	20
	21	/*
	22	* Do transfer on device argument. The controller
	23	* and uba involved are implied by the device.
	24	* We queue for resource wait in the uba code if necessary.
	25	* We return 1 if the transfer was started, 0 if it was not.
	26	* If you call this routine with the head of the queue for a
	27	* UBA, it will automatically remove the device from the UBA
	28	* queue before it returns. If some other device is given
	29	* as argument, it will be added to the request queue if the
	30	* request cannot be started immediately. This means that
	31	* passing a device which is on the queue but not at the head
	32	* of the request queue is likely to be a disaster.
	33	*/
	34	ubago(ui)
	35	register struct uba_dinfo *ui;
	36	{
	37	register struct uba_minfo *um = ui->ui_mi;
	38	register struct uba_hd *uh;
	39	register int s, unit;
	40
	41	uh = &uba_hd[um->um_ubanum];
	42	s = spl6();
28ca05a9	43	if (um->um_driver->ud_xclu && uh->uh_users > 0 \|\| uh->uh_xclu)
0801d37f	44	goto rwait;
b7333467 BJ	45	um->um_ubinfo = ubasetup(um->um_ubanum, um->um_tab.b_actf->b_actf,
b7333467 BJ	46	UBA_NEEDBDP\|UBA_CANTWAIT);
0801d37f BJ	47	if (um->um_ubinfo == 0)
0801d37f BJ	48	goto rwait;
0801d37f	49	uh->uh_users++;
28ca05a9	50	if (um->um_driver->ud_xclu)
0801d37f	51	uh->uh_xclu = 1;
b7333467 BJ	52	splx(s);
	53	if (ui->ui_dk >= 0) {
	54	unit = ui->ui_dk;
	55	dk_busy \|= 1<<unit;
	56	}
	57	if (uh->uh_actf == ui)
	58	uh->uh_actf = ui->ui_forw;
	59	(*um->um_driver->ud_dgo)(um);
	60	if (ui->ui_dk >= 0) {
	61	dk_xfer[unit]++;
	62	dk_wds[unit] += um->um_tab.b_actf->b_bcount>>6;
	63	}
	64	return (1);
0801d37f BJ	65	rwait:
	66	if (uh->uh_actf != ui) {
	67	ui->ui_forw = NULL;
	68	if (uh->uh_actf == NULL)
	69	uh->uh_actf = ui;
	70	else
	71	uh->uh_actl->ui_forw = ui;
	72	uh->uh_actl = ui;
	73	}
	74	splx(s);
	75	return (0);
	76	}
	77
	78	ubadone(um)
	79	register struct uba_minfo *um;
	80	{
	81	register struct uba_hd *uh = &uba_hd[um->um_ubanum];
	82
28ca05a9	83	if (um->um_driver->ud_xclu)
0801d37f BJ	84	uh->uh_xclu = 0;
0801d37f BJ	85	uh->uh_users--;
0801d37f	86	ubarelse(um->um_ubanum, &um->um_ubinfo);
b7333467	87	}
c14fd247 BJ	88
c14fd247 BJ	89	/*
3f3a34c3 BJ	90	* Allocate and setup UBA map registers, and bdp's
	91	* Flags says whether bdp is needed, whether the caller can't
	92	* wait (e.g. if the caller is at interrupt level).
c14fd247	93	*
b7333467	94	* Return value:
c14fd247 BJ	95	* Bits 0-8 Byte offset
	96	* Bits 9-17 Start map reg. no.
	97	* Bits 18-27 No. mapping reg's
	98	* Bits 28-31 BDP no.
	99	*/
3f3a34c3 BJ	100	ubasetup(uban, bp, flags)
3f3a34c3 BJ	101	struct buf *bp;
c14fd247	102	{
3f3a34c3	103	register struct uba_hd *uh = &uba_hd[uban];
c14fd247 BJ	104	register int temp, i;
	105	int npf, reg, bdp;
	106	unsigned v;
	107	register struct pte pte, io;
	108	struct proc *rp;
	109	int a, o, ubinfo;
	110
	111	v = btop(bp->b_un.b_addr);
	112	o = (int)bp->b_un.b_addr & PGOFSET;
	113	npf = btoc(bp->b_bcount + o) + 1;
	114	a = spl6();
3f3a34c3 BJ	115	while ((reg = malloc(uh->uh_map, npf)) == 0) {
	116	if (flags & UBA_CANTWAIT)
	117	return (0);
	118	uh->uh_mrwant++;
	119	sleep((caddr_t)uh->uh_map, PSWP);
c14fd247	120	}
c14fd247	121	bdp = 0;
3f3a34c3 BJ	122	if (flags & UBA_NEEDBDP) {
	123	while ((bdp = ffs(uh->uh_bdpfree)) == 0) {
	124	if (flags & UBA_CANTWAIT) {
	125	mfree(uh->uh_map, npf, reg);
	126	return (0);
	127	}
	128	uh->uh_bdpwant++;
	129	sleep((caddr_t)uh->uh_map, PSWP);
c14fd247	130	}
658110d5	131	uh->uh_bdpfree &= ~(1 << (bdp-1));
3f3a34c3	132	}
c14fd247	133	splx(a);
658110d5	134	reg--;
c14fd247	135	ubinfo = (bdp << 28) \| (npf << 18) \| (reg << 9) \| o;
3f3a34c3 BJ	136	io = &uh->uh_uba->uba_map[reg];
3f3a34c3 BJ	137	temp = (bdp << 21) \| UBA_MRV;
c14fd247 BJ	138	rp = bp->b_flags&B_DIRTY ? &proc[2] : bp->b_proc;
c14fd247 BJ	139	if (bdp && (o & 01))
3f3a34c3	140	temp \|= UBA_BO;
c14fd247 BJ	141	if (bp->b_flags & B_UAREA) {
	142	for (i = UPAGES - bp->b_bcount / NBPG; i < UPAGES; i++) {
	143	if (rp->p_addr[i].pg_pfnum == 0)
	144	panic("uba: zero upage");
	145	(int )io++ = rp->p_addr[i].pg_pfnum \| temp;
	146	}
	147	} else if ((bp->b_flags & B_PHYS) == 0) {
da1392b6	148	pte = &Sysmap[btop(((int)bp->b_un.b_addr)&0x7fffffff)];
c14fd247	149	while (--npf != 0)
da1392b6	150	(int )io++ = pte++->pg_pfnum \| temp;
c14fd247 BJ	151	} else {
	152	if (bp->b_flags & B_PAGET)
	153	pte = &Usrptmap[btokmx((struct pte *)bp->b_un.b_addr)];
	154	else
	155	pte = vtopte(rp, v);
	156	while (--npf != 0) {
	157	if (pte->pg_pfnum == 0)
	158	panic("uba zero uentry");
	159	(int )io++ = pte++->pg_pfnum \| temp;
	160	}
	161	}
	162	(int )io++ = 0;
	163	return (ubinfo);
	164	}
	165
c14fd247	166	/*
b7333467	167	* Non buffer setup interface... set up a buffer and call ubasetup.
c14fd247	168	*/
3f3a34c3	169	uballoc(uban, addr, bcnt, flags)
c14fd247 BJ	170	caddr_t addr;
	171	unsigned short bcnt;
	172	{
89e0f717	173	struct buf ubabuf;
c14fd247	174
c14fd247 BJ	175	ubabuf.b_un.b_addr = addr;
	176	ubabuf.b_flags = B_BUSY;
	177	ubabuf.b_bcount = bcnt;
89e0f717	178	/* that's all the fields ubasetup() needs */
3f3a34c3	179	return (ubasetup(uban, &ubabuf, flags));
c14fd247 BJ	180	}
c14fd247 BJ	181
b28deaf8	182	/*
b7333467 BJ	183	* Release resources on uba uban, and then unblock resource waiters.
	184	* The map register parameter is by value since we need to block
	185	* against uba resets on 11/780's.
b28deaf8	186	*/
3f3a34c3	187	ubarelse(uban, amr)
b28deaf8	188	int *amr;
c14fd247	189	{
3f3a34c3	190	register struct uba_hd *uh = &uba_hd[uban];
b7333467	191	register int bdp, reg, npf, s;
b28deaf8	192	int mr;
c14fd247	193
b7333467 BJ	194	/*
	195	* Carefully see if we should release the space, since
	196	* it may be released asynchronously at uba reset time.
	197	*/
	198	s = spl6();
b28deaf8 BJ	199	mr = *amr;
b28deaf8 BJ	200	if (mr == 0) {
b7333467 BJ	201	/*
	202	* A ubareset() occurred before we got around
	203	* to releasing the space... no need to bother.
	204	*/
	205	splx(s);
b28deaf8 BJ	206	return;
b28deaf8 BJ	207	}
88149598	208	*amr = 0;
b7333467	209	splx(s); /* let interrupts in, we're safe for a while */
c14fd247 BJ	210	bdp = (mr >> 28) & 0x0f;
c14fd247 BJ	211	if (bdp) {
5aa9d5ea RE	212	switch (cpu)
	213	{
	214	#if VAX780
	215	case VAX_780:
	216	uh->uh_uba->uba_dpr[bdp] \|= UBA_BNE;
	217	break;
	218	#endif
	219	#if VAX750
	220	case VAX_750:
	221	uh->uh_uba->uba_dpr[bdp] \|= UBA_PURGE\|UBA_NXM\|UBA_UCE;
	222	break;
	223	#endif
	224	}
b7333467	225	uh->uh_bdpfree \|= 1 << (bdp-1); /* atomic */
3f3a34c3 BJ	226	if (uh->uh_bdpwant) {
	227	uh->uh_bdpwant = 0;
	228	wakeup((caddr_t)uh->uh_map);
c14fd247 BJ	229	}
c14fd247 BJ	230	}
b7333467 BJ	231	/*
	232	* Put back the registers in the resource map.
	233	* The map code must not be reentered, so we do this
	234	* at high ipl.
	235	*/
c14fd247 BJ	236	npf = (mr >> 18) & 0x3ff;
c14fd247 BJ	237	reg = ((mr >> 9) & 0x1ff) + 1;
b7333467	238	s = spl6();
3f3a34c3	239	mfree(uh->uh_map, npf, reg);
b7333467 BJ	240	splx(s);
	241
	242	/*
	243	* Wakeup sleepers for map registers,
	244	* and also, if there are processes blocked in dgo(),
	245	* give them a chance at the UNIBUS.
	246	*/
3f3a34c3 BJ	247	if (uh->uh_mrwant) {
	248	uh->uh_mrwant = 0;
	249	wakeup((caddr_t)uh->uh_map);
c14fd247	250	}
b7333467 BJ	251	while (uh->uh_actf && ubago(uh->uh_actf))
b7333467 BJ	252	;
c14fd247 BJ	253	}
c14fd247 BJ	254
b7333467 BJ	255	/*
	256	* Generate a reset on uba number uban. Then
	257	* call each device in the character device table,
	258	* giving it a chance to clean up so as to be able to continue.
	259	*/
3f3a34c3	260	ubareset(uban)
b7333467	261	int uban;
2e74ef16	262	{
2e74ef16	263	register struct cdevsw *cdp;
49c84d3f	264	int s;
2e74ef16	265
4ea0bfc4	266	s = spl6();
3f3a34c3	267	switch (cpu) {
868a6a95	268	#if VAX==780
3f3a34c3 BJ	269	case VAX_780:
	270	printf("UBA RESET %d:", uban);
	271	ubainit(uba_hd[uban].uh_uba);
	272	break;
868a6a95 BJ	273	#endif
868a6a95 BJ	274	#if VAX==750
3f3a34c3 BJ	275	case VAX_750:
	276	printf("UNIBUS INIT:");
	277	mtpr(IUR, 1);
	278	DELAY(100000);
	279	break;
868a6a95	280	#endif
3f3a34c3	281	}
2e74ef16	282	for (cdp = cdevsw; cdp->d_open; cdp++)
3f3a34c3	283	(*cdp->d_reset)(uban);
2e74ef16	284	printf("\n");
4ea0bfc4	285	splx(s);
2e74ef16	286	}
3f3a34c3	287
b7333467 BJ	288	/*
	289	* Init a uba. This is called with a pointer
	290	* rather than a virtual address since it is called
	291	* by code which runs with memory mapping disabled.
	292	* In these cases we really don't need the interrupts
	293	* enabled, but since we run with ipl high, we don't care
	294	* if they are, they will never happen anyways.
	295	*/
5aa9d5ea RE	296	ubainit(uba)
5aa9d5ea RE	297	register struct uba_regs *uba;
3f3a34c3 BJ	298	{
3f3a34c3 BJ	299
5aa9d5ea RE	300	uba->uba_cr = UBA_ADINIT;
	301	uba->uba_cr = UBA_IFS\|UBA_BRIE\|UBA_USEFIE\|UBA_SUEFIE;
	302	while ((uba->uba_cnfgr & UBA_UBIC) == 0)
3f3a34c3 BJ	303	;
	304	}
	305
	306	#if VAX780
b7333467 BJ	307	/*
	308	* Check to make sure the UNIBUS adaptor is not hung,
	309	* with an interrupt in the register to be presented,
	310	* but not presenting it for an extended period (5 seconds).
	311	*/
3f3a34c3 BJ	312	unhang()
	313	{
	314	register int uban;
	315
	316	for (uban = 0; uban < numuba; uban++) {
	317	register struct uba_hd *uh = &uba_hd[uban];
	318	register struct uba_regs *up = uh->uh_uba;
	319
	320	if (up->uba_sr == 0)
	321	return;
	322	uh->uh_hangcnt++;
	323	if (uh->uh_hangcnt > 5*HZ) {
	324	uh->uh_hangcnt = 0;
	325	printf("HANG ");
	326	ubareset(uban);
	327	}
	328	}
	329	}
	330
b7333467 BJ	331	/*
	332	* This is a timeout routine which decrements the ``i forgot to
	333	* interrupt'' counts, on an 11/780. This prevents slowly growing
	334	* counts from causing a UBA reset since we are interested only
	335	* in hang situations.
	336	*/
3f3a34c3 BJ	337	ubawatch()
	338	{
	339	register struct uba_hd *uh;
	340	register int uban;
	341
	342	for (uban = 0; uban < numuba; uban++) {
	343	uh = &uba_hd[uban];
	344	if (uh->uh_hangcnt)
	345	uh->uh_hangcnt--;
	346	}
	347	}
	348
b7333467 BJ	349	/*
	350	* This routine is called by the locore code to
	351	* process a UBA error on an 11/780. The arguments are passed
	352	* on the stack, and value-result (through some trickery).
	353	* In particular, the uvec argument is used for further
	354	* uba processing so the result aspect of it is very important.
	355	* It must not be declared register.
	356	*/
5aa9d5ea	357	/ARGSUSED/
3f3a34c3 BJ	358	ubaerror(uban, uh, xx, uvec, uba)
	359	register int uban;
	360	register struct uba_hd *uh;
	361	int uvec;
	362	register struct uba_regs *uba;
	363	{
	364	register sr, s;
	365
	366	if (uvec == 0) {
	367	uh->uh_zvcnt++;
	368	if (uh->uh_zvcnt > 250000) {
	369	printf("ZERO VECTOR ");
	370	ubareset(uban);
	371	}
	372	uvec = 0;
	373	return;
	374	}
	375	if (uba->uba_cnfgr & NEX_CFGFLT) {
	376	printf("UBA%d SBI FAULT sr %x cnfgr %x\n",
	377	uban, uba->uba_sr, uba->uba_cnfgr);
	378	ubareset(uban);
	379	uvec = 0;
	380	return;
	381	}
	382	sr = uba->uba_sr;
	383	s = spl7();
	384	printf("UBA%d ERROR SR %x FMER %x FUBAR %o\n",
7e00c42b	385	uban, uba->uba_sr, uba->uba_fmer, 4*uba->uba_fubar);
3f3a34c3 BJ	386	splx(s);
	387	uba->uba_sr = sr;
	388	uvec &= UBA_DIV;
	389	return;
	390	}
	391	#endif