Commit | Line | Data |
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9bf86ebb PR |
1 | extern int target_flags; |
2 | ||
3 | enum reg_class | |
4 | { | |
5 | NO_REGS, | |
6 | AREG, DREG, CREG, BREG, | |
7 | Q_REGS, | |
8 | SIREG, DIREG, | |
9 | INDEX_REGS, | |
10 | GENERAL_REGS, | |
11 | FP_TOP_REG, FP_SECOND_REG, | |
12 | FLOAT_REGS, | |
13 | ALL_REGS, LIM_REG_CLASSES | |
14 | }; | |
15 | extern enum reg_class regclass_map[17 ]; | |
16 | ||
17 | ||
18 | extern struct rtx_def *i386_compare_op0, *i386_compare_op1; | |
19 | extern struct rtx_def *(*i386_compare_gen)(), *(*i386_compare_gen_eq)(); | |
20 | extern char *hi_reg_name[]; | |
21 | extern char *qi_reg_name[]; | |
22 | extern char *qi_high_reg_name[]; | |
23 | ||
24 | union flt_or_value { float i; float f; }; | |
25 | union flt_or_int { int i; float f; }; | |
26 | long int | |
27 | __udivsi3 (a, b) | |
28 | unsigned long int a, b; | |
29 | { | |
30 | { register int dx asm("dx"); register int ax asm("ax"); dx = 0; ax = a ; asm ("divl %3" : "=a" (ax), "=d" (dx) : "a" (ax), "g" ( b ), "d" (dx)); return ax; } ; | |
31 | } |