Commit | Line | Data |
---|---|---|
15637ed4 RG |
1 | /* Reload pseudo regs into hard regs for insns that require hard regs. |
2 | Copyright (C) 1987, 1988, 1989 Free Software Foundation, Inc. | |
3 | ||
4 | This file is part of GNU CC. | |
5 | ||
6 | GNU CC is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 1, or (at your option) | |
9 | any later version. | |
10 | ||
11 | GNU CC is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GNU CC; see the file COPYING. If not, write to | |
18 | the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ | |
19 | ||
20 | ||
21 | #include "config.h" | |
22 | #include "rtl.h" | |
23 | #include "insn-config.h" | |
24 | #include "flags.h" | |
25 | #include "regs.h" | |
26 | #include "hard-reg-set.h" | |
27 | #include "reload.h" | |
28 | #include "recog.h" | |
29 | #include "basic-block.h" | |
30 | #include <stdio.h> | |
31 | ||
32 | #define min(A,B) ((A) < (B) ? (A) : (B)) | |
33 | #define max(A,B) ((A) > (B) ? (A) : (B)) | |
34 | ||
35 | /* This file contains the reload pass of the compiler, which is | |
36 | run after register allocation has been done. It checks that | |
37 | each insn is valid (operands required to be in registers really | |
38 | are in registers of the proper class) and fixes up invalid ones | |
39 | by copying values temporarily into registers for the insns | |
40 | that need them. | |
41 | ||
42 | The results of register allocation are described by the vector | |
43 | reg_renumber; the insns still contain pseudo regs, but reg_renumber | |
44 | can be used to find which hard reg, if any, a pseudo reg is in. | |
45 | ||
46 | The technique we always use is to free up a few hard regs that are | |
47 | called ``reload regs'', and for each place where a pseudo reg | |
48 | must be in a hard reg, copy it temporarily into one of the reload regs. | |
49 | ||
50 | All the pseudos that were formerly allocated to the hard regs that | |
51 | are now in use as reload regs must be ``spilled''. This means | |
52 | that they go to other hard regs, or to stack slots if no other | |
53 | available hard regs can be found. Spilling can invalidate more | |
54 | insns, requiring additional need for reloads, so we must keep checking | |
55 | until the process stabilizes. | |
56 | ||
57 | For machines with different classes of registers, we must keep track | |
58 | of the register class needed for each reload, and make sure that | |
59 | we allocate enough reload registers of each class. | |
60 | ||
61 | The file reload.c contains the code that checks one insn for | |
62 | validity and reports the reloads that it needs. This file | |
63 | is in charge of scanning the entire rtl code, accumulating the | |
64 | reload needs, spilling, assigning reload registers to use for | |
65 | fixing up each insn, and generating the new insns to copy values | |
66 | into the reload registers. */ | |
67 | \f | |
68 | /* During reload_as_needed, element N contains a REG rtx for the hard reg | |
69 | into which pseudo reg N has been reloaded (perhaps for a previous insn). */ | |
70 | static rtx *reg_last_reload_reg; | |
71 | ||
72 | /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn | |
73 | for an output reload that stores into reg N. */ | |
74 | static char *reg_has_output_reload; | |
75 | ||
76 | /* Elt N nonzero if hard reg N is a reload-register for an output reload | |
77 | in the current insn. */ | |
78 | static char reg_is_output_reload[FIRST_PSEUDO_REGISTER]; | |
79 | ||
80 | /* Element N is the constant value to which pseudo reg N is equivalent, | |
81 | or zero if pseudo reg N is not equivalent to a constant. | |
82 | find_reloads looks at this in order to replace pseudo reg N | |
83 | with the constant it stands for. */ | |
84 | rtx *reg_equiv_constant; | |
85 | ||
86 | /* Element N is the address of stack slot to which pseudo reg N is equivalent. | |
87 | This is used when the address is not valid as a memory address | |
88 | (because its displacement is too big for the machine.) */ | |
89 | rtx *reg_equiv_address; | |
90 | ||
91 | /* Element N is the memory slot to which pseudo reg N is equivalent, | |
92 | or zero if pseudo reg N is not equivalent to a memory slot. */ | |
93 | rtx *reg_equiv_mem; | |
94 | ||
95 | /* Widest width in which each pseudo reg is referred to (via subreg). */ | |
96 | static int *reg_max_ref_width; | |
97 | ||
98 | /* Element N is the insn that initialized reg N from its equivalent | |
99 | constant or memory slot. */ | |
100 | static rtx *reg_equiv_init; | |
101 | ||
102 | /* During reload_as_needed, element N contains the last pseudo regno | |
103 | reloaded into the Nth reload register. This vector is in parallel | |
104 | with spill_regs. */ | |
105 | static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER]; | |
106 | ||
107 | /* During reload_as_needed, element N contains the insn for which | |
108 | the Nth reload register was last used. This vector is in parallel | |
109 | with spill_regs, and its contents are significant only when | |
110 | reg_reloaded_contents is significant. */ | |
111 | static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER]; | |
112 | ||
113 | /* Number of spill-regs so far; number of valid elements of spill_regs. */ | |
114 | static int n_spills; | |
115 | ||
116 | /* In parallel with spill_regs, contains REG rtx's for those regs. | |
117 | Holds the last rtx used for any given reg, or 0 if it has never | |
118 | been used for spilling yet. This rtx is reused, provided it has | |
119 | the proper mode. */ | |
120 | static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER]; | |
121 | ||
122 | /* In parallel with spill_regs, contains nonzero for a spill reg | |
123 | that was stored after the last time it was used. | |
124 | The precise value is the insn generated to do the store. */ | |
125 | static rtx spill_reg_store[FIRST_PSEUDO_REGISTER]; | |
126 | ||
127 | /* This table is the inverse mapping of spill_regs: | |
128 | indexed by hard reg number, | |
129 | it contains the position of that reg in spill_regs, | |
130 | or -1 for something that is not in spill_regs. */ | |
131 | static short spill_reg_order[FIRST_PSEUDO_REGISTER]; | |
132 | ||
133 | /* This table contains 1 for a register that may not be used | |
134 | for retrying global allocation, or -1 for a register that may be used. | |
135 | The registers that may not be used include all spill registers | |
136 | and the frame pointer (if we are using one). */ | |
137 | static short forbidden_regs[FIRST_PSEUDO_REGISTER]; | |
138 | ||
139 | /* Describes order of use of registers for reloading | |
140 | of spilled pseudo-registers. `spills' is the number of | |
141 | elements that are actually valid; new ones are added at the end. */ | |
142 | static char spill_regs[FIRST_PSEUDO_REGISTER]; | |
143 | ||
144 | /* Describes order of preference for putting regs into spill_regs. | |
145 | Contains the numbers of all the hard regs, in order most preferred first. | |
146 | This order is different for each function. | |
147 | It is set up by order_regs_for_reload. | |
148 | Empty elements at the end contain -1. */ | |
149 | static short potential_reload_regs[FIRST_PSEUDO_REGISTER]; | |
150 | ||
151 | /* 1 for a hard register that appears explicitly in the rtl | |
152 | (for example, function value registers, special registers | |
153 | used by insns, structure value pointer registers). */ | |
154 | static char regs_explicitly_used[FIRST_PSEUDO_REGISTER]; | |
155 | ||
156 | /* For each register, 1 if it was counted against the need for | |
157 | groups. 0 means it can count against max_nongroup instead. */ | |
158 | static char counted_for_groups[FIRST_PSEUDO_REGISTER]; | |
159 | ||
160 | /* For each register, 1 if it was counted against the need for | |
161 | non-groups. 0 means it can become part of a new group. | |
162 | During choose_reload_regs, 1 here means don't use this reg | |
163 | as part of a group, even if it seems to be otherwise ok. */ | |
164 | static char counted_for_nongroups[FIRST_PSEUDO_REGISTER]; | |
165 | ||
166 | /* Nonzero if spilling (REG n) does not require reloading it into | |
167 | a register in order to do (MEM (REG n)). */ | |
168 | ||
169 | static char spill_indirect_ok; | |
170 | ||
171 | /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */ | |
172 | ||
173 | char double_reg_address_ok; | |
174 | ||
175 | /* Record the stack slot for each spilled hard register. */ | |
176 | ||
177 | static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER]; | |
178 | ||
179 | /* Width allocated so far for that stack slot. */ | |
180 | ||
181 | static int spill_stack_slot_width[FIRST_PSEUDO_REGISTER]; | |
182 | ||
183 | /* Indexed by basic block number, nonzero if there is any need | |
184 | for a spill register in that basic block. | |
185 | The pointer is 0 if we did stupid allocation and don't know | |
186 | the structure of basic blocks. */ | |
187 | ||
188 | char *basic_block_needs; | |
189 | ||
190 | /* First uid used by insns created by reload in this function. | |
191 | Used in find_equiv_reg. */ | |
192 | int reload_first_uid; | |
193 | ||
194 | /* Flag set by local-alloc or global-alloc if anything is live in | |
195 | a call-clobbered reg across calls. */ | |
196 | ||
197 | int caller_save_needed; | |
198 | ||
199 | /* Set to 1 by alter_frame_pointer_addresses if it changes anything. */ | |
200 | ||
201 | static int frame_pointer_address_altered; | |
202 | ||
203 | void mark_home_live (); | |
204 | static rtx scan_paradoxical_subregs (); | |
205 | static void reload_as_needed (); | |
206 | static int modes_equiv_for_class_p (); | |
207 | static rtx alter_frame_pointer_addresses (); | |
208 | static void alter_reg (); | |
209 | static int new_spill_reg(); | |
210 | static int spill_hard_reg (); | |
211 | static void choose_reload_regs (); | |
212 | static void emit_reload_insns (); | |
213 | static void delete_output_reload (); | |
214 | static void forget_old_reloads_1 (); | |
215 | static void order_regs_for_reload (); | |
216 | static void eliminate_frame_pointer (); | |
217 | static rtx inc_for_reload (); | |
218 | static int constraint_accepts_reg_p (); | |
219 | static int count_occurrences (); | |
220 | static rtx gen_input_reload (); | |
221 | ||
222 | extern void remove_death (); | |
223 | extern rtx adj_offsettable_operand (); | |
224 | \f | |
225 | /* Main entry point for the reload pass, and only entry point | |
226 | in this file. | |
227 | ||
228 | FIRST is the first insn of the function being compiled. | |
229 | ||
230 | GLOBAL nonzero means we were called from global_alloc | |
231 | and should attempt to reallocate any pseudoregs that we | |
232 | displace from hard regs we will use for reloads. | |
233 | If GLOBAL is zero, we do not have enough information to do that, | |
234 | so any pseudo reg that is spilled must go to the stack. | |
235 | ||
236 | DUMPFILE is the global-reg debugging dump file stream, or 0. | |
237 | If it is nonzero, messages are written to it to describe | |
238 | which registers are seized as reload regs, which pseudo regs | |
239 | are spilled from them, and where the pseudo regs are reallocated to. */ | |
240 | ||
241 | void | |
242 | reload (first, global, dumpfile) | |
243 | rtx first; | |
244 | int global; | |
245 | FILE *dumpfile; | |
246 | { | |
247 | register int class; | |
248 | register int i; | |
249 | register rtx insn; | |
250 | ||
251 | int something_changed; | |
252 | int something_needs_reloads; | |
253 | int new_basic_block_needs; | |
254 | ||
255 | /* The basic block number currently being processed for INSN. */ | |
256 | int this_block; | |
257 | ||
258 | /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack. | |
259 | Set spill_indirect_ok if so. */ | |
260 | register rtx tem | |
261 | = gen_rtx (MEM, Pmode, | |
262 | gen_rtx (PLUS, Pmode, | |
263 | gen_rtx (REG, Pmode, FRAME_POINTER_REGNUM), | |
264 | gen_rtx (CONST_INT, VOIDmode, 4))); | |
265 | ||
266 | spill_indirect_ok = memory_address_p (QImode, tem); | |
267 | ||
268 | tem = gen_rtx (PLUS, Pmode, | |
269 | gen_rtx (REG, Pmode, FRAME_POINTER_REGNUM), | |
270 | gen_rtx (REG, Pmode, FRAME_POINTER_REGNUM)); | |
271 | /* This way, we make sure that reg+reg is an offsettable address. */ | |
272 | tem = plus_constant (tem, 4); | |
273 | ||
274 | double_reg_address_ok = memory_address_p (QImode, tem); | |
275 | ||
276 | /* Enable find_equiv_reg to distinguish insns made by reload. */ | |
277 | reload_first_uid = get_max_uid (); | |
278 | ||
279 | basic_block_needs = 0; | |
280 | ||
281 | /* Remember which hard regs appear explicitly | |
282 | before we merge into `regs_ever_live' the ones in which | |
283 | pseudo regs have been allocated. */ | |
284 | bcopy (regs_ever_live, regs_explicitly_used, sizeof regs_ever_live); | |
285 | ||
286 | /* We don't have a stack slot for any spill reg yet. */ | |
287 | bzero (spill_stack_slot, sizeof spill_stack_slot); | |
288 | bzero (spill_stack_slot_width, sizeof spill_stack_slot_width); | |
289 | ||
290 | /* Compute which hard registers are now in use | |
291 | as homes for pseudo registers. | |
292 | This is done here rather than (eg) in global_alloc | |
293 | because this point is reached even if not optimizing. */ | |
294 | ||
295 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
296 | mark_home_live (i); | |
297 | ||
298 | /* Make sure that the last insn in the chain | |
299 | is not something that needs reloading. */ | |
300 | emit_note (0, NOTE_INSN_DELETED); | |
301 | ||
302 | /* Find all the pseudo registers that didn't get hard regs | |
303 | but do have known equivalent constants or memory slots. | |
304 | These include parameters (known equivalent to parameter slots) | |
305 | and cse'd or loop-moved constant memory addresses. | |
306 | ||
307 | Record constant equivalents in reg_equiv_constant | |
308 | so they will be substituted by find_reloads. | |
309 | Record memory equivalents in reg_mem_equiv so they can | |
310 | be substituted eventually by altering the REG-rtx's. */ | |
311 | ||
312 | reg_equiv_constant = (rtx *) alloca (max_regno * sizeof (rtx)); | |
313 | bzero (reg_equiv_constant, max_regno * sizeof (rtx)); | |
314 | reg_equiv_mem = (rtx *) alloca (max_regno * sizeof (rtx)); | |
315 | bzero (reg_equiv_mem, max_regno * sizeof (rtx)); | |
316 | reg_equiv_init = (rtx *) alloca (max_regno * sizeof (rtx)); | |
317 | bzero (reg_equiv_init, max_regno * sizeof (rtx)); | |
318 | reg_equiv_address = (rtx *) alloca (max_regno * sizeof (rtx)); | |
319 | bzero (reg_equiv_address, max_regno * sizeof (rtx)); | |
320 | reg_max_ref_width = (int *) alloca (max_regno * sizeof (int)); | |
321 | bzero (reg_max_ref_width, max_regno * sizeof (int)); | |
322 | ||
323 | /* Look for REG_EQUIV notes; record what each pseudo is equivalent to. | |
324 | Also find all paradoxical subregs | |
325 | and find largest such for each pseudo. */ | |
326 | ||
327 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
328 | { | |
329 | if (GET_CODE (insn) == INSN | |
330 | && GET_CODE (PATTERN (insn)) == SET | |
331 | && GET_CODE (SET_DEST (PATTERN (insn))) == REG) | |
332 | { | |
333 | rtx note = find_reg_note (insn, REG_EQUIV, 0); | |
334 | if (note) | |
335 | { | |
336 | rtx x = XEXP (note, 0); | |
337 | i = REGNO (SET_DEST (PATTERN (insn))); | |
338 | if (i >= FIRST_PSEUDO_REGISTER) | |
339 | { | |
340 | if (GET_CODE (x) == MEM) | |
341 | { | |
342 | if (memory_address_p (GET_MODE (x), XEXP (x, 0))) | |
343 | reg_equiv_mem[i] = x; | |
344 | else | |
345 | reg_equiv_address[i] = XEXP (x, 0); | |
346 | } | |
347 | else if (immediate_operand (x, VOIDmode)) | |
348 | reg_equiv_constant[i] = x; | |
349 | else | |
350 | continue; | |
351 | reg_equiv_init[i] = insn; | |
352 | } | |
353 | } | |
354 | } | |
355 | if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN | |
356 | || GET_CODE (insn) == JUMP_INSN) | |
357 | scan_paradoxical_subregs (PATTERN (insn)); | |
358 | } | |
359 | ||
360 | /* Does this function require a frame pointer? */ | |
361 | ||
362 | frame_pointer_needed | |
363 | |= (! global || FRAME_POINTER_REQUIRED); | |
364 | ||
365 | if (! frame_pointer_needed) | |
366 | frame_pointer_needed | |
367 | = check_frame_pointer_required (reg_equiv_constant, | |
368 | reg_equiv_mem, reg_equiv_address); | |
369 | ||
370 | /* Alter each pseudo-reg rtx to contain its hard reg number. | |
371 | Delete initializations of pseudos that don't have hard regs | |
372 | and do have equivalents. | |
373 | Assign stack slots to the pseudos that lack hard regs or equivalents. */ | |
374 | ||
375 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
376 | alter_reg (i, -1); | |
377 | ||
378 | #ifndef REGISTER_CONSTRAINTS | |
379 | /* If all the pseudo regs have hard regs, | |
380 | except for those that are never referenced, | |
381 | we know that no reloads are needed. */ | |
382 | /* But that is not true if there are register constraints, since | |
383 | in that case some pseudos might be in the wrong kind of hard reg. */ | |
384 | ||
385 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
386 | if (reg_renumber[i] == -1 && reg_n_refs[i] != 0) | |
387 | break; | |
388 | ||
389 | if (i == max_regno && frame_pointer_needed && ! caller_save_needed) | |
390 | return; | |
391 | #endif | |
392 | ||
393 | /* Compute the order of preference for hard registers to spill. | |
394 | Store them by decreasing preference in potential_reload_regs. */ | |
395 | ||
396 | order_regs_for_reload (); | |
397 | ||
398 | /* So far, no hard regs have been spilled. */ | |
399 | n_spills = 0; | |
400 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
401 | { | |
402 | spill_reg_order[i] = -1; | |
403 | forbidden_regs[i] = -1; | |
404 | } | |
405 | ||
406 | if (caller_save_needed) | |
407 | frame_pointer_needed = 1; | |
408 | ||
409 | if (frame_pointer_needed) | |
410 | { | |
411 | forbidden_regs[FRAME_POINTER_REGNUM] = 1; | |
412 | spill_hard_reg (FRAME_POINTER_REGNUM, global, dumpfile); | |
413 | } | |
414 | ||
415 | if (global) | |
416 | { | |
417 | basic_block_needs = (char *)alloca (n_basic_blocks); | |
418 | bzero (basic_block_needs, n_basic_blocks); | |
419 | } | |
420 | ||
421 | /* This loop scans the entire function each go-round | |
422 | and repeats until one repetition spills no additional hard regs. */ | |
423 | ||
424 | /* This flag is set when a psuedo reg is spilled, | |
425 | to require another pass. Note that getting an additional reload | |
426 | reg does not necessarily imply any pseudo reg was spilled; | |
427 | sometimes we find a reload reg that no pseudo reg was allocated in. */ | |
428 | something_changed = 1; | |
429 | /* This flag is set if there are any insns that require reloading. */ | |
430 | something_needs_reloads = 0; | |
431 | while (something_changed) | |
432 | { | |
433 | /* For each class, number of reload regs needed in that class. | |
434 | This is the maximum over all insns of the needs in that class | |
435 | of the individual insn. */ | |
436 | int max_needs[N_REG_CLASSES]; | |
437 | /* For each class, size of group of consecutive regs | |
438 | that is needed for the reloads of this class. */ | |
439 | int group_size[N_REG_CLASSES]; | |
440 | /* For each class, max number of consecutive groups needed. | |
441 | (Each group contains max_needs_size[CLASS] consecutive registers.) */ | |
442 | int max_groups[N_REG_CLASSES]; | |
443 | /* For each class, max number needed of regs that don't belong | |
444 | to any of the groups. */ | |
445 | int max_nongroups[N_REG_CLASSES]; | |
446 | /* For each class, the machine mode which requires consecutive | |
447 | groups of regs of that class. | |
448 | If two different modes ever require groups of one class, | |
449 | they must be the same size and equally restrictive for that class, | |
450 | otherwise we can't handle the complexity. */ | |
451 | enum machine_mode group_mode[N_REG_CLASSES]; | |
452 | ||
453 | something_changed = 0; | |
454 | bzero (max_needs, sizeof max_needs); | |
455 | bzero (max_groups, sizeof max_groups); | |
456 | bzero (max_nongroups, sizeof max_nongroups); | |
457 | bzero (group_size, sizeof group_size); | |
458 | for (i = 0; i < N_REG_CLASSES; i++) | |
459 | group_mode[i] = VOIDmode; | |
460 | ||
461 | /* Keep track of which basic blocks are needing the reloads. */ | |
462 | this_block = 0; | |
463 | ||
464 | /* Remember whether any element of basic_block_needs | |
465 | changes from 0 to 1 in this pass. */ | |
466 | new_basic_block_needs = 0; | |
467 | ||
468 | /* Compute the most additional registers needed by any instruction. | |
469 | Collect information separately for each class of regs. */ | |
470 | ||
471 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
472 | { | |
473 | rtx after_call = 0; | |
474 | ||
475 | if (global && this_block + 1 < n_basic_blocks | |
476 | && insn == basic_block_head[this_block+1]) | |
477 | ++this_block; | |
478 | ||
479 | if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN | |
480 | || GET_CODE (insn) == CALL_INSN) | |
481 | { | |
482 | /* Nonzero means don't use a reload reg that overlaps | |
483 | the place where a function value can be returned. */ | |
484 | rtx avoid_return_reg = 0; | |
485 | /* Initially, count RELOAD_OTHER reloads. | |
486 | Later, merge in the other kinds. */ | |
487 | int insn_needs[N_REG_CLASSES]; | |
488 | int insn_groups[N_REG_CLASSES]; | |
489 | int insn_total_groups = 0; | |
490 | ||
491 | /* Count RELOAD_FOR_INPUT_RELOAD_ADDRESS reloads. */ | |
492 | int insn_needs_for_inputs[N_REG_CLASSES]; | |
493 | int insn_groups_for_inputs[N_REG_CLASSES]; | |
494 | int insn_total_groups_for_inputs = 0; | |
495 | ||
496 | /* Count RELOAD_FOR_OUTPUT_RELOAD_ADDRESS reloads. */ | |
497 | int insn_needs_for_outputs[N_REG_CLASSES]; | |
498 | int insn_groups_for_outputs[N_REG_CLASSES]; | |
499 | int insn_total_groups_for_outputs = 0; | |
500 | ||
501 | /* Count RELOAD_FOR_OPERAND_ADDRESS reloads. */ | |
502 | int insn_needs_for_operands[N_REG_CLASSES]; | |
503 | int insn_groups_for_operands[N_REG_CLASSES]; | |
504 | int insn_total_groups_for_operands = 0; | |
505 | ||
506 | for (i = 0; i < N_REG_CLASSES; i++) | |
507 | { | |
508 | insn_needs[i] = 0, insn_groups[i] = 0; | |
509 | insn_needs_for_inputs[i] = 0, insn_groups_for_inputs[i] = 0; | |
510 | insn_needs_for_outputs[i] = 0, insn_groups_for_outputs[i] = 0; | |
511 | insn_needs_for_operands[i] = 0, insn_groups_for_operands[i] = 0; | |
512 | } | |
513 | ||
514 | #if 0 /* This wouldn't work nowadays, since optimize_bit_field | |
515 | looks for non-strict memory addresses. */ | |
516 | /* Optimization: a bit-field instruction whose field | |
517 | happens to be a byte or halfword in memory | |
518 | can be changed to a move instruction. */ | |
519 | ||
520 | if (GET_CODE (PATTERN (insn)) == SET) | |
521 | { | |
522 | rtx dest = SET_DEST (PATTERN (insn)); | |
523 | rtx src = SET_SRC (PATTERN (insn)); | |
524 | ||
525 | if (GET_CODE (dest) == ZERO_EXTRACT | |
526 | || GET_CODE (dest) == SIGN_EXTRACT) | |
527 | optimize_bit_field (PATTERN (insn), insn, reg_equiv_mem); | |
528 | if (GET_CODE (src) == ZERO_EXTRACT | |
529 | || GET_CODE (src) == SIGN_EXTRACT) | |
530 | optimize_bit_field (PATTERN (insn), insn, reg_equiv_mem); | |
531 | } | |
532 | #endif | |
533 | ||
534 | /* Set avoid_return_reg if this is an insn | |
535 | that might use the value of a function call. */ | |
536 | if (GET_CODE (insn) == CALL_INSN) | |
537 | { | |
538 | if (GET_CODE (PATTERN (insn)) == SET) | |
539 | after_call = SET_DEST (PATTERN (insn)); | |
540 | else if (GET_CODE (PATTERN (insn)) == PARALLEL | |
541 | && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET) | |
542 | after_call = SET_DEST (XVECEXP (PATTERN (insn), 0, 0)); | |
543 | else | |
544 | after_call = 0; | |
545 | } | |
546 | else if (after_call != 0 | |
547 | && !(GET_CODE (PATTERN (insn)) == SET | |
548 | && SET_DEST (PATTERN (insn)) == stack_pointer_rtx)) | |
549 | { | |
550 | if (reg_mentioned_p (after_call, PATTERN (insn))) | |
551 | avoid_return_reg = after_call; | |
552 | after_call = 0; | |
553 | } | |
554 | ||
555 | /* Analyze the instruction. */ | |
556 | ||
557 | find_reloads (insn, 0, spill_indirect_ok, global, spill_reg_order); | |
558 | ||
559 | if (n_reloads == 0) | |
560 | continue; | |
561 | ||
562 | something_needs_reloads = 1; | |
563 | ||
564 | /* Count each reload once in every class | |
565 | containing the reload's own class. */ | |
566 | ||
567 | for (i = 0; i < n_reloads; i++) | |
568 | { | |
569 | register enum reg_class *p; | |
570 | int size; | |
571 | enum machine_mode mode; | |
572 | int *this_groups; | |
573 | int *this_needs; | |
574 | int *this_total_groups; | |
575 | ||
576 | /* Don't use dummy reloads in regs | |
577 | being spilled in this block. */ | |
578 | if (reload_reg_rtx[i] != 0 | |
579 | && (!global || basic_block_needs[this_block]) | |
580 | && spill_reg_order[REGNO (reload_reg_rtx[i])] >= 0) | |
581 | reload_reg_rtx[i] = 0; | |
582 | ||
583 | /* Don't count the dummy reloads, for which one of the | |
584 | regs mentioned in the insn can be used for reloading. | |
585 | Don't count optional reloads. | |
586 | Don't count reloads that got combined with others. */ | |
587 | if (reload_reg_rtx[i] != 0 | |
588 | || reload_optional[i] != 0 | |
589 | || (reload_out[i] == 0 && reload_in[i] == 0)) | |
590 | continue; | |
591 | ||
592 | /* Decide which time-of-use to count this reload for. */ | |
593 | switch (reload_when_needed[i]) | |
594 | { | |
595 | case RELOAD_OTHER: | |
596 | this_needs = insn_needs; | |
597 | this_groups = insn_groups; | |
598 | this_total_groups = &insn_total_groups; | |
599 | break; | |
600 | ||
601 | case RELOAD_FOR_INPUT_RELOAD_ADDRESS: | |
602 | this_needs = insn_needs_for_inputs; | |
603 | this_groups = insn_groups_for_inputs; | |
604 | this_total_groups = &insn_total_groups_for_inputs; | |
605 | break; | |
606 | ||
607 | case RELOAD_FOR_OUTPUT_RELOAD_ADDRESS: | |
608 | this_needs = insn_needs_for_outputs; | |
609 | this_groups = insn_groups_for_outputs; | |
610 | this_total_groups = &insn_total_groups_for_outputs; | |
611 | break; | |
612 | ||
613 | case RELOAD_FOR_OPERAND_ADDRESS: | |
614 | this_needs = insn_needs_for_operands; | |
615 | this_groups = insn_groups_for_operands; | |
616 | this_total_groups = &insn_total_groups_for_operands; | |
617 | break; | |
618 | } | |
619 | ||
620 | mode = reload_inmode[i]; | |
621 | if (GET_MODE_SIZE (reload_outmode[i]) > GET_MODE_SIZE (mode)) | |
622 | mode = reload_outmode[i]; | |
623 | size = CLASS_MAX_NREGS (reload_reg_class[i], mode); | |
624 | if (size > 1) | |
625 | { | |
626 | /* Count number of groups needed separately from | |
627 | number of individual regs needed. */ | |
628 | this_groups[(int) reload_reg_class[i]]++; | |
629 | p = reg_class_superclasses[(int) reload_reg_class[i]]; | |
630 | while (*p != LIM_REG_CLASSES) | |
631 | this_groups[(int) *p++]++; | |
632 | (*this_total_groups)++; | |
633 | ||
634 | /* If a group of consecutive regs are needed, | |
635 | record which machine mode needs them. | |
636 | Crash if two dissimilar machine modes both need | |
637 | groups of consecutive regs of the same class. */ | |
638 | ||
639 | if (group_mode[(int) reload_reg_class[i]] != VOIDmode | |
640 | && | |
641 | (! modes_equiv_for_class_p (group_mode[(int) reload_reg_class[i]], mode, reload_reg_class[i]) | |
642 | || | |
643 | group_size[(int) reload_reg_class[i]] != size)) | |
644 | abort (); | |
645 | ||
646 | /* Record size and mode of a group of this class. */ | |
647 | group_size[(int) reload_reg_class[i]] = size; | |
648 | group_mode[(int) reload_reg_class[i]] = mode; | |
649 | } | |
650 | else if (size == 1) | |
651 | { | |
652 | this_needs[(int) reload_reg_class[i]] += 1; | |
653 | p = reg_class_superclasses[(int) reload_reg_class[i]]; | |
654 | while (*p != LIM_REG_CLASSES) | |
655 | this_needs[(int) *p++] += 1; | |
656 | } | |
657 | else | |
658 | abort (); | |
659 | ||
660 | if (global) | |
661 | { | |
662 | if (! basic_block_needs[this_block]) | |
663 | new_basic_block_needs = 1; | |
664 | basic_block_needs[this_block] = 1; | |
665 | } | |
666 | } | |
667 | ||
668 | /* All reloads have been counted for this insn; | |
669 | now merge the various times of use. | |
670 | This sets insn_needs, etc., to the maximum total number | |
671 | of registers needed at any point in this insn. */ | |
672 | ||
673 | for (i = 0; i < N_REG_CLASSES; i++) | |
674 | { | |
675 | int this_max; | |
676 | this_max = insn_needs_for_inputs[i]; | |
677 | if (insn_needs_for_outputs[i] > this_max) | |
678 | this_max = insn_needs_for_outputs[i]; | |
679 | if (insn_needs_for_operands[i] > this_max) | |
680 | this_max = insn_needs_for_operands[i]; | |
681 | insn_needs[i] += this_max; | |
682 | this_max = insn_groups_for_inputs[i]; | |
683 | if (insn_groups_for_outputs[i] > this_max) | |
684 | this_max = insn_groups_for_outputs[i]; | |
685 | if (insn_groups_for_operands[i] > this_max) | |
686 | this_max = insn_groups_for_operands[i]; | |
687 | insn_groups[i] += this_max; | |
688 | } | |
689 | insn_total_groups += max (insn_total_groups_for_inputs, | |
690 | max (insn_total_groups_for_outputs, | |
691 | insn_total_groups_for_operands)); | |
692 | ||
693 | /* Remember for later shortcuts which insns had any reloads. */ | |
694 | ||
695 | PUT_MODE (insn, n_reloads ? QImode : VOIDmode); | |
696 | ||
697 | /* If this insn stores the value of a function call, | |
698 | and that value is in a register that has been spilled, | |
699 | and if the insn needs a reload in a class | |
700 | that might use that register as the reload register, | |
701 | then add add an extra need in that class. | |
702 | This makes sure we have a register available that does | |
703 | not overlap the return value. */ | |
704 | if (avoid_return_reg) | |
705 | { | |
706 | int regno = REGNO (avoid_return_reg); | |
707 | int nregs | |
708 | = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg)); | |
709 | int r; | |
710 | int inc_groups = 0; | |
711 | for (r = regno; r < regno + nregs; r++) | |
712 | if (spill_reg_order[r] >= 0) | |
713 | for (i = 0; i < N_REG_CLASSES; i++) | |
714 | if (TEST_HARD_REG_BIT (reg_class_contents[i], r)) | |
715 | { | |
716 | if (insn_needs[i] > 0) | |
717 | insn_needs[i]++; | |
718 | if (insn_groups[i] > 0 | |
719 | && nregs > 1) | |
720 | inc_groups = 1; | |
721 | } | |
722 | if (inc_groups) | |
723 | insn_groups[i]++; | |
724 | } | |
725 | ||
726 | /* For each class, collect maximum need of any insn. */ | |
727 | ||
728 | for (i = 0; i < N_REG_CLASSES; i++) | |
729 | { | |
730 | if (max_needs[i] < insn_needs[i]) | |
731 | max_needs[i] = insn_needs[i]; | |
732 | if (max_groups[i] < insn_groups[i]) | |
733 | max_groups[i] = insn_groups[i]; | |
734 | if (insn_total_groups > 0) | |
735 | if (max_nongroups[i] < insn_needs[i]) | |
736 | max_nongroups[i] = insn_needs[i]; | |
737 | } | |
738 | } | |
739 | /* Note that there is a continue statement above. */ | |
740 | } | |
741 | ||
742 | /* Now deduct from the needs for the registers already | |
743 | available (already spilled). */ | |
744 | ||
745 | bzero (counted_for_groups, sizeof counted_for_groups); | |
746 | bzero (counted_for_nongroups, sizeof counted_for_nongroups); | |
747 | ||
748 | /* Find all consecutive groups of spilled registers | |
749 | and mark each group off against the need for such groups. */ | |
750 | ||
751 | for (i = 0; i < N_REG_CLASSES; i++) | |
752 | if (group_size[i] > 1) | |
753 | { | |
754 | char regmask[FIRST_PSEUDO_REGISTER]; | |
755 | int j; | |
756 | ||
757 | bzero (regmask, sizeof regmask); | |
758 | /* Make a mask of all the regs that are spill regs in class I. */ | |
759 | for (j = 0; j < n_spills; j++) | |
760 | if (TEST_HARD_REG_BIT (reg_class_contents[i], spill_regs[j]) | |
761 | && !counted_for_groups[spill_regs[j]]) | |
762 | regmask[spill_regs[j]] = 1; | |
763 | /* Find each consecutive group of them. */ | |
764 | for (j = 0; j < FIRST_PSEUDO_REGISTER && max_groups[i] > 0; j++) | |
765 | if (regmask[j] && j + group_size[i] <= FIRST_PSEUDO_REGISTER | |
766 | /* Next line in case group-mode for this class | |
767 | demands an even-odd pair. */ | |
768 | && HARD_REGNO_MODE_OK (j, group_mode[i])) | |
769 | { | |
770 | int k; | |
771 | for (k = 1; k < group_size[i]; k++) | |
772 | if (! regmask[j + k]) | |
773 | break; | |
774 | if (k == group_size[i]) | |
775 | { | |
776 | /* We found a group. Mark it off against this class's | |
777 | need for groups, and against each superclass too. */ | |
778 | register enum reg_class *p; | |
779 | max_groups[i]--; | |
780 | p = reg_class_superclasses[i]; | |
781 | while (*p != LIM_REG_CLASSES) | |
782 | max_groups[(int) *p++]--; | |
783 | /* Don't count these registers again. */ | |
784 | counted_for_groups[j] = 1; | |
785 | for (k = 1; k < group_size[i]; k++) | |
786 | counted_for_groups[j + k] = 1; | |
787 | } | |
788 | j += k; | |
789 | } | |
790 | } | |
791 | ||
792 | /* Now count all remaining spill regs against the individual need. | |
793 | Those that weren't counted_for_groups in groups can also count against | |
794 | the not-in-group need. */ | |
795 | ||
796 | for (i = 0; i < n_spills; i++) | |
797 | { | |
798 | register enum reg_class *p; | |
799 | class = (int) REGNO_REG_CLASS (spill_regs[i]); | |
800 | ||
801 | max_needs[class]--; | |
802 | p = reg_class_superclasses[class]; | |
803 | while (*p != LIM_REG_CLASSES) | |
804 | max_needs[(int) *p++]--; | |
805 | ||
806 | if (! counted_for_groups[spill_regs[i]]) | |
807 | { | |
808 | if (max_nongroups[class] > 0) | |
809 | counted_for_nongroups[spill_regs[i]] = 1; | |
810 | max_nongroups[class]--; | |
811 | p = reg_class_superclasses[class]; | |
812 | while (*p != LIM_REG_CLASSES) | |
813 | { | |
814 | if (max_nongroups[(int) *p] > 0) | |
815 | counted_for_nongroups[spill_regs[i]] = 1; | |
816 | max_nongroups[(int) *p++]--; | |
817 | } | |
818 | } | |
819 | } | |
820 | ||
821 | /* If all needs are met, we win. */ | |
822 | ||
823 | for (i = 0; i < N_REG_CLASSES; i++) | |
824 | if (max_needs[i] > 0 || max_groups[i] > 0 || max_nongroups[i] > 0) | |
825 | break; | |
826 | if (i == N_REG_CLASSES && !new_basic_block_needs) | |
827 | break; | |
828 | ||
829 | /* Not all needs are met; must spill more hard regs. */ | |
830 | ||
831 | /* If any element of basic_block_needs changed from 0 to 1, | |
832 | re-spill all the regs already spilled. This may spill | |
833 | additional pseudos that didn't spill before. */ | |
834 | ||
835 | if (new_basic_block_needs) | |
836 | for (i = 0; i < n_spills; i++) | |
837 | something_changed | |
838 | |= spill_hard_reg (spill_regs[i], global, dumpfile); | |
839 | ||
840 | /* Now find more reload regs to satisfy the remaining need | |
841 | Do it by ascending class number, since otherwise a reg | |
842 | might be spilled for a big class and might fail to count | |
843 | for a smaller class even though it belongs to that class. | |
844 | ||
845 | Count spilled regs in `spills', and add entries to | |
846 | `spill_regs' and `spill_reg_order'. */ | |
847 | ||
848 | for (class = 0; class < N_REG_CLASSES; class++) | |
849 | { | |
850 | /* First get the groups of registers. | |
851 | If we got single registers first, we might fragment | |
852 | possible groups. */ | |
853 | while (max_groups[class] > 0) | |
854 | { | |
855 | /* Groups of size 2 (the only groups used on most machines) | |
856 | are treated specially. */ | |
857 | if (group_size[class] == 2) | |
858 | { | |
859 | /* First, look for a register that will complete a group. */ | |
860 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
861 | { | |
862 | int j = potential_reload_regs[i]; | |
863 | int other; | |
864 | if (j >= 0 && !fixed_regs[j] && j != FRAME_POINTER_REGNUM | |
865 | && !regs_explicitly_used[j] | |
866 | && | |
867 | ((j > 0 && (other = j - 1, spill_reg_order[other] >= 0) | |
868 | && TEST_HARD_REG_BIT (reg_class_contents[class], j) | |
869 | && TEST_HARD_REG_BIT (reg_class_contents[class], other) | |
870 | && HARD_REGNO_MODE_OK (other, group_mode[class]) | |
871 | && ! counted_for_nongroups[other] | |
872 | /* We don't want one part of another group. | |
873 | We could get "two groups" that overlap! */ | |
874 | && ! counted_for_groups[other]) | |
875 | ||
876 | || | |
877 | (j < FIRST_PSEUDO_REGISTER - 1 | |
878 | && (other = j + 1, spill_reg_order[other] >= 0) | |
879 | && TEST_HARD_REG_BIT (reg_class_contents[class], j) | |
880 | && TEST_HARD_REG_BIT (reg_class_contents[class], other) | |
881 | && HARD_REGNO_MODE_OK (j, group_mode[class]) | |
882 | && ! counted_for_nongroups[other] | |
883 | && ! counted_for_groups[other]))) | |
884 | { | |
885 | register enum reg_class *p; | |
886 | ||
887 | /* We have found one that will complete a group, | |
888 | so count off one group as provided. */ | |
889 | max_groups[class]--; | |
890 | p = reg_class_superclasses[class]; | |
891 | while (*p != LIM_REG_CLASSES) | |
892 | max_groups[(int) *p++]--; | |
893 | ||
894 | /* Indicate both these regs are part of a group. */ | |
895 | counted_for_groups[j] = 1; | |
896 | counted_for_groups[other] = 1; | |
897 | ||
898 | break; | |
899 | } | |
900 | } | |
901 | /* We can't complete a group, so start one. */ | |
902 | if (i == FIRST_PSEUDO_REGISTER) | |
903 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
904 | { | |
905 | int j = potential_reload_regs[i]; | |
906 | if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER | |
907 | && !fixed_regs[j] && j != FRAME_POINTER_REGNUM | |
908 | && spill_reg_order[j] < 0 && spill_reg_order[j + 1] < 0 | |
909 | && TEST_HARD_REG_BIT (reg_class_contents[class], j) | |
910 | && TEST_HARD_REG_BIT (reg_class_contents[class], j + 1) | |
911 | && HARD_REGNO_MODE_OK (j, group_mode[class]) | |
912 | && ! counted_for_nongroups[j + 1]) | |
913 | break; | |
914 | } | |
915 | ||
916 | /* I should be the index in potential_reload_regs | |
917 | of the new reload reg we have found. */ | |
918 | ||
919 | something_changed | |
920 | |= new_spill_reg (i, class, max_needs, 0, | |
921 | global, dumpfile); | |
922 | } | |
923 | else | |
924 | { | |
925 | /* For groups of more than 2 registers, | |
926 | look for a sufficient sequence of unspilled registers, | |
927 | and spill them all at once. */ | |
928 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
929 | { | |
930 | int j = potential_reload_regs[i]; | |
931 | int k; | |
932 | if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER | |
933 | && HARD_REGNO_MODE_OK (j, group_mode[class])) | |
934 | { | |
935 | /* Check each reg in the sequence. */ | |
936 | for (k = 0; k < group_size[class]; k++) | |
937 | if (! (spill_reg_order[j + k] < 0 | |
938 | && !fixed_regs[j + k] | |
939 | && j + k != FRAME_POINTER_REGNUM | |
940 | && TEST_HARD_REG_BIT (reg_class_contents[class], j + k))) | |
941 | break; | |
942 | /* We got a full sequence, so spill them all. */ | |
943 | if (k == group_size[class]) | |
944 | { | |
945 | register enum reg_class *p; | |
946 | for (k = 0; k < group_size[class]; k++) | |
947 | { | |
948 | int idx; | |
949 | counted_for_groups[j + k] = 1; | |
950 | for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++) | |
951 | if (potential_reload_regs[idx] == j + k) | |
952 | break; | |
953 | something_changed | |
954 | |= new_spill_reg (idx, class, max_needs, 0, | |
955 | global, dumpfile); | |
956 | } | |
957 | ||
958 | /* We have found one that will complete a group, | |
959 | so count off one group as provided. */ | |
960 | max_groups[class]--; | |
961 | p = reg_class_superclasses[class]; | |
962 | while (*p != LIM_REG_CLASSES) | |
963 | max_groups[(int) *p++]--; | |
964 | ||
965 | break; | |
966 | } | |
967 | } | |
968 | } | |
969 | } | |
970 | } | |
971 | ||
972 | /* Now similarly satisfy all need for single registers. */ | |
973 | ||
974 | while (max_needs[class] > 0 || max_nongroups[class] > 0) | |
975 | { | |
976 | /* Consider the potential reload regs that aren't | |
977 | yet in use as reload regs, in order of preference. | |
978 | Find the most preferred one that's in this class. */ | |
979 | ||
980 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
981 | if (potential_reload_regs[i] >= 0 | |
982 | && TEST_HARD_REG_BIT (reg_class_contents[class], | |
983 | potential_reload_regs[i])) | |
984 | break; | |
985 | ||
986 | /* I should be the index in potential_reload_regs | |
987 | of the new reload reg we have found. */ | |
988 | ||
989 | something_changed | |
990 | |= new_spill_reg (i, class, max_needs, max_nongroups, | |
991 | global, dumpfile); | |
992 | } | |
993 | } | |
994 | } | |
995 | ||
996 | /* Insert code to save and restore call-clobbered hard regs | |
997 | around calls. */ | |
998 | ||
999 | if (caller_save_needed) | |
1000 | save_call_clobbered_regs (); | |
1001 | ||
1002 | /* Now we know for certain whether we have a frame pointer. | |
1003 | If not, correct all references to go through the stack pointer. | |
1004 | This must be done before reloading, since reloading could generate | |
1005 | insns where sp+const cannot validly replace the frame pointer. | |
1006 | *This will lose if an insn might need more spill regs after | |
1007 | frame pointer elimination than it needed before.* */ | |
1008 | ||
1009 | if (! frame_pointer_needed) | |
1010 | eliminate_frame_pointer (first); | |
1011 | ||
1012 | /* Use the reload registers where necessary | |
1013 | by generating move instructions to move the must-be-register | |
1014 | values into or out of the reload registers. */ | |
1015 | ||
1016 | if (something_needs_reloads) | |
1017 | reload_as_needed (first, global); | |
1018 | ||
1019 | /* Now eliminate all pseudo regs by modifying them into | |
1020 | their equivalent memory references. | |
1021 | The REG-rtx's for the pseudos are modified in place, | |
1022 | so all insns that used to refer to them now refer to memory. | |
1023 | ||
1024 | For a reg that has a reg_equiv_address, all those insns | |
1025 | were changed by reloading so that no insns refer to it any longer; | |
1026 | but the DECL_RTL of a variable decl may refer to it, | |
1027 | and if so this causes the debugging info to mention the variable. */ | |
1028 | ||
1029 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
1030 | { | |
1031 | rtx addr = 0; | |
1032 | if (reg_equiv_mem[i]) | |
1033 | addr = XEXP (reg_equiv_mem[i], 0); | |
1034 | if (reg_equiv_address[i]) | |
1035 | addr = reg_equiv_address[i]; | |
1036 | if (addr) | |
1037 | { | |
1038 | if (! frame_pointer_needed) | |
1039 | FIX_FRAME_POINTER_ADDRESS (addr, 0); | |
1040 | if (reg_renumber[i] < 0) | |
1041 | { | |
1042 | rtx reg = regno_reg_rtx[i]; | |
1043 | XEXP (reg, 0) = addr; | |
1044 | REG_USERVAR_P (reg) = 0; | |
1045 | PUT_CODE (reg, MEM); | |
1046 | } | |
1047 | else if (reg_equiv_mem[i]) | |
1048 | XEXP (reg_equiv_mem[i], 0) = addr; | |
1049 | } | |
1050 | } | |
1051 | } | |
1052 | \f | |
1053 | /* 1 if two machine modes MODE0 and MODE1 are equivalent | |
1054 | as far as HARD_REGNO_MODE_OK is concerned | |
1055 | for registers in class CLASS. */ | |
1056 | ||
1057 | static int | |
1058 | modes_equiv_for_class_p (mode0, mode1, class) | |
1059 | enum machine_mode mode0, mode1; | |
1060 | enum reg_class class; | |
1061 | { | |
1062 | register int regno; | |
1063 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
1064 | { | |
1065 | /* If any reg in CLASS allows one mode but not the other, fail. | |
1066 | Or if the two modes have different sizes in that reg, fail. */ | |
1067 | if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno) | |
1068 | && (HARD_REGNO_MODE_OK (regno, mode0) | |
1069 | != HARD_REGNO_MODE_OK (regno, mode1)) | |
1070 | && (HARD_REGNO_NREGS (regno, mode0) | |
1071 | != HARD_REGNO_NREGS (regno, mode1))) | |
1072 | return 0; | |
1073 | } | |
1074 | return 1; | |
1075 | } | |
1076 | ||
1077 | /* Add a new register to the tables of available spill-registers | |
1078 | (as well as spilling all pseudos allocated to the register). | |
1079 | I is the index of this register in potential_reload_regs. | |
1080 | CLASS is the regclass whose need is being satisfied. | |
1081 | MAX_NEEDS and MAX_NONGROUPS are the vectors of needs, | |
1082 | so that this register can count off against them. | |
1083 | MAX_NONGROUPS is 0 if this register is part of a group. | |
1084 | GLOBAL and DUMPFILE are the same as the args that `reload' got. */ | |
1085 | ||
1086 | static int | |
1087 | new_spill_reg (i, class, max_needs, max_nongroups, global, dumpfile) | |
1088 | int i; | |
1089 | int class; | |
1090 | int *max_needs; | |
1091 | int *max_nongroups; | |
1092 | int global; | |
1093 | FILE *dumpfile; | |
1094 | { | |
1095 | register enum reg_class *p; | |
1096 | int val; | |
1097 | int regno = potential_reload_regs[i]; | |
1098 | ||
1099 | if (i >= FIRST_PSEUDO_REGISTER) | |
1100 | abort (); /* Caller failed to find any register. */ | |
1101 | ||
1102 | /* Make reg REGNO an additional reload reg. */ | |
1103 | ||
1104 | potential_reload_regs[i] = -1; | |
1105 | spill_regs[n_spills] = regno; | |
1106 | spill_reg_order[regno] = n_spills; | |
1107 | forbidden_regs[regno] = 1; | |
1108 | if (dumpfile) | |
1109 | fprintf (dumpfile, "Spilling reg %d.\n", spill_regs[n_spills]); | |
1110 | ||
1111 | /* Clear off the needs we just satisfied. */ | |
1112 | ||
1113 | max_needs[class]--; | |
1114 | p = reg_class_superclasses[class]; | |
1115 | while (*p != LIM_REG_CLASSES) | |
1116 | max_needs[(int) *p++]--; | |
1117 | ||
1118 | if (max_nongroups && max_nongroups[class] > 0) | |
1119 | { | |
1120 | counted_for_nongroups[regno] = 1; | |
1121 | max_nongroups[class]--; | |
1122 | p = reg_class_superclasses[class]; | |
1123 | while (*p != LIM_REG_CLASSES) | |
1124 | max_nongroups[(int) *p++]--; | |
1125 | } | |
1126 | ||
1127 | /* Spill every pseudo reg that was allocated to this reg | |
1128 | or to something that overlaps this reg. */ | |
1129 | ||
1130 | val = spill_hard_reg (spill_regs[n_spills], global, dumpfile); | |
1131 | ||
1132 | regs_ever_live[spill_regs[n_spills]] = 1; | |
1133 | n_spills++; | |
1134 | ||
1135 | return val; | |
1136 | } | |
1137 | \f | |
1138 | /* Scan all insns, computing the stack depth, and convert all | |
1139 | frame-pointer-relative references to stack-pointer-relative references. */ | |
1140 | ||
1141 | static void | |
1142 | eliminate_frame_pointer (first) | |
1143 | rtx first; | |
1144 | { | |
1145 | int depth = 0; | |
1146 | int max_uid = get_max_uid (); | |
1147 | int *label_depth = (int *) alloca ((max_uid + 1) * sizeof (int)); | |
1148 | int i; | |
1149 | rtx insn; | |
1150 | ||
1151 | for (i = 0; i <= max_uid; i++) | |
1152 | label_depth[i] = -1; | |
1153 | ||
1154 | /* In this loop, for each forward branch we record the stack | |
1155 | depth of the label it jumps to. We take advantage of the fact | |
1156 | that the stack depth at a label reached by a backward branch | |
1157 | is always, in GCC output, equal to the stack depth of the preceding | |
1158 | unconditional jump, because it was either a loop statement or | |
1159 | statement label. */ | |
1160 | ||
1161 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
1162 | { | |
1163 | rtx pattern = PATTERN (insn); | |
1164 | switch (GET_CODE (insn)) | |
1165 | { | |
1166 | case INSN: | |
1167 | frame_pointer_address_altered = 0; | |
1168 | alter_frame_pointer_addresses (pattern, depth); | |
1169 | /* Rerecognize insn if changed. */ | |
1170 | if (frame_pointer_address_altered) | |
1171 | INSN_CODE (insn) = -1; | |
1172 | ||
1173 | /* Notice pushes and pops; update DEPTH. */ | |
1174 | if (GET_CODE (pattern) == SET) | |
1175 | { | |
1176 | #ifdef PUSH_ROUNDING | |
1177 | if (push_operand (SET_DEST (pattern), | |
1178 | GET_MODE (SET_DEST (pattern)))) | |
1179 | depth += PUSH_ROUNDING (GET_MODE_SIZE (GET_MODE (SET_DEST (pattern)))); | |
1180 | #endif | |
1181 | if (GET_CODE (SET_DEST (pattern)) == REG | |
1182 | && REGNO (SET_DEST (pattern)) == STACK_POINTER_REGNUM) | |
1183 | { | |
1184 | int delta; | |
1185 | if (GET_CODE (SET_SRC (pattern)) == PLUS | |
1186 | && GET_CODE (XEXP (SET_SRC (pattern), 0)) == REG | |
1187 | && REGNO (XEXP (SET_SRC (pattern), 0)) == STACK_POINTER_REGNUM) | |
1188 | delta = INTVAL (XEXP (SET_SRC (pattern), 1)); | |
1189 | else if (GET_CODE (SET_SRC (pattern)) == MINUS | |
1190 | && GET_CODE (XEXP (SET_SRC (pattern), 0)) == REG | |
1191 | && REGNO (XEXP (SET_SRC (pattern), 0)) == STACK_POINTER_REGNUM) | |
1192 | delta = -INTVAL (XEXP (SET_SRC (pattern), 1)); | |
1193 | else abort (); | |
1194 | #ifdef STACK_GROWS_DOWNWARD | |
1195 | depth -= delta; | |
1196 | #else | |
1197 | depth += delta; | |
1198 | #endif | |
1199 | } | |
1200 | } | |
1201 | break; | |
1202 | ||
1203 | case JUMP_INSN: | |
1204 | frame_pointer_address_altered = 0; | |
1205 | alter_frame_pointer_addresses (pattern, depth); | |
1206 | /* Rerecognize insn if changed. */ | |
1207 | if (frame_pointer_address_altered) | |
1208 | INSN_CODE (insn) = -1; | |
1209 | ||
1210 | if (GET_CODE (pattern) == ADDR_VEC) | |
1211 | for (i = 0; i < XVECLEN (pattern, 0); i++) | |
1212 | label_depth[INSN_UID (XEXP (XVECEXP (pattern, 0, i), 0))] = depth; | |
1213 | else if (GET_CODE (pattern) == ADDR_DIFF_VEC) | |
1214 | { | |
1215 | label_depth[INSN_UID (XEXP (XEXP (pattern, 0), 0))] = depth; | |
1216 | for (i = 0; i < XVECLEN (pattern, 1); i++) | |
1217 | label_depth[INSN_UID (XEXP (XVECEXP (pattern, 1, i), 0))] = depth; | |
1218 | } | |
1219 | else if (JUMP_LABEL (insn)) | |
1220 | label_depth[INSN_UID (JUMP_LABEL (insn))] = depth; | |
1221 | else | |
1222 | break; | |
1223 | ||
1224 | case CODE_LABEL: | |
1225 | if (label_depth [INSN_UID (insn)] >= 0) | |
1226 | depth = label_depth [INSN_UID (insn)]; | |
1227 | break; | |
1228 | ||
1229 | case CALL_INSN: | |
1230 | frame_pointer_address_altered = 0; | |
1231 | alter_frame_pointer_addresses (pattern, depth); | |
1232 | /* Rerecognize insn if changed. */ | |
1233 | if (frame_pointer_address_altered) | |
1234 | INSN_CODE (insn) = -1; | |
1235 | break; | |
1236 | } | |
1237 | } | |
1238 | } | |
1239 | \f | |
1240 | /* Walk the rtx X, converting all frame-pointer refs to stack-pointer refs | |
1241 | on the assumption that the current temporary stack depth is DEPTH. | |
1242 | (The size of saved registers must be added to DEPTH | |
1243 | to get the actual offset between the logical frame-pointer and the | |
1244 | stack pointer. FIX_FRAME_POINTER_ADDRESS takes care of that.) */ | |
1245 | ||
1246 | static rtx | |
1247 | alter_frame_pointer_addresses (x, depth) | |
1248 | register rtx x; | |
1249 | int depth; | |
1250 | { | |
1251 | register int i; | |
1252 | register char *fmt; | |
1253 | register enum rtx_code code = GET_CODE (x); | |
1254 | ||
1255 | switch (code) | |
1256 | { | |
1257 | case CONST_INT: | |
1258 | case CONST: | |
1259 | case SYMBOL_REF: | |
1260 | case LABEL_REF: | |
1261 | case CONST_DOUBLE: | |
1262 | case CC0: | |
1263 | case PC: | |
1264 | return x; | |
1265 | ||
1266 | case REG: | |
1267 | /* Frame ptr can occur outside a PLUS if a stack slot | |
1268 | can occur with offset 0. */ | |
1269 | if (x == frame_pointer_rtx) | |
1270 | { | |
1271 | rtx oldx = x; | |
1272 | FIX_FRAME_POINTER_ADDRESS (x, depth); | |
1273 | if (x != oldx) | |
1274 | frame_pointer_address_altered = 1; | |
1275 | } | |
1276 | return x; | |
1277 | ||
1278 | case MEM: | |
1279 | { | |
1280 | rtx addr = XEXP (x, 0); | |
1281 | rtx mem; | |
1282 | rtx old_addr = addr; | |
1283 | FIX_FRAME_POINTER_ADDRESS (addr, depth); | |
1284 | if (addr != old_addr) | |
1285 | frame_pointer_address_altered = 1; | |
1286 | /* These MEMs are normally shared. Make a changed copy; | |
1287 | don't alter the shared MEM, since it needs to be altered | |
1288 | differently each time it occurs (since DEPTH varies). */ | |
1289 | mem = gen_rtx (MEM, GET_MODE (x), addr); | |
1290 | MEM_VOLATILE_P (mem) = MEM_VOLATILE_P (x); | |
1291 | return mem; | |
1292 | } | |
1293 | ||
1294 | case PLUS: | |
1295 | { | |
1296 | rtx oldx = x; | |
1297 | /* Handle addresses being loaded or pushed, etc., | |
1298 | rather than referenced. */ | |
1299 | FIX_FRAME_POINTER_ADDRESS (x, depth); | |
1300 | if (x != oldx) | |
1301 | frame_pointer_address_altered = 1; | |
1302 | code = GET_CODE (x); | |
1303 | break; | |
1304 | } | |
1305 | } | |
1306 | ||
1307 | fmt = GET_RTX_FORMAT (code); | |
1308 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1309 | { | |
1310 | if (fmt[i] == 'e') | |
1311 | XEXP (x, i) = alter_frame_pointer_addresses (XEXP (x, i), depth); | |
1312 | else if (fmt[i] == 'E') | |
1313 | { | |
1314 | register int j; | |
1315 | for (j = XVECLEN (x, i) - 1; j >=0; j--) | |
1316 | XVECEXP (x, i, j) | |
1317 | = alter_frame_pointer_addresses (XVECEXP (x, i, j), depth); | |
1318 | } | |
1319 | } | |
1320 | return x; | |
1321 | } | |
1322 | \f | |
1323 | /* Modify the home of pseudo-reg I. | |
1324 | The new home is present in reg_renumber[I]. | |
1325 | ||
1326 | FROM_REG may be the hard reg that the pseudo-reg is being spilled from; | |
1327 | or it may be -1, meaning there is none or it is not relevant. | |
1328 | This is used so that all pseudos spilled from a given hard reg | |
1329 | can share one stack slot. */ | |
1330 | ||
1331 | static void | |
1332 | alter_reg (i, from_reg) | |
1333 | register int i; | |
1334 | int from_reg; | |
1335 | { | |
1336 | /* When outputting an inline function, this can happen | |
1337 | for a reg that isn't actually used. */ | |
1338 | if (regno_reg_rtx[i] == 0) | |
1339 | return; | |
1340 | ||
1341 | /* If the reg got changed to a MEM at rtl-generation time, | |
1342 | ignore it. */ | |
1343 | if (GET_CODE (regno_reg_rtx[i]) != REG) | |
1344 | return; | |
1345 | ||
1346 | /* Modify the reg-rtx to contain the new hard reg | |
1347 | number or else to contain its pseudo reg number. */ | |
1348 | REGNO (regno_reg_rtx[i]) | |
1349 | = reg_renumber[i] >= 0 ? reg_renumber[i] : i; | |
1350 | ||
1351 | if (reg_renumber[i] < 0 && reg_equiv_init[i]) | |
1352 | { | |
1353 | /* Delete the insn that loads the pseudo register. */ | |
1354 | PUT_CODE (reg_equiv_init[i], NOTE); | |
1355 | NOTE_LINE_NUMBER (reg_equiv_init[i]) | |
1356 | = NOTE_INSN_DELETED; | |
1357 | NOTE_SOURCE_FILE (reg_equiv_init[i]) = 0; | |
1358 | } | |
1359 | ||
1360 | /* If we have a pseudo that is needed but has no hard reg or equivalent, | |
1361 | allocate a stack slot for it. */ | |
1362 | ||
1363 | if (reg_renumber[i] < 0 | |
1364 | && reg_n_refs[i] > 0 | |
1365 | && reg_equiv_constant[i] == 0 | |
1366 | && reg_equiv_mem[i] == 0 | |
1367 | && reg_equiv_address[i] == 0) | |
1368 | { | |
1369 | register rtx x, addr; | |
1370 | int inherent_size = PSEUDO_REGNO_BYTES (i); | |
1371 | int total_size = max (inherent_size, reg_max_ref_width[i]); | |
1372 | ||
1373 | /* Each pseudo reg has an inherent size which comes from its own mode, | |
1374 | and a total size which provides room for paradoxical subregs | |
1375 | which refer to the pseudo reg in wider modes. | |
1376 | ||
1377 | We can use a slot already allocated if it provides both | |
1378 | enough inherent space and enough total space. | |
1379 | Otherwise, we allocate a new slot, making sure that it has no less | |
1380 | inherent space, and no less total space, then the previous slot. */ | |
1381 | if (from_reg == -1) | |
1382 | { | |
1383 | /* No known place to spill from => no slot to reuse. */ | |
1384 | x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size); | |
1385 | #ifdef BYTES_BIG_ENDIAN | |
1386 | /* Cancel the big-endian correction done in assign_stack_local. | |
1387 | Get the address of the beginning of the slot. | |
1388 | This is so we can do a big-endian correction unconditionally | |
1389 | below. */ | |
1390 | x = gen_rtx (MEM, GET_MODE (regno_reg_rtx[i]), | |
1391 | plus_constant (XEXP (x, 0), | |
1392 | inherent_size - total_size)); | |
1393 | #endif | |
1394 | } | |
1395 | /* Reuse a stack slot if possible. */ | |
1396 | else if (spill_stack_slot[from_reg] != 0 | |
1397 | && spill_stack_slot_width[from_reg] >= total_size | |
1398 | && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg])) | |
1399 | >= inherent_size)) | |
1400 | x = spill_stack_slot[from_reg]; | |
1401 | /* Allocate a new or bigger slot. */ | |
1402 | else | |
1403 | { | |
1404 | /* Compute maximum size needed, both for inherent size | |
1405 | and for total size. */ | |
1406 | enum machine_mode mode = GET_MODE (regno_reg_rtx[i]); | |
1407 | if (spill_stack_slot[from_reg]) | |
1408 | { | |
1409 | if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg])) | |
1410 | > inherent_size) | |
1411 | mode = GET_MODE (spill_stack_slot[from_reg]); | |
1412 | if (spill_stack_slot_width[from_reg] > total_size) | |
1413 | total_size = spill_stack_slot_width[from_reg]; | |
1414 | } | |
1415 | /* Make a slot with that size. */ | |
1416 | x = assign_stack_local (mode, total_size); | |
1417 | #ifdef BYTES_BIG_ENDIAN | |
1418 | /* Cancel the big-endian correction done in assign_stack_local. | |
1419 | Get the address of the beginning of the slot. | |
1420 | This is so we can do a big-endian correction unconditionally | |
1421 | below. */ | |
1422 | x = gen_rtx (MEM, mode, | |
1423 | plus_constant (XEXP (x, 0), | |
1424 | GET_MODE_SIZE (mode) - total_size)); | |
1425 | #endif | |
1426 | spill_stack_slot[from_reg] = x; | |
1427 | spill_stack_slot_width[from_reg] = total_size; | |
1428 | } | |
1429 | ||
1430 | #ifdef BYTES_BIG_ENDIAN | |
1431 | /* On a big endian machine, the "address" of the slot | |
1432 | is the address of the low part that fits its inherent mode. */ | |
1433 | if (inherent_size < total_size) | |
1434 | x = gen_rtx (MEM, GET_MODE (regno_reg_rtx[i]), | |
1435 | plus_constant (XEXP (x, 0), | |
1436 | total_size - inherent_size)); | |
1437 | #endif /* BYTES_BIG_ENDIAN */ | |
1438 | ||
1439 | addr = XEXP (x, 0); | |
1440 | ||
1441 | /* If the stack slot is directly addressable, substitute | |
1442 | the MEM we just got directly for the old REG. | |
1443 | Otherwise, record the address; we will generate hairy code | |
1444 | to compute the address in a register each time it is needed. */ | |
1445 | if (memory_address_p (GET_MODE (regno_reg_rtx[i]), addr)) | |
1446 | reg_equiv_mem[i] = x; | |
1447 | else | |
1448 | reg_equiv_address[i] = XEXP (x, 0); | |
1449 | } | |
1450 | } | |
1451 | ||
1452 | /* Mark the slots in regs_ever_live for the hard regs | |
1453 | used by pseudo-reg number REGNO. */ | |
1454 | ||
1455 | void | |
1456 | mark_home_live (regno) | |
1457 | int regno; | |
1458 | { | |
1459 | register int i, lim; | |
1460 | i = reg_renumber[regno]; | |
1461 | if (i < 0) | |
1462 | return; | |
1463 | lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno)); | |
1464 | while (i < lim) | |
1465 | regs_ever_live[i++] = 1; | |
1466 | } | |
1467 | ||
1468 | /* Kick all pseudos out of hard register REGNO. | |
1469 | If GLOBAL is nonzero, try to find someplace else to put them. | |
1470 | If DUMPFILE is nonzero, log actions taken on that file. | |
1471 | ||
1472 | Return nonzero if any pseudos needed to be kicked out | |
1473 | or if this hard reg may appear explicitly in some instructions. */ | |
1474 | ||
1475 | static int | |
1476 | spill_hard_reg (regno, global, dumpfile) | |
1477 | register int regno; | |
1478 | int global; | |
1479 | FILE *dumpfile; | |
1480 | { | |
1481 | int something_changed = 0; | |
1482 | register int i; | |
1483 | ||
1484 | /* Spill every pseudo reg that was allocated to this reg | |
1485 | or to something that overlaps this reg. */ | |
1486 | ||
1487 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
1488 | if (reg_renumber[i] >= 0 | |
1489 | && reg_renumber[i] <= regno | |
1490 | && (reg_renumber[i] | |
1491 | + HARD_REGNO_NREGS (reg_renumber[i], | |
1492 | PSEUDO_REGNO_MODE (i)) | |
1493 | > regno)) | |
1494 | { | |
1495 | /* If this register belongs solely to a basic block | |
1496 | which needed no spilling, leave it be. */ | |
1497 | if (regno != FRAME_POINTER_REGNUM | |
1498 | && basic_block_needs | |
1499 | && reg_basic_block[i] >= 0 | |
1500 | && basic_block_needs[reg_basic_block[i]] == 0) | |
1501 | continue; | |
1502 | ||
1503 | /* Mark it as no longer having a hard register home. */ | |
1504 | reg_renumber[i] = -1; | |
1505 | /* We will need to scan everything again. */ | |
1506 | something_changed = 1; | |
1507 | if (global) | |
1508 | { | |
1509 | retry_global_alloc (i, forbidden_regs); | |
1510 | /* Update regs_ever_live for new home (if any). */ | |
1511 | mark_home_live (i); | |
1512 | /* If something gets spilled to the stack, | |
1513 | we must have a frame pointer, so spill the frame pointer. */ | |
1514 | if (reg_renumber[i] == -1 && ! frame_pointer_needed) | |
1515 | { | |
1516 | frame_pointer_needed = 1; | |
1517 | forbidden_regs[FRAME_POINTER_REGNUM] = 1; | |
1518 | spill_hard_reg (FRAME_POINTER_REGNUM, global, dumpfile); | |
1519 | } | |
1520 | } | |
1521 | alter_reg (i, regno); | |
1522 | if (dumpfile) | |
1523 | { | |
1524 | if (reg_renumber[i] == -1) | |
1525 | fprintf (dumpfile, " Register %d now on stack.\n\n", i); | |
1526 | else | |
1527 | fprintf (dumpfile, " Register %d now in %d.\n\n", | |
1528 | i, reg_renumber[i]); | |
1529 | } | |
1530 | } | |
1531 | ||
1532 | return something_changed || regs_explicitly_used[regno]; | |
1533 | } | |
1534 | \f | |
1535 | /* Find all paradoxical subregs within X and update reg_max_ref_width. */ | |
1536 | ||
1537 | static rtx | |
1538 | scan_paradoxical_subregs (x) | |
1539 | register rtx x; | |
1540 | { | |
1541 | register int i; | |
1542 | register char *fmt; | |
1543 | register enum rtx_code code = GET_CODE (x); | |
1544 | ||
1545 | switch (code) | |
1546 | { | |
1547 | case CONST_INT: | |
1548 | case CONST: | |
1549 | case SYMBOL_REF: | |
1550 | case LABEL_REF: | |
1551 | case CONST_DOUBLE: | |
1552 | case CC0: | |
1553 | case PC: | |
1554 | case REG: | |
1555 | case USE: | |
1556 | case CLOBBER: | |
1557 | return; | |
1558 | ||
1559 | case SUBREG: | |
1560 | if (GET_CODE (SUBREG_REG (x)) == REG | |
1561 | && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) | |
1562 | reg_max_ref_width[REGNO (SUBREG_REG (x))] | |
1563 | = GET_MODE_SIZE (GET_MODE (x)); | |
1564 | return; | |
1565 | } | |
1566 | ||
1567 | fmt = GET_RTX_FORMAT (code); | |
1568 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1569 | { | |
1570 | if (fmt[i] == 'e') | |
1571 | scan_paradoxical_subregs (XEXP (x, i)); | |
1572 | else if (fmt[i] == 'E') | |
1573 | { | |
1574 | register int j; | |
1575 | for (j = XVECLEN (x, i) - 1; j >=0; j--) | |
1576 | scan_paradoxical_subregs (XVECEXP (x, i, j)); | |
1577 | } | |
1578 | } | |
1579 | } | |
1580 | \f | |
1581 | struct hard_reg_n_uses { int regno; int uses; }; | |
1582 | ||
1583 | static int | |
1584 | hard_reg_use_compare (p1, p2) | |
1585 | struct hard_reg_n_uses *p1, *p2; | |
1586 | { | |
1587 | int tem = p1->uses - p2->uses; | |
1588 | if (tem != 0) return tem; | |
1589 | /* If regs are equally good, sort by regno, | |
1590 | so that the results of qsort leave nothing to chance. */ | |
1591 | return p1->regno - p2->regno; | |
1592 | } | |
1593 | ||
1594 | /* Choose the order to consider regs for use as reload registers | |
1595 | based on how much trouble would be caused by spilling one. | |
1596 | Store them in order of decreasing preference in potential_reload_regs. */ | |
1597 | ||
1598 | static void | |
1599 | order_regs_for_reload () | |
1600 | { | |
1601 | register int i; | |
1602 | register int o = 0; | |
1603 | int large = 0; | |
1604 | ||
1605 | struct hard_reg_n_uses hard_reg_n_uses[FIRST_PSEUDO_REGISTER]; | |
1606 | ||
1607 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1608 | potential_reload_regs[i] = -1; | |
1609 | ||
1610 | /* Count number of uses of each hard reg by pseudo regs allocated to it | |
1611 | and then order them by decreasing use. */ | |
1612 | ||
1613 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1614 | { | |
1615 | hard_reg_n_uses[i].uses = 0; | |
1616 | hard_reg_n_uses[i].regno = i; | |
1617 | } | |
1618 | ||
1619 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
1620 | { | |
1621 | int regno = reg_renumber[i]; | |
1622 | if (regno >= 0) | |
1623 | { | |
1624 | int lim = regno + HARD_REGNO_NREGS (regno, PSEUDO_REGNO_MODE (i)); | |
1625 | while (regno < lim) | |
1626 | hard_reg_n_uses[regno++].uses += reg_n_refs[i]; | |
1627 | } | |
1628 | large += reg_n_refs[i]; | |
1629 | } | |
1630 | ||
1631 | /* Now fixed registers (which cannot safely be used for reloading) | |
1632 | get a very high use count so they will be considered least desirable. | |
1633 | Registers used explicitly in the rtl code are almost as bad. */ | |
1634 | ||
1635 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1636 | { | |
1637 | if (fixed_regs[i]) | |
1638 | hard_reg_n_uses[i].uses += large + 2; | |
1639 | else if (regs_explicitly_used[i]) | |
1640 | hard_reg_n_uses[i].uses += large + 1; | |
1641 | } | |
1642 | hard_reg_n_uses[FRAME_POINTER_REGNUM].uses += large + 2; | |
1643 | ||
1644 | qsort (hard_reg_n_uses, FIRST_PSEUDO_REGISTER, | |
1645 | sizeof hard_reg_n_uses[0], hard_reg_use_compare); | |
1646 | ||
1647 | /* Prefer registers not so far used, for use in temporary loading. | |
1648 | Among them, prefer registers not preserved by calls. */ | |
1649 | ||
1650 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1651 | { | |
1652 | #ifdef REG_ALLOC_ORDER | |
1653 | int regno = reg_alloc_order[i]; | |
1654 | #else | |
1655 | int regno = i; | |
1656 | #endif | |
1657 | if (regs_ever_live[regno] == 0 && call_used_regs[regno] | |
1658 | && ! fixed_regs[regno]) | |
1659 | potential_reload_regs[o++] = regno; | |
1660 | } | |
1661 | ||
1662 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1663 | { | |
1664 | #ifdef REG_ALLOC_ORDER | |
1665 | int regno = reg_alloc_order[i]; | |
1666 | #else | |
1667 | int regno = i; | |
1668 | #endif | |
1669 | if (regs_ever_live[regno] == 0 && ! call_used_regs[regno] | |
1670 | && regno != FRAME_POINTER_REGNUM) | |
1671 | potential_reload_regs[o++] = regno; | |
1672 | } | |
1673 | ||
1674 | /* Now add the regs that are already used, | |
1675 | preferring those used less often. */ | |
1676 | ||
1677 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1678 | if (regs_ever_live[hard_reg_n_uses[i].regno] != 0) | |
1679 | potential_reload_regs[o++] = hard_reg_n_uses[i].regno; | |
1680 | ||
1681 | #if 0 | |
1682 | /* For regs that are used, don't prefer those not preserved by calls | |
1683 | because those are likely to contain high priority things | |
1684 | that are live for short periods of time. */ | |
1685 | ||
1686 | for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--) | |
1687 | if (regs_ever_live[i] != 0 && ! call_used_regs[i]) | |
1688 | potential_reload_regs[o++] = i; | |
1689 | #endif | |
1690 | } | |
1691 | \f | |
1692 | /* Reload pseudo-registers into hard regs around each insn as needed. | |
1693 | Additional register load insns are output before the insn that needs it | |
1694 | and perhaps store insns after insns that modify the reloaded pseudo reg. | |
1695 | ||
1696 | reg_last_reload_reg and reg_reloaded_contents keep track of | |
1697 | which pseudo-registers are already available in reload registers. | |
1698 | We update these for the reloads that we perform, | |
1699 | as the insns are scanned. */ | |
1700 | ||
1701 | static void | |
1702 | reload_as_needed (first, live_known) | |
1703 | rtx first; | |
1704 | int live_known; | |
1705 | { | |
1706 | register rtx insn; | |
1707 | register int i; | |
1708 | int this_block = 0; | |
1709 | rtx x; | |
1710 | rtx after_call = 0; | |
1711 | ||
1712 | bzero (spill_reg_rtx, sizeof spill_reg_rtx); | |
1713 | reg_last_reload_reg = (rtx *) alloca (max_regno * sizeof (rtx)); | |
1714 | bzero (reg_last_reload_reg, max_regno * sizeof (rtx)); | |
1715 | reg_has_output_reload = (char *) alloca (max_regno); | |
1716 | for (i = 0; i < n_spills; i++) | |
1717 | { | |
1718 | reg_reloaded_contents[i] = -1; | |
1719 | reg_reloaded_insn[i] = 0; | |
1720 | } | |
1721 | ||
1722 | for (insn = first; insn;) | |
1723 | { | |
1724 | register rtx next = NEXT_INSN (insn); | |
1725 | ||
1726 | /* Notice when we move to a new basic block. */ | |
1727 | if (basic_block_needs && this_block + 1 < n_basic_blocks | |
1728 | && insn == basic_block_head[this_block+1]) | |
1729 | ++this_block; | |
1730 | ||
1731 | if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN | |
1732 | || GET_CODE (insn) == CALL_INSN) | |
1733 | { | |
1734 | rtx avoid_return_reg = 0; | |
1735 | ||
1736 | /* If insn has no reloads, we want these to be zero, down below. */ | |
1737 | bzero (reg_has_output_reload, max_regno); | |
1738 | bzero (reg_is_output_reload, FIRST_PSEUDO_REGISTER); | |
1739 | ||
1740 | /* Set avoid_return_reg if this is an insn | |
1741 | that might use the value of a function call. */ | |
1742 | if (GET_CODE (insn) == CALL_INSN) | |
1743 | { | |
1744 | if (GET_CODE (PATTERN (insn)) == SET) | |
1745 | after_call = SET_DEST (PATTERN (insn)); | |
1746 | else if (GET_CODE (PATTERN (insn)) == PARALLEL | |
1747 | && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET) | |
1748 | after_call = SET_DEST (XVECEXP (PATTERN (insn), 0, 0)); | |
1749 | else | |
1750 | after_call = 0; | |
1751 | } | |
1752 | else if (after_call != 0 | |
1753 | && !(GET_CODE (PATTERN (insn)) == SET | |
1754 | && SET_DEST (PATTERN (insn)) == stack_pointer_rtx)) | |
1755 | { | |
1756 | if (reg_mentioned_p (after_call, PATTERN (insn))) | |
1757 | avoid_return_reg = after_call; | |
1758 | after_call = 0; | |
1759 | } | |
1760 | ||
1761 | if (GET_MODE (insn) == VOIDmode) | |
1762 | n_reloads = 0; | |
1763 | /* First find the pseudo regs that must be reloaded for this insn. | |
1764 | This info is returned in the tables reload_... (see reload.h). | |
1765 | Also modify the body of INSN by substituting RELOAD | |
1766 | rtx's for those pseudo regs. */ | |
1767 | else | |
1768 | find_reloads (insn, 1, spill_indirect_ok, live_known, spill_reg_order); | |
1769 | ||
1770 | if (n_reloads > 0) | |
1771 | { | |
1772 | /* If this block has not had spilling done, | |
1773 | deactivate any optional reloads lest they | |
1774 | try to use a spill-reg which isn't available here. | |
1775 | If we have any non-optionals that need a spill reg, abort. */ | |
1776 | if (basic_block_needs != 0 | |
1777 | && basic_block_needs[this_block] == 0) | |
1778 | { | |
1779 | for (i = 0; i < n_reloads; i++) | |
1780 | { | |
1781 | if (reload_optional[i]) | |
1782 | reload_in[i] = reload_out[i] = 0; | |
1783 | else if (reload_reg_rtx[i] == 0) | |
1784 | abort (); | |
1785 | } | |
1786 | } | |
1787 | ||
1788 | /* Now compute which reload regs to reload them into. Perhaps | |
1789 | reusing reload regs from previous insns, or else output | |
1790 | load insns to reload them. Maybe output store insns too. | |
1791 | Record the choices of reload reg in reload_reg_rtx. */ | |
1792 | choose_reload_regs (insn, avoid_return_reg); | |
1793 | ||
1794 | /* Generate the insns to reload operands into or out of | |
1795 | their reload regs. */ | |
1796 | emit_reload_insns (insn); | |
1797 | ||
1798 | /* Substitute the chosen reload regs from reload_reg_rtx | |
1799 | into the insn's body (or perhaps into the bodies of other | |
1800 | load and store insn that we just made for reloading | |
1801 | and that we moved the structure into). */ | |
1802 | subst_reloads (); | |
1803 | } | |
1804 | /* Any previously reloaded spilled pseudo reg, stored in this insn, | |
1805 | is no longer validly lying around to save a future reload. | |
1806 | Note that this does not detect pseudos that were reloaded | |
1807 | for this insn in order to be stored in | |
1808 | (obeying register constraints). That is correct; such reload | |
1809 | registers ARE still valid. */ | |
1810 | note_stores (PATTERN (insn), forget_old_reloads_1); | |
1811 | ||
1812 | /* Likewise for regs altered by auto-increment in this insn. | |
1813 | But note that the reg-notes are not changed by reloading: | |
1814 | they still contain the pseudo-regs, not the spill regs. */ | |
1815 | for (x = REG_NOTES (insn); x; x = XEXP (x, 1)) | |
1816 | if (REG_NOTE_KIND (x) == REG_INC) | |
1817 | { | |
1818 | /* See if this pseudo reg was reloaded in this insn. | |
1819 | If so, its last-reload info is still valid | |
1820 | because it is based on this insn's reload. */ | |
1821 | for (i = 0; i < n_reloads; i++) | |
1822 | if (reload_out[i] == XEXP (x, 0)) | |
1823 | break; | |
1824 | ||
1825 | if (i != n_reloads) | |
1826 | forget_old_reloads_1 (XEXP (x, 0)); | |
1827 | } | |
1828 | } | |
1829 | /* A reload reg's contents are unknown after a label. */ | |
1830 | if (GET_CODE (insn) == CODE_LABEL) | |
1831 | for (i = 0; i < n_spills; i++) | |
1832 | { | |
1833 | reg_reloaded_contents[i] = -1; | |
1834 | reg_reloaded_insn[i] = 0; | |
1835 | } | |
1836 | ||
1837 | /* Don't assume a reload reg is still good after a call insn | |
1838 | if it is a call-used reg. */ | |
1839 | if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == CALL_INSN) | |
1840 | for (i = 0; i < n_spills; i++) | |
1841 | if (call_used_regs[spill_regs[i]]) | |
1842 | { | |
1843 | reg_reloaded_contents[i] = -1; | |
1844 | reg_reloaded_insn[i] = 0; | |
1845 | } | |
1846 | ||
1847 | /* In case registers overlap, allow certain insns to invalidate | |
1848 | particular hard registers. */ | |
1849 | ||
1850 | #ifdef INSN_CLOBBERS_REGNO_P | |
1851 | for (i = 0 ; i < n_spills ; i++) | |
1852 | if (INSN_CLOBBERS_REGNO_P (insn, spill_regs[i])) | |
1853 | { | |
1854 | reg_reloaded_contents[i] = -1; | |
1855 | reg_reloaded_insn[i] = 0; | |
1856 | } | |
1857 | #endif | |
1858 | ||
1859 | insn = next; | |
1860 | ||
1861 | #ifdef USE_C_ALLOCA | |
1862 | alloca (0); | |
1863 | #endif | |
1864 | } | |
1865 | } | |
1866 | ||
1867 | /* Discard all record of any value reloaded from X, | |
1868 | or reloaded in X from someplace else; | |
1869 | unless X is an output reload reg of the current insn. | |
1870 | ||
1871 | X may be a hard reg (the reload reg) | |
1872 | or it may be a pseudo reg that was reloaded from. | |
1873 | ||
1874 | This function is not called for instructions generated by reload. */ | |
1875 | ||
1876 | static void | |
1877 | forget_old_reloads_1 (x) | |
1878 | rtx x; | |
1879 | { | |
1880 | register int regno; | |
1881 | int nr; | |
1882 | ||
1883 | if (GET_CODE (x) != REG) | |
1884 | return; | |
1885 | ||
1886 | regno = REGNO (x); | |
1887 | ||
1888 | if (regno >= FIRST_PSEUDO_REGISTER) | |
1889 | nr = 1; | |
1890 | else | |
1891 | { | |
1892 | int i; | |
1893 | nr = HARD_REGNO_NREGS (regno, GET_MODE (x)); | |
1894 | /* Storing into a spilled-reg invalidates its contents. | |
1895 | This can happen if a block-local pseudo is allocated to that reg | |
1896 | and it wasn't spilled because this block's total need is 0. | |
1897 | Then some insn might have an optional reload and use this reg. */ | |
1898 | for (i = 0; i < nr; i++) | |
1899 | if (spill_reg_order[regno + i] >= 0 | |
1900 | /* But don't do this if the reg actually serves as an output | |
1901 | reload reg in the current instruction. */ | |
1902 | && reg_is_output_reload[regno + i] == 0) | |
1903 | { | |
1904 | reg_reloaded_contents[spill_reg_order[regno + i]] = -1; | |
1905 | reg_reloaded_insn[spill_reg_order[regno + i]] = 0; | |
1906 | } | |
1907 | } | |
1908 | ||
1909 | /* Since value of X has changed, | |
1910 | forget any value previously copied from it. */ | |
1911 | ||
1912 | while (nr-- > 0) | |
1913 | /* But don't forget a copy if this is the output reload | |
1914 | that establishes the copy's validity. */ | |
1915 | if (reg_has_output_reload[regno + nr] == 0) | |
1916 | reg_last_reload_reg[regno + nr] = 0; | |
1917 | } | |
1918 | \f | |
1919 | /* Comparison function for qsort to decide which of two reloads | |
1920 | should be handled first. *P1 and *P2 are the reload numbers. */ | |
1921 | ||
1922 | static int | |
1923 | reload_reg_class_lower (p1, p2) | |
1924 | short *p1, *p2; | |
1925 | { | |
1926 | register int r1 = *p1, r2 = *p2; | |
1927 | register int t; | |
1928 | register enum machine_mode mode1, mode2; | |
1929 | ||
1930 | /* Consider required reloads before optional ones. */ | |
1931 | t = reload_optional[r1] - reload_optional[r2]; | |
1932 | if (t != 0) | |
1933 | return t; | |
1934 | /* Consider all multi-reg groups first. | |
1935 | This is safe because `reload' fills all group-need before | |
1936 | filling all non-group need. */ | |
1937 | mode1 = (reload_inmode[r1] == VOIDmode ? reload_outmode[r1] : reload_inmode[r1]); | |
1938 | mode2 = (reload_inmode[r2] == VOIDmode ? reload_outmode[r2] : reload_inmode[r2]); | |
1939 | t = (CLASS_MAX_NREGS (reload_reg_class[r2], mode2) | |
1940 | - CLASS_MAX_NREGS (reload_reg_class[r1], mode1)); | |
1941 | if (t != 0) | |
1942 | return t; | |
1943 | /* Consider reloads in order of increasing reg-class number. */ | |
1944 | t = (int) reload_reg_class[r1] - (int) reload_reg_class[r2]; | |
1945 | if (t != 0) return t; | |
1946 | /* If reloads are equally urgent, sort by reload number, | |
1947 | so that the results of qsort leave nothing to chance. */ | |
1948 | return r1 - r2; | |
1949 | } | |
1950 | \f | |
1951 | /* The following tables are indexed by register number, | |
1952 | not by spill_regs index. */ | |
1953 | ||
1954 | /* 1 if reg is in use as a reload reg for a RELOAD_OTHER reload. */ | |
1955 | static char reload_reg_in_use[FIRST_PSEUDO_REGISTER]; | |
1956 | /* 1 if reg is in use for a RELOAD_FOR_INPUT_RELOAD_ADDRESS reload. */ | |
1957 | static char reload_reg_in_use_for_inputs[FIRST_PSEUDO_REGISTER]; | |
1958 | /* 1 if reg is in use for a RELOAD_FOR_OUTPUT_RELOAD_ADDRESS reload. */ | |
1959 | static char reload_reg_in_use_for_outputs[FIRST_PSEUDO_REGISTER]; | |
1960 | /* 1 if reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */ | |
1961 | static char reload_reg_in_use_for_operands[FIRST_PSEUDO_REGISTER]; | |
1962 | ||
1963 | /* 1 if reg is in use as a reload reg for any sort of reload. */ | |
1964 | static char reload_reg_in_use_at_all[FIRST_PSEUDO_REGISTER]; | |
1965 | ||
1966 | /* Mark reg REGNO as in use for a reload of the sort spec'd by WHEN_NEEDED. */ | |
1967 | ||
1968 | static void | |
1969 | mark_reload_reg_in_use (regno, when_needed) | |
1970 | int regno; | |
1971 | enum reload_when_needed when_needed; | |
1972 | { | |
1973 | switch (when_needed) | |
1974 | { | |
1975 | case RELOAD_OTHER: | |
1976 | reload_reg_in_use[regno] = 1; | |
1977 | break; | |
1978 | ||
1979 | case RELOAD_FOR_INPUT_RELOAD_ADDRESS: | |
1980 | reload_reg_in_use_for_inputs[regno] = 1; | |
1981 | break; | |
1982 | ||
1983 | case RELOAD_FOR_OUTPUT_RELOAD_ADDRESS: | |
1984 | reload_reg_in_use_for_outputs[regno] = 1; | |
1985 | break; | |
1986 | ||
1987 | case RELOAD_FOR_OPERAND_ADDRESS: | |
1988 | reload_reg_in_use_for_operands[regno] = 1; | |
1989 | break; | |
1990 | } | |
1991 | reload_reg_in_use_at_all[regno] = 1; | |
1992 | } | |
1993 | ||
1994 | /* 1 if reg REGNO is free as a reload reg for a reload of the sort | |
1995 | specified by WHEN_NEEDED. */ | |
1996 | ||
1997 | static int | |
1998 | reload_reg_free_p (regno, when_needed) | |
1999 | int regno; | |
2000 | enum reload_when_needed when_needed; | |
2001 | { | |
2002 | /* In use for a RELOAD_OTHER means it's not available for anything. */ | |
2003 | if (reload_reg_in_use[regno]) | |
2004 | return 0; | |
2005 | switch (when_needed) | |
2006 | { | |
2007 | case RELOAD_OTHER: | |
2008 | /* In use for anything means not available for a RELOAD_OTHER. */ | |
2009 | return ! reload_reg_in_use_at_all[regno]; | |
2010 | ||
2011 | /* The other three kinds of use can share a register. */ | |
2012 | case RELOAD_FOR_INPUT_RELOAD_ADDRESS: | |
2013 | return ! reload_reg_in_use_for_inputs[regno]; | |
2014 | case RELOAD_FOR_OUTPUT_RELOAD_ADDRESS: | |
2015 | return ! reload_reg_in_use_for_outputs[regno]; | |
2016 | case RELOAD_FOR_OPERAND_ADDRESS: | |
2017 | return ! reload_reg_in_use_for_operands[regno]; | |
2018 | } | |
2019 | } | |
2020 | ||
2021 | /* Return 1 if the value in reload reg REGNO, as used by a reload | |
2022 | needed for the part of the insn specified by WHEN_NEEDED, | |
2023 | is not in use for a reload in any prior part of the insn. */ | |
2024 | ||
2025 | static int | |
2026 | reload_reg_free_before_p (regno, when_needed) | |
2027 | int regno; | |
2028 | enum reload_when_needed when_needed; | |
2029 | { | |
2030 | switch (when_needed) | |
2031 | { | |
2032 | case RELOAD_OTHER: | |
2033 | /* Since a RELOAD_OTHER reload claims the reg for the entire insn, | |
2034 | its use starts from the beginning, so nothing can use it earlier. */ | |
2035 | return 1; | |
2036 | ||
2037 | /* If this use is for part of the insn, | |
2038 | check the reg is not in use for any prior part. */ | |
2039 | case RELOAD_FOR_OUTPUT_RELOAD_ADDRESS: | |
2040 | if (reload_reg_in_use_for_operands[regno]) | |
2041 | return 0; | |
2042 | case RELOAD_FOR_OPERAND_ADDRESS: | |
2043 | if (reload_reg_in_use_for_inputs[regno]) | |
2044 | return 0; | |
2045 | case RELOAD_FOR_INPUT_RELOAD_ADDRESS: | |
2046 | return 1; | |
2047 | } | |
2048 | } | |
2049 | ||
2050 | /* Return 1 if the value in reload reg REGNO, as used by a reload | |
2051 | needed for the part of the insn specified by WHEN_NEEDED, | |
2052 | is still available in REGNO at the end of the insn. */ | |
2053 | ||
2054 | static int | |
2055 | reload_reg_reaches_end_p (regno, when_needed) | |
2056 | int regno; | |
2057 | enum reload_when_needed when_needed; | |
2058 | { | |
2059 | switch (when_needed) | |
2060 | { | |
2061 | case RELOAD_OTHER: | |
2062 | /* Since a RELOAD_OTHER reload claims the reg for the entire insn, | |
2063 | its value must reach the end. */ | |
2064 | return 1; | |
2065 | ||
2066 | /* If this use is for part of the insn, | |
2067 | its value reaches if no subsequent part uses the same register. */ | |
2068 | case RELOAD_FOR_INPUT_RELOAD_ADDRESS: | |
2069 | if (reload_reg_in_use_for_operands[regno]) | |
2070 | return 0; | |
2071 | case RELOAD_FOR_OPERAND_ADDRESS: | |
2072 | if (reload_reg_in_use_for_outputs[regno]) | |
2073 | return 0; | |
2074 | case RELOAD_FOR_OUTPUT_RELOAD_ADDRESS: | |
2075 | return 1; | |
2076 | } | |
2077 | } | |
2078 | \f | |
2079 | /* Vector of reload-numbers showing the order in which the reloads should | |
2080 | be processed. */ | |
2081 | short reload_order[MAX_RELOADS]; | |
2082 | ||
2083 | /* Indexed by reload number, 1 if incoming value | |
2084 | inherited from previous insns. */ | |
2085 | char reload_inherited[MAX_RELOADS]; | |
2086 | ||
2087 | /* For an inherited reload, this is the insn the reload was inherited from, | |
2088 | if we know it. Otherwise, this is 0. */ | |
2089 | rtx reload_inheritance_insn[MAX_RELOADS]; | |
2090 | ||
2091 | /* If non-zero, this is a place to get the value of the reload, | |
2092 | rather than using reload_in. */ | |
2093 | rtx reload_override_in[MAX_RELOADS]; | |
2094 | ||
2095 | /* For each reload, the index in spill_regs of the spill register used, | |
2096 | or -1 if we did not need one of the spill registers for this reload. */ | |
2097 | int reload_spill_index[MAX_RELOADS]; | |
2098 | ||
2099 | /* Assign hard reg targets for the pseudo-registers we must reload | |
2100 | into hard regs for this insn. | |
2101 | Also output the instructions to copy them in and out of the hard regs. | |
2102 | ||
2103 | For machines with register classes, we are responsible for | |
2104 | finding a reload reg in the proper class. */ | |
2105 | ||
2106 | static void | |
2107 | choose_reload_regs (insn, avoid_return_reg) | |
2108 | rtx insn; | |
2109 | rtx avoid_return_reg; | |
2110 | { | |
2111 | register int j; | |
2112 | int have_groups = 0; | |
2113 | /* Non-zero means we must reuse spill regs for multiple reloads in this insn | |
2114 | or we will not have enough spill regs. */ | |
2115 | int must_reuse = 0; | |
2116 | rtx original_reload_reg_rtx[MAX_RELOADS]; | |
2117 | ||
2118 | /* Don't bother with avoiding the return reg | |
2119 | if we have no mandatory reload that could use it. */ | |
2120 | if (avoid_return_reg) | |
2121 | { | |
2122 | int do_avoid = 0; | |
2123 | int regno = REGNO (avoid_return_reg); | |
2124 | int nregs | |
2125 | = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg)); | |
2126 | int r; | |
2127 | ||
2128 | for (r = regno; r < regno + nregs; r++) | |
2129 | if (spill_reg_order[r] >= 0) | |
2130 | for (j = 0; j < n_reloads; j++) | |
2131 | if (!reload_optional[j] && reload_reg_rtx[j] == 0 | |
2132 | && | |
2133 | TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[j]], r)) | |
2134 | do_avoid = 1; | |
2135 | if (!do_avoid) | |
2136 | avoid_return_reg = 0; | |
2137 | } | |
2138 | ||
2139 | /* See if we have more mandatory reloads than spill regs. | |
2140 | If so, then we cannot risk optimizations that could prevent | |
2141 | reloads from sharing one spill register. */ | |
2142 | ||
2143 | { | |
2144 | int tem = (avoid_return_reg != 0); | |
2145 | for (j = 0; j < n_reloads; j++) | |
2146 | if (! reload_optional[j] && reload_reg_rtx[j] == 0) | |
2147 | tem++; | |
2148 | if (tem > n_spills) | |
2149 | must_reuse = 1; | |
2150 | } | |
2151 | ||
2152 | bcopy (reload_reg_rtx, original_reload_reg_rtx, sizeof (reload_reg_rtx)); | |
2153 | ||
2154 | /* If we fail to get enough regs without must_reuse, | |
2155 | set must_reuse and jump back here. */ | |
2156 | retry: | |
2157 | bzero (reload_inherited, MAX_RELOADS); | |
2158 | bzero (reload_inheritance_insn, MAX_RELOADS * sizeof (rtx)); | |
2159 | bzero (reload_override_in, MAX_RELOADS * sizeof (rtx)); | |
2160 | bzero (reload_reg_in_use, FIRST_PSEUDO_REGISTER); | |
2161 | bzero (reload_reg_in_use_at_all, FIRST_PSEUDO_REGISTER); | |
2162 | bzero (reload_reg_in_use_for_inputs, FIRST_PSEUDO_REGISTER); | |
2163 | bzero (reload_reg_in_use_for_outputs, FIRST_PSEUDO_REGISTER); | |
2164 | bzero (reload_reg_in_use_for_operands, FIRST_PSEUDO_REGISTER); | |
2165 | ||
2166 | /* Don't use the subroutine call return reg for a reload | |
2167 | if we are supposed to avoid it. */ | |
2168 | if (avoid_return_reg) | |
2169 | { | |
2170 | int regno = REGNO (avoid_return_reg); | |
2171 | int nregs | |
2172 | = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg)); | |
2173 | int r; | |
2174 | ||
2175 | for (r = regno; r < regno + nregs; r++) | |
2176 | if (spill_reg_order[r] >= 0) | |
2177 | reload_reg_in_use[r] = 1; | |
2178 | } | |
2179 | ||
2180 | /* In order to be certain of getting the registers we need, | |
2181 | we must sort the reloads into order of increasing register class. | |
2182 | Then our grabbing of reload registers will parallel the process | |
2183 | that provided the reload registers. */ | |
2184 | ||
2185 | /* Also note whether any of the reloads wants a consecutive group of regs. | |
2186 | When that happens, we must when processing the non-group reloads | |
2187 | avoid (when possible) using a reload reg that would break up a group. */ | |
2188 | ||
2189 | /* This used to look for an existing reloaded home for all | |
2190 | of the reloads, and only then perform any new reloads. | |
2191 | But that could lose if the reloads were done out of reg-class order | |
2192 | because a later reload with a looser constraint might have an old | |
2193 | home in a register needed by an earlier reload with a tighter constraint. | |
2194 | It would be possible with even hairier code to detect such cases | |
2195 | and handle them, but it doesn't seem worth while yet. */ | |
2196 | ||
2197 | for (j = 0; j < n_reloads; j++) | |
2198 | { | |
2199 | enum machine_mode mode; | |
2200 | reload_order[j] = j; | |
2201 | reload_spill_index[j] = -1; | |
2202 | mode = (reload_inmode[j] == VOIDmode | |
2203 | || GET_MODE_SIZE (reload_outmode[j]) > GET_MODE_SIZE (reload_inmode[j]) | |
2204 | ? reload_outmode[j] : reload_inmode[j]); | |
2205 | ||
2206 | if (CLASS_MAX_NREGS (reload_reg_class[j], mode) > 1) | |
2207 | have_groups = 1; | |
2208 | /* If we have already decided to use a certain register, | |
2209 | don't use it in another way. */ | |
2210 | if (reload_reg_rtx[j]) | |
2211 | mark_reload_reg_in_use (REGNO (reload_reg_rtx[j]), reload_when_needed[j]); | |
2212 | } | |
2213 | ||
2214 | if (n_reloads > 1) | |
2215 | qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower); | |
2216 | ||
2217 | for (j = 0; j < n_reloads; j++) | |
2218 | { | |
2219 | register int r = reload_order[j]; | |
2220 | register int i; | |
2221 | register rtx new; | |
2222 | enum machine_mode reload_mode = reload_inmode[r]; | |
2223 | int h1_ok, h2_ok, h3_ok; | |
2224 | ||
2225 | /* Ignore reloads that got marked inoperative. */ | |
2226 | if (reload_out[r] == 0 && reload_in[r] == 0) | |
2227 | continue; | |
2228 | ||
2229 | if (GET_MODE_SIZE (reload_outmode[r]) > GET_MODE_SIZE (reload_mode)) | |
2230 | reload_mode = reload_outmode[r]; | |
2231 | if (reload_strict_low[r]) | |
2232 | reload_mode = GET_MODE (SUBREG_REG (reload_out[r])); | |
2233 | ||
2234 | /* No need to find a reload-register if find_reloads chose one. */ | |
2235 | ||
2236 | if (reload_reg_rtx[r] != 0) | |
2237 | continue; | |
2238 | ||
2239 | /* First see if this pseudo is already available as reloaded | |
2240 | for a previous insn. | |
2241 | This feature is disabled for multi-register groups | |
2242 | because we haven't yet any way to tell whether the entire | |
2243 | value is properly preserved. | |
2244 | It is also disabled when there are other reloads for mult-register | |
2245 | groups, lest the inherited reload reg break up a needed group. */ | |
2246 | ||
2247 | { | |
2248 | register int regno = -1; | |
2249 | ||
2250 | if (reload_in[r] == 0) | |
2251 | ; | |
2252 | else if (GET_CODE (reload_in[r]) == REG) | |
2253 | regno = REGNO (reload_in[r]); | |
2254 | else if (GET_CODE (reload_in_reg[r]) == REG) | |
2255 | regno = REGNO (reload_in_reg[r]); | |
2256 | #if 0 | |
2257 | /* This won't work, since REGNO can be a pseudo reg number. | |
2258 | Also, it takes much more hair to keep track of all the things | |
2259 | that can invalidate an inherited reload of part of a pseudoreg. */ | |
2260 | else if (GET_CODE (reload_in[r]) == SUBREG | |
2261 | && GET_CODE (SUBREG_REG (reload_in[r])) == REG) | |
2262 | regno = REGNO (SUBREG_REG (reload_in[r])) + SUBREG_WORD (reload_in[r]); | |
2263 | #endif | |
2264 | ||
2265 | if (regno >= 0 | |
2266 | && reg_last_reload_reg[regno] != 0 | |
2267 | && ! have_groups | |
2268 | /* See comment at next use of must_reuse. */ | |
2269 | && ! must_reuse) | |
2270 | { | |
2271 | i = spill_reg_order[REGNO (reg_last_reload_reg[regno])]; | |
2272 | ||
2273 | if (reg_reloaded_contents[i] == regno | |
2274 | && HARD_REGNO_MODE_OK (spill_regs[i], reload_mode) | |
2275 | && TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]], | |
2276 | spill_regs[i]) | |
2277 | && reload_reg_free_p (spill_regs[i], reload_when_needed[r]) | |
2278 | && reload_reg_free_before_p (spill_regs[i], | |
2279 | reload_when_needed[r])) | |
2280 | { | |
2281 | /* Mark the register as in use for this part of the insn. */ | |
2282 | mark_reload_reg_in_use (spill_regs[i], reload_when_needed[r]); | |
2283 | reload_reg_rtx[r] = reg_last_reload_reg[regno]; | |
2284 | reload_inherited[r] = 1; | |
2285 | reload_inheritance_insn[r] = reg_reloaded_insn[i]; | |
2286 | reload_spill_index[r] = i; | |
2287 | } | |
2288 | } | |
2289 | } | |
2290 | ||
2291 | /* Here's another way to see if the value is already lying around. */ | |
2292 | if (reload_in[r] != 0 | |
2293 | && reload_reg_rtx[r] == 0 | |
2294 | && reload_out[r] == 0 | |
2295 | && (CONSTANT_P (reload_in[r]) | |
2296 | || GET_CODE (reload_in[r]) == PLUS | |
2297 | || GET_CODE (reload_in[r]) == REG | |
2298 | || GET_CODE (reload_in[r]) == MEM) | |
2299 | && ! have_groups | |
2300 | /* This optimization can prevent this reload from reusing | |
2301 | a spill reg used for another reload. That could take away | |
2302 | a spill reg that another reload will need. If we cannot | |
2303 | be sure there will still be enough spill regs, | |
2304 | don't do this optimization. */ | |
2305 | && ! must_reuse) | |
2306 | { | |
2307 | register rtx equiv | |
2308 | = find_equiv_reg (reload_in[r], insn, reload_reg_class[r], | |
2309 | -1, 0, 0, reload_mode); | |
2310 | int regno; | |
2311 | ||
2312 | if (equiv != 0) | |
2313 | regno = REGNO (equiv); | |
2314 | ||
2315 | /* If we found a spill reg, reject it unless it is free | |
2316 | and of the desired class. */ | |
2317 | if (equiv != 0 && GET_CODE (equiv) == REG | |
2318 | && spill_reg_order[regno] >= 0 | |
2319 | && reload_reg_free_before_p (regno, reload_when_needed[r])) | |
2320 | { | |
2321 | if (! TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]], | |
2322 | regno)) | |
2323 | equiv = 0; | |
2324 | } | |
2325 | ||
2326 | if (equiv != 0 && reload_reg_in_use_at_all[regno]) | |
2327 | equiv = 0; | |
2328 | ||
2329 | if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, reload_mode)) | |
2330 | equiv = 0; | |
2331 | ||
2332 | /* We found a register that contains the value we need. | |
2333 | If this register is the same as an `earlyclobber' operand | |
2334 | of the current insn, just mark it as a place to reload from | |
2335 | since we can't use it as the reload register itself. */ | |
2336 | ||
2337 | if (equiv != 0) | |
2338 | for (i = 0; i < n_earlyclobbers; i++) | |
2339 | if (reg_overlap_mentioned_p (equiv, reload_earlyclobbers[i])) | |
2340 | { | |
2341 | reload_override_in[r] = equiv; | |
2342 | equiv = 0; | |
2343 | break; | |
2344 | } | |
2345 | ||
2346 | /* If we found an equivalent reg, say no code need be generated | |
2347 | to load it, and use it as our reload reg. */ | |
2348 | if (equiv != 0 | |
2349 | && REGNO (equiv) != FRAME_POINTER_REGNUM) | |
2350 | { | |
2351 | reload_reg_rtx[r] = equiv; | |
2352 | reload_inherited[r] = 1; | |
2353 | /* If it is a spill reg, | |
2354 | mark the spill reg as in use for this insn. */ | |
2355 | i = spill_reg_order[REGNO (equiv)]; | |
2356 | if (i >= 0) | |
2357 | { | |
2358 | int nr = HARD_REGNO_NREGS (spill_regs[i], reload_mode); | |
2359 | while (nr > 0) | |
2360 | mark_reload_reg_in_use (REGNO (equiv) + --nr, | |
2361 | reload_when_needed[r]); | |
2362 | } | |
2363 | } | |
2364 | } | |
2365 | ||
2366 | /* If it isn't lying around, and isn't optional, | |
2367 | find a place to reload it into. */ | |
2368 | if (reload_reg_rtx[r] != 0 || reload_optional[r] != 0) | |
2369 | continue; | |
2370 | ||
2371 | /* Value not lying around; find a register to reload it into. | |
2372 | Here I is not a regno, it is an index into spill_regs. */ | |
2373 | i = n_spills; | |
2374 | ||
2375 | #if 0 | |
2376 | /* The following is no longer needed now that all multi-register | |
2377 | (group) reloads are processed before all solitary register reloads | |
2378 | (due to changes in `reg_class_lower_p' and `reload'. */ | |
2379 | /* The following also fails to test HARD_REGNO_MODE_OK appropriately, | |
2380 | which was hard to fix because we don't know the mode that the | |
2381 | group might have that would want this register. */ | |
2382 | ||
2383 | /* If we want just one reg, and other reloads want groups, | |
2384 | first try to find a reg that can't be part of a group. */ | |
2385 | if (have_groups | |
2386 | && CLASS_MAX_NREGS (reload_reg_class[r], reload_mode) == 1) | |
2387 | for (i = 0; i < n_spills; i++) | |
2388 | { | |
2389 | int regno = spill_regs[i]; | |
2390 | int class = (int) reload_reg_class[r]; | |
2391 | if (reload_reg_in_use_at_all[regno] == 0 | |
2392 | && TEST_HARD_REG_BIT (reg_class_contents[class], | |
2393 | regno) | |
2394 | && !(regno + 1 < FIRST_PSEUDO_REGISTER | |
2395 | && spill_reg_order[regno + 1] >= 0 | |
2396 | && reload_reg_in_use_at_all[regno + 1] == 0 | |
2397 | && TEST_HARD_REG_BIT (reg_class_contents[class], | |
2398 | regno + 1)) | |
2399 | && !(regno > 0 | |
2400 | && spill_reg_order[regno - 1] >= 0 | |
2401 | && reload_reg_in_use_at_all[regno - 1] == 0 | |
2402 | && TEST_HARD_REG_BIT (reg_class_contents[class], | |
2403 | regno - 1))) | |
2404 | break; | |
2405 | } | |
2406 | ||
2407 | /* If that didn't work, try to find a register that has only one | |
2408 | neighbor that could make a group with it. That way, if the | |
2409 | available registers are three consecutive ones, we avoid taking | |
2410 | the middle one (which would leave us with no possible groups). */ | |
2411 | ||
2412 | if (have_groups | |
2413 | && CLASS_MAX_NREGS (reload_reg_class[r], reload_mode) == 1 | |
2414 | && i == n_spills) | |
2415 | for (i = 0; i < n_spills; i++) | |
2416 | { | |
2417 | int regno = spill_regs[i]; | |
2418 | int class = (int) reload_reg_class[r]; | |
2419 | if (reload_reg_in_use_at_all[regno] == 0 | |
2420 | && TEST_HARD_REG_BIT (reg_class_contents[class], | |
2421 | regno) | |
2422 | && (!(regno + 1 < FIRST_PSEUDO_REGISTER | |
2423 | && spill_reg_order[regno + 1] >= 0 | |
2424 | && reload_reg_in_use_at_all[regno + 1] == 0 | |
2425 | && TEST_HARD_REG_BIT (reg_class_contents[class], | |
2426 | regno + 1)) | |
2427 | || !(regno > 0 | |
2428 | && spill_reg_order[regno - 1] >= 0 | |
2429 | && reload_reg_in_use_at_all[regno - 1] == 0 | |
2430 | && TEST_HARD_REG_BIT (reg_class_contents[class], | |
2431 | regno - 1)))) | |
2432 | break; | |
2433 | } | |
2434 | #endif | |
2435 | ||
2436 | /* Now, if we want a single register and haven't yet found one, | |
2437 | take any reg in the right class and not in use. | |
2438 | If we want a consecutive group, here is where we look for it. */ | |
2439 | if (i == n_spills) | |
2440 | { | |
2441 | int pass; | |
2442 | /* If we put this reload ahead, thinking it is a group, | |
2443 | then insist on finding a group. Otherwise we can grab a | |
2444 | reg that some other reload needs. | |
2445 | (That can happen when we have a 68000 DATA_OR_FP_REG | |
2446 | which is a group of data regs or one fp reg.) | |
2447 | ??? Really it would be nicer to have smarter handling | |
2448 | for that kind of reg class, where a problem like this is normal. | |
2449 | Perhaps those classes should be avoided for reloading | |
2450 | by use of more alternatives. */ | |
2451 | int force_group | |
2452 | = (CLASS_MAX_NREGS (reload_reg_class[r], reload_mode) > 1); | |
2453 | /* We need not be so restrictive if there are no more reloads | |
2454 | for this insn. */ | |
2455 | if (j + 1 == n_reloads) | |
2456 | force_group = 0; | |
2457 | ||
2458 | for (pass = 0; pass < 2; pass++) | |
2459 | { | |
2460 | for (i = 0; i < n_spills; i++) | |
2461 | { | |
2462 | int class = (int) reload_reg_class[r]; | |
2463 | if (reload_reg_free_p (spill_regs[i], reload_when_needed[r]) | |
2464 | && TEST_HARD_REG_BIT (reg_class_contents[class], | |
2465 | spill_regs[i]) | |
2466 | /* Look first for regs to share, then for unshared. */ | |
2467 | && (pass || reload_reg_in_use_at_all[spill_regs[i]])) | |
2468 | { | |
2469 | int nr = HARD_REGNO_NREGS (spill_regs[i], reload_mode); | |
2470 | /* Avoid the problem where spilling a GENERAL_OR_FP_REG | |
2471 | (on 68000) got us two FP regs. If NR is 1, | |
2472 | we would reject both of them. */ | |
2473 | if (force_group) | |
2474 | nr = CLASS_MAX_NREGS (reload_reg_class[r], reload_mode); | |
2475 | /* If we need only one reg, we have already won. */ | |
2476 | if (nr == 1) | |
2477 | { | |
2478 | /* But reject a single reg if we demand a group. */ | |
2479 | if (force_group) | |
2480 | continue; | |
2481 | break; | |
2482 | } | |
2483 | /* Otherwise check that as many consecutive regs as we need | |
2484 | are available here. | |
2485 | Also, don't use for a group registers that are | |
2486 | needed for nongroups. */ | |
2487 | if (HARD_REGNO_MODE_OK (spill_regs[i], reload_mode) | |
2488 | && ! counted_for_nongroups[spill_regs[i]]) | |
2489 | while (nr > 1) | |
2490 | { | |
2491 | int regno = spill_regs[i] + nr - 1; | |
2492 | if (!(TEST_HARD_REG_BIT (reg_class_contents[class], | |
2493 | regno) | |
2494 | && spill_reg_order[regno] >= 0 | |
2495 | && reload_reg_free_p (regno, reload_when_needed[r]) | |
2496 | && ! counted_for_nongroups[regno])) | |
2497 | break; | |
2498 | nr--; | |
2499 | } | |
2500 | if (nr == 1) | |
2501 | break; | |
2502 | } | |
2503 | } | |
2504 | /* If find something on pass 1, omit pass 2. */ | |
2505 | if (i < n_spills) | |
2506 | break; | |
2507 | } | |
2508 | } | |
2509 | ||
2510 | /* We should have found a spill register by now. */ | |
2511 | if (i == n_spills) | |
2512 | { | |
2513 | if (must_reuse) | |
2514 | abort (); | |
2515 | bcopy (original_reload_reg_rtx, reload_reg_rtx, sizeof (reload_reg_rtx)); | |
2516 | must_reuse = 1; | |
2517 | goto retry; | |
2518 | } | |
2519 | ||
2520 | /* Mark as in use for this insn the reload regs we use for this. */ | |
2521 | { | |
2522 | int nr = HARD_REGNO_NREGS (spill_regs[i], reload_mode); | |
2523 | while (nr > 0) | |
2524 | { | |
2525 | mark_reload_reg_in_use (spill_regs[i] + --nr, | |
2526 | reload_when_needed[r]); | |
2527 | reg_reloaded_contents[spill_reg_order[spill_regs[i] + nr]] = -1; | |
2528 | reg_reloaded_insn[spill_reg_order[spill_regs[i] + nr]] = 0; | |
2529 | } | |
2530 | } | |
2531 | ||
2532 | new = spill_reg_rtx[i]; | |
2533 | ||
2534 | if (new == 0 || GET_MODE (new) != reload_mode) | |
2535 | spill_reg_rtx[i] = new = gen_rtx (REG, reload_mode, spill_regs[i]); | |
2536 | ||
2537 | reload_reg_rtx[r] = new; | |
2538 | reload_spill_index[r] = i; | |
2539 | ||
2540 | /* Detect when the reload reg can't hold the reload mode. | |
2541 | This used to be one `if', but Sequent compiler can't handle that. */ | |
2542 | if (HARD_REGNO_MODE_OK (REGNO (reload_reg_rtx[r]), reload_mode)) | |
2543 | if (! (reload_in[r] != 0 | |
2544 | && ! HARD_REGNO_MODE_OK (REGNO (reload_reg_rtx[r]), | |
2545 | GET_MODE (reload_in[r])))) | |
2546 | if (! (reload_out[r] != 0 | |
2547 | && ! HARD_REGNO_MODE_OK (REGNO (reload_reg_rtx[r]), | |
2548 | GET_MODE (reload_out[r])))) | |
2549 | /* The reg is OK. */ | |
2550 | continue; | |
2551 | ||
2552 | /* The reg is not OK. */ | |
2553 | { | |
2554 | if (asm_noperands (PATTERN (insn)) < 0) | |
2555 | /* It's the compiler's fault. */ | |
2556 | abort (); | |
2557 | /* It's the user's fault; the operand's mode and constraint | |
2558 | don't match. Disable this reload so we don't crash in final. */ | |
2559 | error_for_asm (insn, | |
2560 | "`asm' operand constraint incompatible with operand size"); | |
2561 | reload_in[r] = 0; | |
2562 | reload_out[r] = 0; | |
2563 | reload_reg_rtx[r] = 0; | |
2564 | reload_optional[r] = 1; | |
2565 | } | |
2566 | } | |
2567 | ||
2568 | /* If we thought we could inherit a reload, because it seemed that | |
2569 | nothing else wanted the same reload register earlier in the insn, | |
2570 | verify that assumption, now that all reloads have been assigned. */ | |
2571 | ||
2572 | for (j = 0; j < n_reloads; j++) | |
2573 | { | |
2574 | register int r = reload_order[j]; | |
2575 | ||
2576 | if (reload_inherited[r] && reload_reg_rtx[r] != 0 | |
2577 | && ! reload_reg_free_before_p (REGNO (reload_reg_rtx[r]), | |
2578 | reload_when_needed[r])) | |
2579 | reload_inherited[r] = 0; | |
2580 | ||
2581 | /* If we found a better place to reload from, | |
2582 | validate it in the same fashion, if it is a reload reg. */ | |
2583 | if (reload_override_in[r] | |
2584 | && GET_CODE (reload_override_in[r]) == REG | |
2585 | && spill_reg_order[REGNO (reload_override_in[r])] >= 0 | |
2586 | && ! reload_reg_free_before_p (REGNO (reload_override_in[r]), | |
2587 | reload_when_needed[r])) | |
2588 | reload_override_in[r] = 0; | |
2589 | } | |
2590 | ||
2591 | /* Now that reload_override_in is known valid, | |
2592 | actually override reload_in. */ | |
2593 | for (j = 0; j < n_reloads; j++) | |
2594 | if (reload_override_in[j]) | |
2595 | reload_in[j] = reload_override_in[j]; | |
2596 | ||
2597 | /* For all the spill regs newly reloaded in this instruction, | |
2598 | record what they were reloaded from, so subsequent instructions | |
2599 | can inherit the reloads. */ | |
2600 | ||
2601 | for (j = 0; j < n_reloads; j++) | |
2602 | { | |
2603 | register int r = reload_order[j]; | |
2604 | register int i = reload_spill_index[r]; | |
2605 | ||
2606 | /* I is nonneg if this reload used one of the spill regs. | |
2607 | If reload_reg_rtx[r] is 0, this is an optional reload | |
2608 | that we opted to ignore. */ | |
2609 | if (i >= 0 && reload_reg_rtx[r] != 0) | |
2610 | { | |
2611 | /* Maybe the spill reg contains a copy of reload_out. */ | |
2612 | if (reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG) | |
2613 | { | |
2614 | register int nregno = REGNO (reload_out[r]); | |
2615 | reg_last_reload_reg[nregno] = reload_reg_rtx[r]; | |
2616 | reg_reloaded_contents[i] = nregno; | |
2617 | reg_reloaded_insn[i] = insn; | |
2618 | reg_has_output_reload[nregno] = 1; | |
2619 | reg_is_output_reload[spill_regs[i]] = 1; | |
2620 | if (reload_when_needed[r] != RELOAD_OTHER) | |
2621 | abort (); | |
2622 | } | |
2623 | /* Maybe the spill reg contains a copy of reload_in. */ | |
2624 | else if (reload_out[r] == 0 | |
2625 | && (GET_CODE (reload_in[r]) == REG | |
2626 | || GET_CODE (reload_in_reg[r]) == REG)) | |
2627 | { | |
2628 | register int nregno; | |
2629 | if (GET_CODE (reload_in[r]) == REG) | |
2630 | nregno = REGNO (reload_in[r]); | |
2631 | else | |
2632 | nregno = REGNO (reload_in_reg[r]); | |
2633 | ||
2634 | /* If there are two separate reloads (one in and one out) | |
2635 | for the same (hard or pseudo) reg, | |
2636 | leave reg_last_reload_reg set | |
2637 | based on the output reload. | |
2638 | Otherwise, set it from this input reload. */ | |
2639 | if (!reg_has_output_reload[nregno]) | |
2640 | { | |
2641 | reg_last_reload_reg[nregno] = reload_reg_rtx[r]; | |
2642 | reg_reloaded_contents[i] = nregno; | |
2643 | reg_reloaded_insn[i] = insn; | |
2644 | ||
2645 | /* But don't do so if another input reload | |
2646 | will clobber this one's value. */ | |
2647 | if (! reload_reg_reaches_end_p (spill_regs[i], | |
2648 | reload_when_needed[r])) | |
2649 | { | |
2650 | reg_reloaded_contents[i] = -1; | |
2651 | reg_reloaded_insn[i] = 0; | |
2652 | } | |
2653 | } | |
2654 | } | |
2655 | /* Otherwise, the spill reg doesn't contain a copy of any reg. | |
2656 | Clear out its records, lest it be taken for a copy | |
2657 | of reload_in when that is no longer true. */ | |
2658 | else | |
2659 | { | |
2660 | reg_reloaded_contents[i] = -1; | |
2661 | reg_reloaded_insn[i] = 0; | |
2662 | } | |
2663 | } | |
2664 | ||
2665 | /* The following if-statement was #if 0'd in 1.34 (or before...). | |
2666 | It's reenabled in 1.35 because supposedly nothing else | |
2667 | deals with this problem. */ | |
2668 | ||
2669 | /* If a register gets output-reloaded from a non-spill register, | |
2670 | that invalidates any previous reloaded copy of it. | |
2671 | But forget_old_reloads_1 won't get to see it, because | |
2672 | it thinks only about the original insn. So invalidate it here. */ | |
2673 | if (i < 0 && reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG) | |
2674 | { | |
2675 | register int nregno = REGNO (reload_out[r]); | |
2676 | reg_last_reload_reg[nregno] = 0; | |
2677 | reg_has_output_reload[nregno] = 1; | |
2678 | } | |
2679 | } | |
2680 | } | |
2681 | \f | |
2682 | /* Output insns to reload values in and out of the chosen reload regs. */ | |
2683 | ||
2684 | static void | |
2685 | emit_reload_insns (insn) | |
2686 | rtx insn; | |
2687 | { | |
2688 | register int j; | |
2689 | rtx first_output_reload_insn = NEXT_INSN (insn); | |
2690 | rtx first_other_reload_insn = insn; | |
2691 | rtx first_operand_address_reload_insn = insn; | |
2692 | int special; | |
2693 | ||
2694 | /* Now output the instructions to copy the data into and out of the | |
2695 | reload registers. Do these in the order that the reloads were reported, | |
2696 | since reloads of base and index registers precede reloads of operands | |
2697 | and the operands may need the base and index registers reloaded. */ | |
2698 | ||
2699 | for (j = 0; j < n_reloads; j++) | |
2700 | { | |
2701 | register rtx old; | |
2702 | rtx store_insn; | |
2703 | ||
2704 | old = reload_in[j]; | |
2705 | if (old != 0 && ! reload_inherited[j] | |
2706 | && reload_reg_rtx[j] != old | |
2707 | && reload_reg_rtx[j] != 0) | |
2708 | { | |
2709 | register rtx reloadreg = reload_reg_rtx[j]; | |
2710 | rtx oldequiv = 0; | |
2711 | enum machine_mode mode; | |
2712 | rtx where; | |
2713 | rtx this_reload_insn = 0; | |
2714 | ||
2715 | #if 0 | |
2716 | /* No longer done because these paradoxical subregs now occur | |
2717 | only for regs and for spilled stack slots, and in either case | |
2718 | we can safely reload in the nominal machine mode. */ | |
2719 | ||
2720 | /* Strip off of OLD any size-increasing SUBREGs such as | |
2721 | (SUBREG:SI foo:QI 0). */ | |
2722 | ||
2723 | while (GET_CODE (old) == SUBREG && SUBREG_WORD (old) == 0 | |
2724 | && (GET_MODE_SIZE (GET_MODE (old)) | |
2725 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (old))))) | |
2726 | old = SUBREG_REG (old); | |
2727 | #endif | |
2728 | ||
2729 | /* Determine the mode to reload in. | |
2730 | This is very tricky because we have three to choose from. | |
2731 | There is the mode the insn operand wants (reload_inmode[J]). | |
2732 | There is the mode of the reload register RELOADREG. | |
2733 | There is the intrinsic mode of the operand, which we could find | |
2734 | by stripping some SUBREGs. | |
2735 | It turns out that RELOADREG's mode is irrelevant: | |
2736 | we can change that arbitrarily. | |
2737 | ||
2738 | Consider (SUBREG:SI foo:QI) as an operand that must be SImode; | |
2739 | then the reload reg may not support QImode moves, so use SImode. | |
2740 | If foo is in memory due to spilling a pseudo reg, this is safe, | |
2741 | because the QImode value is in the least significant part of a | |
2742 | slot big enough for a SImode. If foo is some other sort of | |
2743 | memory reference, then it is impossible to reload this case, | |
2744 | so previous passes had better make sure this never happens. | |
2745 | ||
2746 | Then consider a one-word union which has SImode and one of its | |
2747 | members is a float, being fetched as (SUBREG:SF union:SI). | |
2748 | We must fetch that as SFmode because we could be loading into | |
2749 | a float-only register. In this case OLD's mode is correct. | |
2750 | ||
2751 | Consider an immediate integer: it has VOIDmode. Here we need | |
2752 | to get a mode from something else. | |
2753 | ||
2754 | In some cases, there is a fourth mode, the operand's | |
2755 | containing mode. If the insn specifies a containing mode for | |
2756 | this operand, it overrides all others. | |
2757 | ||
2758 | I am not sure whether the algorithm here is always right, | |
2759 | but it does the right things in those cases. */ | |
2760 | ||
2761 | mode = GET_MODE (old); | |
2762 | if (mode == VOIDmode) | |
2763 | mode = reload_inmode[j]; | |
2764 | if (reload_strict_low[j]) | |
2765 | mode = GET_MODE (SUBREG_REG (reload_in[j])); | |
2766 | ||
2767 | /* If reloading from memory, see if there is a register | |
2768 | that already holds the same value. If so, reload from there. | |
2769 | We can pass 0 as the reload_reg_p argument because | |
2770 | any other reload has either already been emitted, | |
2771 | in which case find_equiv_reg will see the reload-insn, | |
2772 | or has yet to be emitted, in which case it doesn't matter | |
2773 | because we will use this equiv reg right away. */ | |
2774 | ||
2775 | if (GET_CODE (old) == MEM | |
2776 | || (GET_CODE (old) == REG | |
2777 | && REGNO (old) >= FIRST_PSEUDO_REGISTER | |
2778 | && reg_renumber[REGNO (old)] < 0)) | |
2779 | oldequiv = find_equiv_reg (old, insn, GENERAL_REGS, | |
2780 | -1, 0, 0, mode); | |
2781 | ||
2782 | /* If OLDEQUIV is a spill register, don't use it for this | |
2783 | if any other reload needs it at an earlier stage of this insn | |
2784 | or at this stage. */ | |
2785 | if (oldequiv && GET_CODE (oldequiv) == REG | |
2786 | && spill_reg_order[REGNO (oldequiv)] >= 0 | |
2787 | && (! reload_reg_free_p (REGNO (oldequiv), reload_when_needed[j]) | |
2788 | || ! reload_reg_free_before_p (REGNO (oldequiv), | |
2789 | reload_when_needed[j]))) | |
2790 | oldequiv = 0; | |
2791 | ||
2792 | /* If OLDEQUIV is not a spill register, | |
2793 | don't use it if any other reload wants it. */ | |
2794 | if (oldequiv && GET_CODE (oldequiv) == REG | |
2795 | && spill_reg_order[REGNO (oldequiv)] < 0) | |
2796 | { | |
2797 | int k; | |
2798 | for (k = 0; k < n_reloads; k++) | |
2799 | if (reload_reg_rtx[k] != 0 && k != j | |
2800 | && reg_overlap_mentioned_p (reload_reg_rtx[k], oldequiv)) | |
2801 | { | |
2802 | oldequiv = 0; | |
2803 | break; | |
2804 | } | |
2805 | } | |
2806 | ||
2807 | if (oldequiv == 0) | |
2808 | oldequiv = old; | |
2809 | ||
2810 | /* Encapsulate both RELOADREG and OLDEQUIV into that mode, | |
2811 | then load RELOADREG from OLDEQUIV. */ | |
2812 | ||
2813 | if (GET_MODE (reloadreg) != mode) | |
2814 | reloadreg = gen_rtx (SUBREG, mode, reloadreg, 0); | |
2815 | while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode) | |
2816 | oldequiv = SUBREG_REG (oldequiv); | |
2817 | if (GET_MODE (oldequiv) != VOIDmode | |
2818 | && mode != GET_MODE (oldequiv)) | |
2819 | oldequiv = gen_rtx (SUBREG, mode, oldequiv, 0); | |
2820 | ||
2821 | /* Decide where to put reload insn for this reload. */ | |
2822 | switch (reload_when_needed[j]) | |
2823 | { | |
2824 | case RELOAD_OTHER: | |
2825 | where = first_operand_address_reload_insn; | |
2826 | break; | |
2827 | case RELOAD_FOR_INPUT_RELOAD_ADDRESS: | |
2828 | where = first_other_reload_insn; | |
2829 | break; | |
2830 | case RELOAD_FOR_OUTPUT_RELOAD_ADDRESS: | |
2831 | where = first_output_reload_insn; | |
2832 | break; | |
2833 | case RELOAD_FOR_OPERAND_ADDRESS: | |
2834 | where = insn; | |
2835 | } | |
2836 | ||
2837 | special = 0; | |
2838 | ||
2839 | /* Auto-increment addresses must be reloaded in a special way. */ | |
2840 | if (GET_CODE (oldequiv) == POST_INC | |
2841 | || GET_CODE (oldequiv) == POST_DEC | |
2842 | || GET_CODE (oldequiv) == PRE_INC | |
2843 | || GET_CODE (oldequiv) == PRE_DEC) | |
2844 | { | |
2845 | /* Prevent normal processing of this reload. */ | |
2846 | special = 1; | |
2847 | /* Output a special code sequence for this case. */ | |
2848 | this_reload_insn | |
2849 | = inc_for_reload (reloadreg, oldequiv, reload_inc[j], where); | |
2850 | } | |
2851 | ||
2852 | /* If we are reloading a pseudo-register that was set by the previous | |
2853 | insn, see if we can get rid of that pseudo-register entirely | |
2854 | by redirecting the previous insn into our reload register. */ | |
2855 | ||
2856 | else if (optimize && GET_CODE (old) == REG | |
2857 | && REGNO (old) >= FIRST_PSEUDO_REGISTER | |
2858 | && dead_or_set_p (insn, old) | |
2859 | /* This is unsafe if some other reload | |
2860 | uses the same reg first. */ | |
2861 | && (reload_when_needed[j] == RELOAD_OTHER | |
2862 | || reload_when_needed[j] == RELOAD_FOR_INPUT_RELOAD_ADDRESS)) | |
2863 | { | |
2864 | rtx temp = PREV_INSN (insn); | |
2865 | while (temp && GET_CODE (temp) == NOTE) | |
2866 | temp = PREV_INSN (temp); | |
2867 | if (temp | |
2868 | && GET_CODE (temp) == INSN | |
2869 | && GET_CODE (PATTERN (temp)) == SET | |
2870 | && SET_DEST (PATTERN (temp)) == old | |
2871 | /* Make sure we can access insn_operand_constraint. */ | |
2872 | && asm_noperands (PATTERN (temp)) < 0 | |
2873 | /* This is unsafe if prev insn rejects our reload reg. */ | |
2874 | && constraint_accepts_reg_p (insn_operand_constraint[recog_memoized (temp)][0], | |
2875 | reloadreg) | |
2876 | /* This is unsafe if operand occurs more than once in current | |
2877 | insn. Perhaps some occurrences aren't reloaded. */ | |
2878 | && count_occurrences (PATTERN (insn), old) == 1 | |
2879 | /* Don't risk splitting a matching pair of operands. */ | |
2880 | && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp)))) | |
2881 | { | |
2882 | /* Store into the reload register instead of the pseudo. */ | |
2883 | SET_DEST (PATTERN (temp)) = reloadreg; | |
2884 | /* If these are the only uses of the pseudo reg, | |
2885 | pretend for GDB it lives in the reload reg we used. */ | |
2886 | if (reg_n_deaths[REGNO (old)] == 1 | |
2887 | && reg_n_sets[REGNO (old)] == 1) | |
2888 | { | |
2889 | reg_renumber[REGNO (old)] = REGNO (reload_reg_rtx[j]); | |
2890 | alter_reg (REGNO (old), -1); | |
2891 | } | |
2892 | special = 1; | |
2893 | } | |
2894 | } | |
2895 | ||
2896 | /* We can't do that, so output an insn to load RELOADREG. | |
2897 | Keep them in the following order: | |
2898 | all reloads for input reload addresses, | |
2899 | all reloads for ordinary input operands, | |
2900 | all reloads for addresses of non-reloaded operands, | |
2901 | the insn being reloaded, | |
2902 | all reloads for addresses of output reloads, | |
2903 | the output reloads. */ | |
2904 | if (! special) | |
2905 | this_reload_insn = gen_input_reload (reloadreg, oldequiv, where); | |
2906 | ||
2907 | /* Update where to put other reload insns. */ | |
2908 | if (this_reload_insn) | |
2909 | switch (reload_when_needed[j]) | |
2910 | { | |
2911 | case RELOAD_OTHER: | |
2912 | if (first_other_reload_insn == first_operand_address_reload_insn) | |
2913 | first_other_reload_insn = this_reload_insn; | |
2914 | break; | |
2915 | case RELOAD_FOR_OPERAND_ADDRESS: | |
2916 | if (first_operand_address_reload_insn == insn) | |
2917 | first_operand_address_reload_insn = this_reload_insn; | |
2918 | if (first_other_reload_insn == insn) | |
2919 | first_other_reload_insn = this_reload_insn; | |
2920 | } | |
2921 | ||
2922 | /* reload_inc[j] was formerly processed here. */ | |
2923 | } | |
2924 | ||
2925 | /* Add a note saying the input reload reg | |
2926 | dies in this insn, if anyone cares. */ | |
2927 | #ifdef PRESERVE_DEATH_INFO_REGNO_P | |
2928 | if (old != 0 | |
2929 | && reload_reg_rtx[j] != old | |
2930 | && reload_reg_rtx[j] != 0 | |
2931 | && reload_out[j] == 0 | |
2932 | && PRESERVE_DEATH_INFO_REGNO_P (REGNO (reload_reg_rtx[j]))) | |
2933 | { | |
2934 | register rtx reloadreg = reload_reg_rtx[j]; | |
2935 | ||
2936 | /* The code below is incorrect except for RELOAD_OTHER. */ | |
2937 | if (reload_when_needed[j] != RELOAD_OTHER) | |
2938 | abort (); | |
2939 | ||
2940 | /* Add a death note to this insn, for an input reload. */ | |
2941 | ||
2942 | if (! dead_or_set_p (insn, reloadreg)) | |
2943 | REG_NOTES (insn) | |
2944 | = gen_rtx (EXPR_LIST, REG_DEAD, | |
2945 | reloadreg, REG_NOTES (insn)); | |
2946 | } | |
2947 | #endif | |
2948 | ||
2949 | /* ??? The following code is inadequate. | |
2950 | It handles regs inherited via reg_last_reloaded_contents | |
2951 | but not those inherited via find_equiv_reg. | |
2952 | Note that we can't expect spill_reg_store to contain anything | |
2953 | useful in the case of find_equiv_reg. */ | |
2954 | ||
2955 | #ifdef PRESERVE_DEATH_INFO_REGNO_P | |
2956 | /* For some registers it is important to keep the REG_DEATH | |
2957 | notes accurate for the final pass. | |
2958 | If we are inheriting an old output-reload out of such a reg, | |
2959 | the reg no longer dies there, so remove the death note. */ | |
2960 | ||
2961 | if (reload_reg_rtx[j] != 0 | |
2962 | && PRESERVE_DEATH_INFO_REGNO_P (REGNO (reload_reg_rtx[j])) | |
2963 | && reload_inherited[j] && reload_spill_index[j] >= 0 | |
2964 | && GET_CODE (reload_in[j]) == REG | |
2965 | && spill_reg_store[reload_spill_index[j]] != 0 | |
2966 | && regno_dead_p (REGNO (reload_reg_rtx[j]), | |
2967 | spill_reg_store[reload_spill_index[j]])) | |
2968 | { | |
2969 | remove_death (REGNO (reload_reg_rtx[j]), | |
2970 | spill_reg_store[reload_spill_index[j]]); | |
2971 | } | |
2972 | ||
2973 | /* Likewise for input reloads that were inherited. */ | |
2974 | ||
2975 | if (reload_reg_rtx[j] != 0 | |
2976 | && PRESERVE_DEATH_INFO_REGNO_P (REGNO (reload_reg_rtx[j])) | |
2977 | && reload_inherited[j] && reload_spill_index[j] >= 0 | |
2978 | && GET_CODE (reload_in[j]) == REG | |
2979 | && spill_reg_store[reload_spill_index[j]] == 0 | |
2980 | && reload_inheritance_insn[j] != 0 | |
2981 | && regno_dead_p (REGNO (reload_reg_rtx[j]), | |
2982 | reload_inheritance_insn[j])) | |
2983 | { | |
2984 | remove_death (REGNO (reload_reg_rtx[j]), | |
2985 | reload_inheritance_insn[j]); | |
2986 | } | |
2987 | #endif | |
2988 | ||
2989 | /* If we are reloading a register that was recently stored in with an | |
2990 | output-reload, see if we can prove there was | |
2991 | actually no need to store the old value in it. */ | |
2992 | ||
2993 | if (optimize && reload_inherited[j] && reload_spill_index[j] >= 0 | |
2994 | /* This is unsafe if some other reload uses the same reg first. */ | |
2995 | && (reload_when_needed[j] == RELOAD_OTHER | |
2996 | || reload_when_needed[j] == RELOAD_FOR_INPUT_RELOAD_ADDRESS) | |
2997 | && GET_CODE (reload_in[j]) == REG | |
2998 | && REGNO (reload_in[j]) >= FIRST_PSEUDO_REGISTER | |
2999 | && spill_reg_store[reload_spill_index[j]] != 0 | |
3000 | && dead_or_set_p (insn, reload_in[j]) | |
3001 | /* This is unsafe if operand occurs more than once in current | |
3002 | insn. Perhaps some occurrences weren't reloaded. */ | |
3003 | && count_occurrences (PATTERN (insn), reload_in[j]) == 1) | |
3004 | delete_output_reload (insn, j, reload_spill_index[j]); | |
3005 | ||
3006 | /* Input-reloading is done. Now do output-reloading, | |
3007 | storing the value from the reload-register after the main insn | |
3008 | if reload_out[j] is nonzero. */ | |
3009 | old = reload_out[j]; | |
3010 | if (old != 0 | |
3011 | && reload_reg_rtx[j] != old | |
3012 | && reload_reg_rtx[j] != 0 | |
3013 | /* An output operand that dies right away | |
3014 | does need a reload reg, but need not | |
3015 | be copied from it. */ | |
3016 | && ! (GET_CODE (old) == REG | |
3017 | && find_reg_note (insn, REG_DEAD, old))) | |
3018 | { | |
3019 | register rtx reloadreg = reload_reg_rtx[j]; | |
3020 | enum machine_mode mode; | |
3021 | ||
3022 | #if 0 | |
3023 | /* Strip off of OLD any size-increasing SUBREGs such as | |
3024 | (SUBREG:SI foo:QI 0). */ | |
3025 | ||
3026 | while (GET_CODE (old) == SUBREG && SUBREG_WORD (old) == 0 | |
3027 | && (GET_MODE_SIZE (GET_MODE (old)) | |
3028 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (old))))) | |
3029 | old = SUBREG_REG (old); | |
3030 | #endif | |
3031 | ||
3032 | /* Determine the mode to reload in. | |
3033 | See comments above (for input reloading). */ | |
3034 | ||
3035 | mode = GET_MODE (old); | |
3036 | if (mode == VOIDmode) | |
3037 | abort (); /* Should never happen for an output. */ | |
3038 | #if 0 | |
3039 | mode = reload_inmode[j]; | |
3040 | #endif | |
3041 | if (reload_strict_low[j]) | |
3042 | mode = GET_MODE (SUBREG_REG (reload_out[j])); | |
3043 | ||
3044 | /* Encapsulate both RELOADREG and OLD into that mode, | |
3045 | then load RELOADREG from OLD. */ | |
3046 | if (GET_MODE (reloadreg) != mode) | |
3047 | reloadreg = gen_rtx (SUBREG, mode, reloadreg, 0); | |
3048 | /* If OLD is a subreg, then strip it, since the subreg will | |
3049 | be altered by this very reload (if it's a strict_low_part). */ | |
3050 | while (GET_CODE (old) == SUBREG && GET_MODE (old) != mode) | |
3051 | old = SUBREG_REG (old); | |
3052 | if (GET_MODE (old) != VOIDmode | |
3053 | && mode != GET_MODE (old)) | |
3054 | old = gen_rtx (SUBREG, mode, old, 0); | |
3055 | /* Output the reload insn. */ | |
3056 | store_insn = emit_insn_before (gen_move_insn (old, reloadreg), | |
3057 | first_output_reload_insn); | |
3058 | first_output_reload_insn = store_insn; | |
3059 | /* If this output reload doesn't come from a spill reg, | |
3060 | clear any memory of reloaded copies of the pseudo reg. | |
3061 | If this output reload comes from a spill reg, | |
3062 | reg_has_output_reload will make this do nothing. */ | |
3063 | note_stores (PATTERN (store_insn), forget_old_reloads_1); | |
3064 | ||
3065 | #ifdef PRESERVE_DEATH_INFO_REGNO_P | |
3066 | /* If final will look at death notes for this reg, | |
3067 | put one on the output-reload insn. */ | |
3068 | if (PRESERVE_DEATH_INFO_REGNO_P (REGNO (reloadreg))) | |
3069 | REG_NOTES (store_insn) | |
3070 | = gen_rtx (EXPR_LIST, REG_DEAD, | |
3071 | reloadreg, REG_NOTES (store_insn)); | |
3072 | ||
3073 | /* Move all death-notes from the insn being reloaded | |
3074 | to the output reload, if they are for things used | |
3075 | as inputs in this output reload. */ | |
3076 | if (GET_CODE (old) != REG) | |
3077 | { | |
3078 | /* The note we will examine next. */ | |
3079 | rtx reg_notes = REG_NOTES (insn); | |
3080 | /* The place that pointed to this note. */ | |
3081 | rtx *prev_reg_note = ®_NOTES (insn); | |
3082 | ||
3083 | while (reg_notes) | |
3084 | { | |
3085 | rtx next_reg_notes = XEXP (reg_notes, 1); | |
3086 | if (REG_NOTE_KIND (reg_notes) == REG_DEAD | |
3087 | && reg_mentioned_p (XEXP (reg_notes, 0), old)) | |
3088 | { | |
3089 | *prev_reg_note = next_reg_notes; | |
3090 | XEXP (reg_notes, 1) = REG_NOTES (store_insn); | |
3091 | REG_NOTES (store_insn) = reg_notes; | |
3092 | } | |
3093 | else | |
3094 | prev_reg_note = &XEXP (reg_notes, 1); | |
3095 | ||
3096 | reg_notes = next_reg_notes; | |
3097 | } | |
3098 | } | |
3099 | #endif | |
3100 | } | |
3101 | else store_insn = 0; | |
3102 | ||
3103 | if (reload_spill_index[j] >= 0) | |
3104 | spill_reg_store[reload_spill_index[j]] = store_insn; | |
3105 | } | |
3106 | ||
3107 | /* Move death notes from INSN to output-operand-address reload insns. */ | |
3108 | #ifdef PRESERVE_DEATH_INFO_REGNO_P | |
3109 | { | |
3110 | rtx insn1; | |
3111 | /* Loop over those insns, last ones first. */ | |
3112 | for (insn1 = PREV_INSN (first_output_reload_insn); insn1 != insn; | |
3113 | insn1 = PREV_INSN (insn1)) | |
3114 | if (GET_CODE (insn1) == INSN && GET_CODE (PATTERN (insn1)) == SET) | |
3115 | { | |
3116 | rtx source = SET_SRC (PATTERN (insn1)); | |
3117 | ||
3118 | /* The note we will examine next. */ | |
3119 | rtx reg_notes = REG_NOTES (insn); | |
3120 | /* The place that pointed to this note. */ | |
3121 | rtx *prev_reg_note = ®_NOTES (insn); | |
3122 | ||
3123 | /* If the note is for something used in the source of this | |
3124 | output address reload insn, move the note. */ | |
3125 | while (reg_notes) | |
3126 | { | |
3127 | rtx next_reg_notes = XEXP (reg_notes, 1); | |
3128 | if (REG_NOTE_KIND (reg_notes) == REG_DEAD | |
3129 | && reg_mentioned_p (XEXP (reg_notes, 0), source)) | |
3130 | { | |
3131 | *prev_reg_note = next_reg_notes; | |
3132 | XEXP (reg_notes, 1) = REG_NOTES (insn1); | |
3133 | REG_NOTES (insn1) = reg_notes; | |
3134 | } | |
3135 | else | |
3136 | prev_reg_note = &XEXP (reg_notes, 1); | |
3137 | ||
3138 | reg_notes = next_reg_notes; | |
3139 | } | |
3140 | } | |
3141 | } | |
3142 | #endif | |
3143 | } | |
3144 | \f | |
3145 | /* Emit code before BEFORE_INSN to perform an input reload of IN to RELOADREG. | |
3146 | Handle case of reloading a PLUS expression (currently only happens for | |
3147 | stack slots with out-of-range offset). | |
3148 | ||
3149 | Returns last insn emitted. */ | |
3150 | ||
3151 | static rtx | |
3152 | gen_input_reload (reloadreg, in, before_insn) | |
3153 | rtx reloadreg; | |
3154 | rtx in; | |
3155 | rtx before_insn; | |
3156 | { | |
3157 | #if 0 /* Install this in version 1.37. Avoid risk for now. */ | |
3158 | if (GET_CODE (in) == PLUS) | |
3159 | { | |
3160 | /* Don't use gen_move_insn to make what is actually an add insn. */ | |
3161 | emit_insn_before (gen_move_insn (reloadreg, XEXP (in, 0)), before_insn); | |
3162 | emit_insn_before (gen_add2_insn (reloadreg, XEXP (in, 1)), before_insn); | |
3163 | } | |
3164 | else | |
3165 | #endif | |
3166 | emit_insn_before (gen_move_insn (reloadreg, in), before_insn); | |
3167 | ||
3168 | return PREV_INSN (before_insn); | |
3169 | } | |
3170 | \f | |
3171 | /* Delete a previously made output-reload | |
3172 | whose result we now believe is not needed. | |
3173 | First we double-check. | |
3174 | ||
3175 | INSN is the insn now being processed. | |
3176 | J is the reload-number for this insn, | |
3177 | and SPILL_INDEX is the index in spill_regs of the reload-reg | |
3178 | being used for the reload. */ | |
3179 | ||
3180 | static void | |
3181 | delete_output_reload (insn, j, spill_index) | |
3182 | rtx insn; | |
3183 | int j; | |
3184 | int spill_index; | |
3185 | { | |
3186 | register rtx i1; | |
3187 | ||
3188 | /* Get the raw pseudo-register referred to. */ | |
3189 | ||
3190 | rtx reg = reload_in[j]; | |
3191 | while (GET_CODE (reg) == SUBREG) | |
3192 | reg = SUBREG_REG (reg); | |
3193 | ||
3194 | /* If the pseudo-reg we are reloading is no longer referenced | |
3195 | anywhere between the store into it and here, | |
3196 | and no jumps or labels intervene, then the value can get | |
3197 | here through the reload reg alone. | |
3198 | Otherwise, give up--return. */ | |
3199 | for (i1 = NEXT_INSN (spill_reg_store[spill_index]); | |
3200 | i1 != insn; i1 = NEXT_INSN (i1)) | |
3201 | { | |
3202 | if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN) | |
3203 | return; | |
3204 | if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN) | |
3205 | && reg_mentioned_p (reg, PATTERN (i1))) | |
3206 | return; | |
3207 | } | |
3208 | ||
3209 | /* If this insn will store in the pseudo again, | |
3210 | the previous store can be removed. */ | |
3211 | if (reload_out[j] == reload_in[j]) | |
3212 | delete_insn (spill_reg_store[spill_index]); | |
3213 | ||
3214 | /* See if the pseudo reg has been completely replaced | |
3215 | with reload regs. If so, delete the store insn | |
3216 | and forget we had a stack slot for the pseudo. */ | |
3217 | else if (reg_n_deaths[REGNO (reg)] == 1 | |
3218 | && reg_basic_block[REGNO (reg)] >= 0 | |
3219 | && find_regno_note (insn, REG_DEAD, REGNO (reg))) | |
3220 | { | |
3221 | rtx i2; | |
3222 | ||
3223 | /* We know that it was used only between here | |
3224 | and the beginning of the current basic block. | |
3225 | (We also know that the last use before INSN was | |
3226 | the output reload we are thinking of deleting, but never mind that.) | |
3227 | Search that range; see if any ref remains. */ | |
3228 | for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2)) | |
3229 | { | |
3230 | /* Uses which just store in the pseudo don't count, | |
3231 | since if they are the only uses, they are dead. */ | |
3232 | if (GET_CODE (i2) == INSN | |
3233 | && GET_CODE (PATTERN (i2)) == SET | |
3234 | && SET_DEST (PATTERN (i2)) == reg) | |
3235 | continue; | |
3236 | if (GET_CODE (i2) == CODE_LABEL | |
3237 | || GET_CODE (i2) == JUMP_INSN) | |
3238 | break; | |
3239 | if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN) | |
3240 | && reg_mentioned_p (reg, PATTERN (i2))) | |
3241 | /* Some other ref remains; | |
3242 | we can't do anything. */ | |
3243 | return; | |
3244 | } | |
3245 | ||
3246 | /* Delete the now-dead stores into this pseudo. */ | |
3247 | for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2)) | |
3248 | { | |
3249 | /* Uses which just store in the pseudo don't count, | |
3250 | since if they are the only uses, they are dead. */ | |
3251 | if (GET_CODE (i2) == INSN | |
3252 | && GET_CODE (PATTERN (i2)) == SET | |
3253 | && SET_DEST (PATTERN (i2)) == reg) | |
3254 | delete_insn (i2); | |
3255 | if (GET_CODE (i2) == CODE_LABEL | |
3256 | || GET_CODE (i2) == JUMP_INSN) | |
3257 | break; | |
3258 | } | |
3259 | ||
3260 | /* For the debugging info, | |
3261 | say the pseudo lives in this reload reg. */ | |
3262 | reg_renumber[REGNO (reg)] = REGNO (reload_reg_rtx[j]); | |
3263 | alter_reg (REGNO (reg), -1); | |
3264 | } | |
3265 | } | |
3266 | ||
3267 | \f | |
3268 | /* Output reload-insns to reload VALUE into RELOADREG. | |
3269 | VALUE is a autoincrement or autodecrement RTX whose operand | |
3270 | is a register or memory location; | |
3271 | so reloading involves incrementing that location. | |
3272 | ||
3273 | INC_AMOUNT is the number to increment or decrement by (always positive). | |
3274 | This cannot be deduced from VALUE. | |
3275 | ||
3276 | INSN is the insn before which the new insns should be emitted. | |
3277 | ||
3278 | The return value is the first of the insns emitted. */ | |
3279 | ||
3280 | static rtx | |
3281 | inc_for_reload (reloadreg, value, inc_amount, insn) | |
3282 | rtx reloadreg; | |
3283 | rtx value; | |
3284 | int inc_amount; | |
3285 | rtx insn; | |
3286 | { | |
3287 | /* REG or MEM to be copied and incremented. */ | |
3288 | rtx incloc = XEXP (value, 0); | |
3289 | /* Nonzero if increment after copying. */ | |
3290 | int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC); | |
3291 | ||
3292 | /* No hard register is equivalent to this register after | |
3293 | inc/dec operation. If REG_LAST_RELOAD_REG were non-zero, | |
3294 | we could inc/dec that register as well (maybe even using it for | |
3295 | the source), but I'm not sure it's worth worrying about. */ | |
3296 | if (GET_CODE (incloc) == REG) | |
3297 | reg_last_reload_reg[REGNO (incloc)] = 0; | |
3298 | ||
3299 | if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC) | |
3300 | inc_amount = - inc_amount; | |
3301 | ||
3302 | /* First handle preincrement, which is simpler. */ | |
3303 | if (! post) | |
3304 | { | |
3305 | /* If incrementing a register, assume we can | |
3306 | output an insn to increment it directly. */ | |
3307 | if (GET_CODE (incloc) == REG && | |
3308 | (REGNO (incloc) < FIRST_PSEUDO_REGISTER | |
3309 | || reg_renumber[REGNO (incloc)] >= 0)) | |
3310 | { | |
3311 | rtx first_new | |
3312 | = emit_insn_before (gen_add2_insn (incloc, | |
3313 | gen_rtx (CONST_INT, VOIDmode, | |
3314 | inc_amount)), | |
3315 | insn); | |
3316 | emit_insn_before (gen_move_insn (reloadreg, incloc), insn); | |
3317 | return first_new; | |
3318 | } | |
3319 | else | |
3320 | /* Else we must not assume we can increment the location directly | |
3321 | (even though on many target machines we can); | |
3322 | copy it to the reload register, increment there, then save back. */ | |
3323 | { | |
3324 | rtx first_new | |
3325 | = emit_insn_before (gen_move_insn (reloadreg, incloc), insn); | |
3326 | emit_insn_before (gen_add2_insn (reloadreg, | |
3327 | gen_rtx (CONST_INT, VOIDmode, | |
3328 | inc_amount)), | |
3329 | insn); | |
3330 | emit_insn_before (gen_move_insn (incloc, reloadreg), insn); | |
3331 | return first_new; | |
3332 | } | |
3333 | } | |
3334 | /* Postincrement. | |
3335 | Because this might be a jump insn or a compare, and because RELOADREG | |
3336 | may not be available after the insn in an input reload, | |
3337 | we must do the incrementation before the insn being reloaded for. */ | |
3338 | else | |
3339 | { | |
3340 | /* Copy the value, then increment it. */ | |
3341 | rtx first_new | |
3342 | = emit_insn_before (gen_move_insn (reloadreg, incloc), insn); | |
3343 | ||
3344 | /* If incrementing a register, assume we can | |
3345 | output an insn to increment it directly. */ | |
3346 | if (GET_CODE (incloc) == REG && | |
3347 | (REGNO (incloc) < FIRST_PSEUDO_REGISTER | |
3348 | || reg_renumber[REGNO (incloc)] >= 0)) | |
3349 | { | |
3350 | emit_insn_before (gen_add2_insn (incloc, | |
3351 | gen_rtx (CONST_INT, VOIDmode, | |
3352 | inc_amount)), | |
3353 | insn); | |
3354 | } | |
3355 | else | |
3356 | /* Else we must not assume we can increment INCLOC | |
3357 | (even though on many target machines we can); | |
3358 | increment the copy in the reload register, | |
3359 | save that back, then decrement the reload register | |
3360 | so it has the original value. */ | |
3361 | { | |
3362 | emit_insn_before (gen_add2_insn (reloadreg, | |
3363 | gen_rtx (CONST_INT, VOIDmode, | |
3364 | inc_amount)), | |
3365 | insn); | |
3366 | emit_insn_before (gen_move_insn (incloc, reloadreg), insn); | |
3367 | emit_insn_before (gen_sub2_insn (reloadreg, | |
3368 | gen_rtx (CONST_INT, VOIDmode, | |
3369 | inc_amount)), | |
3370 | insn); | |
3371 | } | |
3372 | return first_new; | |
3373 | } | |
3374 | } | |
3375 | \f | |
3376 | /* Return 1 if we are certain that the constraint-string STRING allows | |
3377 | the hard register REG. Return 0 if we can't be sure of this. */ | |
3378 | ||
3379 | static int | |
3380 | constraint_accepts_reg_p (string, reg) | |
3381 | char *string; | |
3382 | rtx reg; | |
3383 | { | |
3384 | int value = 0; | |
3385 | int regno = true_regnum (reg); | |
3386 | ||
3387 | /* We win if this register is a general register | |
3388 | and each alternative accepts all general registers. */ | |
3389 | if (! TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno)) | |
3390 | return 0; | |
3391 | ||
3392 | /* Initialize for first alternative. */ | |
3393 | value = 0; | |
3394 | /* Check that each alternative contains `g' or `r'. */ | |
3395 | while (1) | |
3396 | switch (*string++) | |
3397 | { | |
3398 | case 0: | |
3399 | /* If an alternative lacks `g' or `r', we lose. */ | |
3400 | return value; | |
3401 | case ',': | |
3402 | /* If an alternative lacks `g' or `r', we lose. */ | |
3403 | if (value == 0) | |
3404 | return 0; | |
3405 | /* Initialize for next alternative. */ | |
3406 | value = 0; | |
3407 | break; | |
3408 | case 'g': | |
3409 | case 'r': | |
3410 | value = 1; | |
3411 | } | |
3412 | } | |
3413 | \f | |
3414 | /* Return the number of places FIND appears within X. */ | |
3415 | ||
3416 | static int | |
3417 | count_occurrences (x, find) | |
3418 | register rtx x, find; | |
3419 | { | |
3420 | register int i, j; | |
3421 | register enum rtx_code code; | |
3422 | register char *format_ptr; | |
3423 | int count; | |
3424 | ||
3425 | if (x == find) | |
3426 | return 1; | |
3427 | if (x == 0) | |
3428 | return 0; | |
3429 | ||
3430 | code = GET_CODE (x); | |
3431 | ||
3432 | switch (code) | |
3433 | { | |
3434 | case REG: | |
3435 | case QUEUED: | |
3436 | case CONST_INT: | |
3437 | case CONST_DOUBLE: | |
3438 | case SYMBOL_REF: | |
3439 | case CODE_LABEL: | |
3440 | case PC: | |
3441 | case CC0: | |
3442 | return 0; | |
3443 | } | |
3444 | ||
3445 | format_ptr = GET_RTX_FORMAT (code); | |
3446 | count = 0; | |
3447 | ||
3448 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
3449 | { | |
3450 | switch (*format_ptr++) | |
3451 | { | |
3452 | case 'e': | |
3453 | count += count_occurrences (XEXP (x, i), find); | |
3454 | break; | |
3455 | ||
3456 | case 'E': | |
3457 | if (XVEC (x, i) != NULL) | |
3458 | { | |
3459 | for (j = 0; j < XVECLEN (x, i); j++) | |
3460 | count += count_occurrences (XVECEXP (x, i, j), find); | |
3461 | } | |
3462 | break; | |
3463 | } | |
3464 | } | |
3465 | return count; | |
3466 | } |