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1 | /* |
2 | * Copyright (c) 1992 The Regents of the University of California. | |
3 | * All rights reserved. | |
4 | * | |
5 | * This software was developed by the Computer Systems Engineering group | |
6 | * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and | |
7 | * contributed to Berkeley. | |
8 | * | |
b480239a KB |
9 | * All advertising materials mentioning features or use of this software |
10 | * must display the following acknowledgement: | |
11 | * This product includes software developed by the University of | |
12 | * California, Lawrence Berkeley Laboratories. | |
13 | * | |
51c2a6c6 CT |
14 | * %sccs.include.redist.c% |
15 | * | |
b480239a | 16 | * @(#)esp.c 7.2 (Berkeley) %G% |
51c2a6c6 CT |
17 | * |
18 | * from: $Header: esp.c,v 1.22 92/06/17 06:59:33 torek Exp $ (LBL) | |
19 | * | |
20 | * Loosely derived from Mary Baker's devSCSIC90.c from the Berkeley | |
21 | * Sprite project, which is: | |
22 | * | |
23 | * Copyright 1988 Regents of the University of California | |
24 | * Permission to use, copy, modify, and distribute this | |
25 | * software and its documentation for any purpose and without | |
26 | * fee is hereby granted, provided that the above copyright | |
27 | * notice appear in all copies. The University of California | |
28 | * makes no representations about the suitability of this | |
29 | * software for any purpose. It is provided "as is" without | |
30 | * express or implied warranty. | |
31 | * | |
32 | * from /sprite/src/kernel/dev/sun4c.md/RCS/devSCSIC90.c,v 1.4 | |
33 | * 90/12/19 12:37:58 mgbaker Exp $ SPRITE (Berkeley) | |
34 | */ | |
35 | ||
36 | /* | |
37 | * Sbus ESP/DMA driver. A single driver must be used for both devices | |
38 | * as they are physically tied to each other: The DMA chip can only | |
39 | * be used to assist ESP SCSI transactions; the ESP interrupt enable is | |
40 | * in the DMA chip csr. | |
41 | * | |
42 | * Since DMA and SCSI interrupts are handled in the same routine, the | |
43 | * DMA device does not declare itself as an sbus device. This saves | |
44 | * some space. | |
45 | */ | |
46 | ||
47 | #include "sys/param.h" | |
48 | #include "sys/buf.h" | |
49 | #include "sys/device.h" | |
50 | #include "sys/malloc.h" | |
51 | ||
52 | #include "scsi/scsi.h" | |
53 | #include "scsi/scsivar.h" | |
54 | ||
55 | #include "machine/autoconf.h" | |
56 | #include "machine/cpu.h" | |
57 | ||
58 | #include "dmareg.h" | |
59 | #define ESP_PHASE_NAMES | |
60 | #include "espreg.h" | |
61 | #include "sbusvar.h" | |
62 | ||
63 | #ifdef DEBUG | |
64 | int espdebug = 1; | |
65 | #endif | |
66 | ||
67 | /* | |
68 | * This driver is organized as a collection of state machines. The | |
69 | * primary machine is the SCSI sequencer: | |
70 | * | |
71 | * Given some previous SCSI state (as set up or tracked by us earlier) | |
72 | * and the interrupt registers provided on the chips (dmacsr, espstat, | |
73 | * espstep, and espintr), derive an action. In many cases this is | |
74 | * just a matter of reading the target's phase and following its orders, | |
75 | * which sets a new state. | |
76 | * | |
77 | * This sequencing is done in espact(); the state is primed in espselect(). | |
78 | * | |
79 | * There will be (update this comment when there is) another state machine | |
80 | * used to handle transfers that fall afoul of chip limits (16 bit DMA | |
81 | * counter; 24 bit address counter in 32 bit address field). | |
82 | * | |
83 | * Another state bit is used to recover from bus resets: | |
84 | * | |
85 | * A single TEST UNIT READY is attempted on each target before any | |
86 | * real communication begins; this TEST UNIT READY is allowed to | |
87 | * fail in any way. This is required for the Quantum ProDrive 100 | |
88 | * MB disks, for instance, which respond to their first selection | |
89 | * with status phase, and for anything that insists on implementing | |
90 | * the broken SCSI-2 synch transfer initial message. | |
91 | * | |
92 | * This is done in espclear() (which calls espselect(); functions that | |
93 | * call espselect() must check for clearing first). | |
94 | * | |
95 | * The state machines actually intermingle, as some SCSI sequences are | |
96 | * only allowed during clearing. | |
97 | */ | |
98 | ||
99 | /* per-DMA variables */ | |
100 | struct dma_softc { | |
101 | struct device sc_dev; /* base device */ | |
102 | volatile struct dmareg *sc_dma; /* register virtual address */ | |
103 | }; | |
104 | void dmaattach(struct device *, struct device *, void *); | |
105 | struct cfdriver dmacd = | |
106 | { NULL, "dma", matchbyname, dmaattach, DV_DULL, sizeof(struct dma_softc) }; | |
107 | ||
108 | /* per-ESP variables */ | |
109 | struct esp_softc { | |
110 | /* | |
111 | * External interfaces. | |
112 | */ | |
113 | struct hba_softc sc_hba; /* base device + hba, must be first */ | |
114 | struct sbusdev sc_sd; /* sbus device */ | |
115 | struct intrhand sc_ih; /* interrupt entry */ | |
116 | int sc_interrupts; /* total number of interrupts taken */ | |
117 | struct dma_softc *sc_dsc; /* pointer to corresponding dma sc */ | |
118 | ||
119 | /* | |
120 | * Addresses mapped to hardware registers. | |
121 | */ | |
122 | volatile struct espreg *sc_esp; | |
123 | volatile struct dmareg *sc_dma; | |
124 | ||
125 | /* | |
126 | * Copies of registers cleared/unlatched by reading. | |
127 | */ | |
128 | u_long sc_dmacsr; | |
129 | u_char sc_espstat; | |
130 | u_char sc_espstep; | |
131 | u_char sc_espintr; | |
132 | ||
133 | /* miscellaneous */ | |
134 | int sc_clockfreq; /* clock frequency */ | |
135 | u_char sc_sel_timeout; /* select timeout */ | |
136 | u_char sc_id; /* initiator ID (default = 7) */ | |
137 | u_char sc_needclear; /* uncleared targets (1 bit each) */ | |
138 | u_char sc_esptype; /* 100, 100A, 2xx (see below) */ | |
139 | u_char sc_ccf; /* clock conversion factor */ | |
140 | u_char sc_conf1; /* value for config reg 1 */ | |
141 | u_char sc_conf2; /* value for config reg 2 */ | |
142 | u_char sc_conf3; /* value for config reg 3 */ | |
143 | ||
144 | /* | |
145 | * Information pertaining to the current transfer, | |
146 | * including sequencing. | |
147 | * | |
148 | * The size of sc_msg is the size of the ESP fifo, | |
149 | * since we do message-in simply by allowing the fifo to fill. | |
150 | */ | |
151 | char sc_probing; /* used during autoconf; see below */ | |
152 | char sc_clearing; /* true => cmd is just to clear targ */ | |
153 | char sc_state; /* SCSI protocol state; see below */ | |
154 | char sc_sentcmd; /* set once we get cmd out */ | |
155 | char sc_dmaactive; /* true => doing dma */ | |
156 | #ifdef notyet | |
157 | u_char sc_sync; /* synchronous transfer stuff (?) */ | |
158 | #endif | |
159 | u_char sc_stat[2]; /* status from last `status' phase */ | |
160 | u_char sc_msg[16]; /* message from device */ | |
161 | u_short sc_dmactl; /* control to load into dma csr */ | |
162 | u_long sc_dmaaddr; /* addr to load into dma addr */ | |
163 | int sc_targ; /* the target involved */ | |
164 | int sc_resid; /* count of bytes not xferred */ | |
165 | struct scsi_cdb sc_cdb; /* current command (not in dvma) */ | |
166 | }; | |
167 | ||
168 | /* | |
169 | * Values for sc_esptype (used to control configuration reset). | |
170 | * The order is important; see espreset(). | |
171 | */ | |
172 | #define ESP100 0 | |
173 | #define ESP100A 1 | |
174 | #define ESP2XX 2 | |
175 | ||
176 | /* | |
177 | * Probe state. 0 means not probing. While looking for each target | |
178 | * we set this to PROBE_TESTING and do a TEST UNIT READY on unit 0. | |
179 | * If selection fails, this is changed to PROBE_NO_TARGET; otherwise | |
180 | * we assume the target exists, regardless of the result of the test. | |
181 | */ | |
182 | #define PROBE_TESTING 1 | |
183 | #define PROBE_NO_TARGET 2 | |
184 | ||
185 | /* | |
186 | * States in sc_state. | |
187 | * | |
188 | * Note that S_CMDSVC is rare: normally we load the SCSI command into the | |
189 | * ESP fifo and get interrupted only when the device has gone to data | |
190 | * or status phase. If the device wants to play games, though, we end | |
191 | * up doing things differently. | |
192 | */ | |
193 | char *espstates[] = { | |
194 | #define S_IDLE 0 /* not doing anything */ | |
195 | "idle", | |
196 | #define S_SEL 1 /* expecting select done interrupt */ | |
197 | "selecting", | |
198 | #define S_CMDSVC 2 /* expecting service req interrupt */ | |
199 | "waiting for service request after command", | |
200 | #define S_IOSVC 3 /* expecting service req interrupt */ | |
201 | "waiting for service request after io", | |
202 | #define S_DI 4 /* expecting data-in done interrupt */ | |
203 | "receiving data", | |
204 | #define S_DO 5 /* expecting data-out done interrupt */ | |
205 | "sending data", | |
206 | #define S_STAT 6 /* expecting status done interrupt */ | |
207 | "receiving status", | |
208 | #define S_MI 7 /* expecting message-in done interrupt */ | |
209 | "receiving message", | |
210 | #define S_FI 8 /* expecting final disconnect interrupt */ | |
211 | "waiting for disconnect" | |
212 | }; | |
213 | ||
214 | /* | |
215 | * Return values from espact(). | |
216 | */ | |
217 | #define ACT_CONT 0 /* espact() handled everything */ | |
218 | #define ACT_READ 1 /* target said it is sending us data */ | |
219 | #define ACT_WRITE 2 /* target said it is expecting data */ | |
220 | #define ACT_DONE 3 /* handled everything, and op is now done */ | |
221 | #define ACT_ERROR 4 /* an error occurred, op has been trashed */ | |
222 | #define ACT_RESET 5 /* please reset ESP, then do ACT_ERROR */ | |
223 | #define ACT_QUICKINTR 6 /* another interrupt is expected immediately */ | |
224 | ||
225 | /* autoconfiguration driver */ | |
226 | void espattach(struct device *, struct device *, void *); | |
227 | struct cfdriver espcd = | |
228 | { NULL, "esp", matchbyname, espattach, DV_DULL, sizeof(struct esp_softc) }; | |
229 | ||
230 | /* Sbus driver */ | |
231 | void espsbreset(struct device *); | |
232 | ||
233 | /* interrupt interface */ | |
234 | int espintr(void *); | |
235 | ||
236 | /* SCSI HBA driver */ | |
237 | int espicmd(struct hba_softc *, int, struct scsi_cdb *, caddr_t, int, int); | |
238 | int espdump(struct hba_softc *, int, struct scsi_cdb *, caddr_t, int); | |
239 | void espstart(struct device *, struct sq *, struct buf *, | |
240 | scdgo_fn, struct device *); | |
241 | int espgo(struct device *, int, scintr_fn, struct device *, | |
242 | struct buf *, int); | |
243 | void esprel(struct device *); | |
244 | void esphbareset(struct hba_softc *, int); | |
245 | static struct hbadriver esphbadriver = | |
246 | { espicmd, espdump, espstart, espgo, esprel, esphbareset }; | |
247 | ||
248 | /* forward declarations */ | |
249 | static void espdoattach(int unit); | |
250 | static void espreset(struct esp_softc *); | |
251 | ||
252 | /* | |
253 | * The transfer size is limited to 16 bits since the scsi ctrl transfer | |
254 | * counter is only 2 bytes. A 0 value means the biggest transfer size | |
255 | * (2 ** 16) == 64k. | |
256 | */ | |
257 | #define MAX_TRANSFER_SIZE (64 * 1024) | |
258 | ||
259 | /* Return true if this transfer will cross a dma boundary */ | |
260 | #define CROSS_DMA(addr, len) \ | |
261 | (((int)(addr) & 0xff000000) != (((int)(addr) + (len) - 1) & 0xff000000)) | |
262 | ||
263 | /* | |
264 | * Attach a found DMA chip. | |
265 | * The second argument is really a pointer to an sbus_attach_args. | |
266 | */ | |
267 | void | |
268 | dmaattach(parent, dev, args) | |
269 | struct device *parent; | |
270 | struct device *dev; | |
271 | void *args; | |
272 | { | |
273 | register struct dma_softc *dsc = (struct dma_softc *)dev; | |
274 | register struct sbus_attach_args *sa = args; | |
275 | register volatile struct dmareg *dma; | |
276 | register int rev; | |
277 | struct esp_softc *esc; | |
278 | ||
279 | if (sa->sa_ra.ra_vaddr) | |
280 | dma = (volatile struct dmareg *)sa->sa_ra.ra_vaddr; | |
281 | else | |
282 | dma = (volatile struct dmareg *) | |
283 | mapiodev(sa->sa_ra.ra_paddr, sizeof(struct dmareg)); | |
284 | dsc->sc_dma = dma; | |
285 | ||
286 | switch (rev = DMA_REV(dma->dma_csr)) { | |
287 | case DMAREV_1: | |
288 | printf(": rev 1\n"); | |
289 | break; | |
290 | case DMAREV_2: | |
291 | printf(": rev 2\n"); | |
292 | break; | |
293 | default: | |
294 | printf(": unknown revision %d\n", rev); | |
295 | break; | |
296 | } | |
297 | espdoattach(dsc->sc_dev.dv_unit); | |
298 | } | |
299 | ||
300 | /* | |
301 | * Attach a found ESP chip. Search for targets; attach each one found. | |
302 | * The latter must be deferred if the corresponding dma chip has not yet | |
303 | * been configured. | |
304 | */ | |
305 | void | |
306 | espattach(parent, self, args) | |
307 | struct device *parent; | |
308 | struct device *self; | |
309 | void *args; | |
310 | { | |
311 | register struct esp_softc *sc = (struct esp_softc *)self; | |
312 | register struct sbus_attach_args *sa = args; | |
313 | register volatile struct espreg *esp; | |
314 | struct dma_softc *dsc; | |
315 | int node, pri, freq, t; | |
316 | ||
317 | if (sa->sa_ra.ra_nintr != 1) { | |
318 | printf(": expected 1 interrupt, got %d\n", sa->sa_ra.ra_nintr); | |
319 | return; | |
320 | } | |
321 | pri = sa->sa_ra.ra_intr[0].int_pri; | |
322 | printf(" pri %d", pri); | |
323 | if (sa->sa_ra.ra_vaddr) | |
324 | esp = (volatile struct espreg *)sa->sa_ra.ra_vaddr; | |
325 | else | |
326 | esp = (volatile struct espreg *) | |
327 | mapiodev(sa->sa_ra.ra_paddr, sizeof(struct espreg)); | |
328 | sc->sc_esp = esp; | |
329 | node = sa->sa_ra.ra_node; | |
330 | sc->sc_id = getpropint(node, "initiator-id", 7); | |
331 | freq = getpropint(node, "clock-frequency", -1); | |
332 | if (freq < 0) | |
333 | freq = ((struct sbus_softc *)sc->sc_hba.hba_dev.dv_parent)->sc_clockfreq; | |
334 | ||
335 | /* MIGHT NEED TO RESET ESP CHIP HERE ...? */ | |
336 | ||
337 | /* | |
338 | * Find out whether we have a -100, -100A, or -2xx, | |
339 | * and what speed it runs at. | |
340 | */ | |
341 | sc->sc_conf1 = sc->sc_id | ESPCONF1_PARENB; | |
342 | /* sc->sc_conf2 = 0; */ | |
343 | /* sc->sc_conf3 = 0; */ | |
344 | esp->esp_conf1 = sc->sc_conf1; | |
345 | esp->esp_conf2 = 0; | |
346 | esp->esp_conf2 = ESPCONF2_SCSI2 | ESPCONF2_RPE; | |
347 | if ((esp->esp_conf2 & ~ESPCONF2_RSVD) != | |
348 | (ESPCONF2_SCSI2 | ESPCONF2_RPE)) { | |
349 | printf(": ESP100"); | |
350 | sc->sc_esptype = ESP100; | |
351 | } else { | |
352 | esp->esp_conf2 = 0; | |
353 | esp->esp_conf3 = 0; | |
354 | esp->esp_conf3 = 5; | |
355 | if (esp->esp_conf3 != 5) { /* XXX def bits */ | |
356 | printf(": ESP100A"); | |
357 | sc->sc_esptype = ESP100A; | |
358 | } else { | |
359 | esp->esp_conf3 = 0; | |
360 | printf(": ESP2XX"); | |
361 | sc->sc_esptype = ESP2XX; | |
362 | } | |
363 | } | |
364 | printf(", clock = %s MHz, ID = %d\n", clockfreq(freq), sc->sc_id); | |
365 | ||
366 | /* | |
367 | * Set clock conversion factor and select timeout. | |
368 | * N.B.: clock frequency is not actually used in the rest | |
369 | * of the driver; I calculate it here for completeness only | |
370 | * (so I can see it when debugging). | |
371 | */ | |
372 | sc->sc_clockfreq = freq; | |
373 | freq = howmany(freq, 1000 * 1000); /* convert to MHz */ | |
374 | t = ESPCCF_FROMMHZ(freq); | |
375 | if (t < ESPCCF_MIN) | |
376 | t = ESPCCF_MIN; | |
377 | sc->sc_ccf = t; | |
378 | t = ESPTIMO_REGVAL(250, t, freq); /* timeout = 250 ms. */ | |
379 | if (t >= 256) | |
380 | t = 0; | |
381 | sc->sc_sel_timeout = t; | |
382 | ||
383 | /* | |
384 | * Link into sbus; set interrupt handler. | |
385 | */ | |
386 | sc->sc_sd.sd_reset = espsbreset; | |
387 | sbus_establish(&sc->sc_sd, &sc->sc_hba.hba_dev); | |
388 | sc->sc_ih.ih_fun = espintr; | |
389 | sc->sc_ih.ih_arg = sc; | |
390 | intr_establish(pri, &sc->sc_ih); | |
391 | espdoattach(sc->sc_hba.hba_dev.dv_unit); | |
392 | } | |
393 | ||
394 | /* | |
395 | * `Final' attach of esp occurs once esp and dma chips have been found | |
396 | * and assigned virtual addresses. Set up the ESP SCSI data structures | |
397 | * and probe the SCSI bus. | |
398 | */ | |
399 | static void | |
400 | espdoattach(unit) | |
401 | int unit; | |
402 | { | |
403 | register struct esp_softc *sc; | |
404 | register struct dma_softc *dsc; | |
405 | register int targ; | |
406 | ||
407 | /* make sure we have both */ | |
408 | if (espcd.cd_ndevs <= unit || | |
409 | dmacd.cd_ndevs <= unit || | |
410 | (sc = espcd.cd_devs[unit]) == NULL || | |
411 | (dsc = dmacd.cd_devs[unit]) == NULL) | |
412 | return; | |
413 | sc->sc_dsc = dsc; | |
414 | sc->sc_dma = dsc->sc_dma; | |
415 | sc->sc_hba.hba_driver = &esphbadriver; | |
416 | ||
417 | espreset(sc); | |
418 | ||
419 | /* MAYBE THIS SHOULD BE MOVED TO scsi_subr.c? */ | |
420 | for (targ = 0; targ < 8; targ++) { | |
421 | if (targ == sc->sc_id) | |
422 | continue; | |
423 | sc->sc_probing = PROBE_TESTING; | |
424 | sc->sc_clearing = 1; | |
425 | (void) scsi_test_unit_ready(&sc->sc_hba, targ, 0); | |
426 | if (sc->sc_probing != PROBE_NO_TARGET) { | |
427 | sc->sc_probing = 0; | |
428 | sc->sc_clearing = 0; | |
429 | SCSI_FOUNDTARGET(&sc->sc_hba, targ); | |
430 | } | |
431 | } | |
432 | sc->sc_probing = 0; | |
433 | sc->sc_clearing = 0; | |
434 | } | |
435 | ||
436 | /* | |
437 | * Internal DMA reset. | |
438 | */ | |
439 | static void | |
440 | dmareset(sc) | |
441 | struct esp_softc *sc; | |
442 | { | |
443 | register volatile struct dmareg *dma = sc->sc_dma; | |
444 | ||
445 | /* reset DMA chip */ | |
446 | dma->dma_csr |= DMA_RESET; | |
447 | DELAY(200); | |
448 | dma->dma_csr &= ~DMA_RESET; /* ??? */ | |
449 | sc->sc_state = S_IDLE; | |
450 | sc->sc_dmaactive = 0; | |
451 | dma->dma_csr |= DMA_IE; /* enable interrupts */ | |
452 | DELAY(200); | |
453 | } | |
454 | ||
455 | /* | |
456 | * Reset the chip. N.B.: this causes a SCSI bus reset! | |
457 | */ | |
458 | static void | |
459 | espreset(sc) | |
460 | register struct esp_softc *sc; | |
461 | { | |
462 | register volatile struct espreg *esp = sc->sc_esp; | |
463 | ||
464 | dmareset(sc); | |
465 | esp->esp_cmd = ESPCMD_RESET_CHIP; | |
466 | DELAY(200); | |
467 | esp->esp_cmd = ESPCMD_NOP; | |
468 | DELAY(200); | |
469 | ||
470 | /* | |
471 | * Reload configuration registers (cleared by RESET_CHIP command). | |
472 | * Reloading conf2 on an ESP100 goofs it up, so out of paranoia | |
473 | * we load only the registers that exist. | |
474 | */ | |
475 | esp->esp_conf1 = sc->sc_conf1; | |
476 | if (sc->sc_esptype > ESP100) { /* 100A, 2XX */ | |
477 | esp->esp_conf2 = sc->sc_conf2; | |
478 | if (sc->sc_esptype > ESP100A) /* 2XX only */ | |
479 | esp->esp_conf3 = sc->sc_conf3; | |
480 | } | |
481 | esp->esp_ccf = sc->sc_ccf; | |
482 | esp->esp_timeout = sc->sc_sel_timeout; | |
483 | /* We set synch offset later. */ | |
484 | ||
485 | sc->sc_needclear = 0xff; | |
486 | } | |
487 | ||
488 | /* | |
489 | * Reset the SCSI bus and, optionally, all attached targets. | |
490 | * The chip should retain most of its parameters (including esp_ccf) | |
491 | * across this kind of reset (see section 3.5 of Emulex documentation). | |
492 | */ | |
493 | void | |
494 | esphbareset(hba, resetunits) | |
495 | struct hba_softc *hba; | |
496 | int resetunits; | |
497 | { | |
498 | register struct esp_softc *sc = (struct esp_softc *)hba; | |
499 | register volatile struct espreg *esp = sc->sc_esp; | |
500 | ||
501 | dmareset(sc); | |
502 | ||
503 | /* BEGIN ??? */ | |
504 | /* turn off scsi bus reset interrupts and reset scsi bus */ | |
505 | esp->esp_conf1 = sc->sc_conf1 | ESPCONF1_REPORT; | |
506 | DELAY(200); | |
507 | esp->esp_cmd = ESPCMD_RESET_BUS; | |
508 | DELAY(800); | |
509 | esp->esp_cmd = ESPCMD_NOP; | |
510 | DELAY(200); | |
511 | esp->esp_conf1 = sc->sc_conf1; | |
512 | /* END ??? */ | |
513 | ||
514 | sc->sc_needclear = 0xff; | |
515 | ||
516 | if (resetunits) | |
517 | scsi_reset_units(&sc->sc_hba); | |
518 | } | |
519 | ||
520 | /* | |
521 | * Reset the esp, after an Sbus reset. | |
522 | * Also resets corresponding dma chip. | |
523 | * | |
524 | * THIS ROUTINE MIGHT GO AWAY | |
525 | */ | |
526 | void | |
527 | espsbreset(dev) | |
528 | struct device *dev; | |
529 | { | |
530 | struct esp_softc *sc = (struct esp_softc *)dev; | |
531 | ||
532 | if (sc->sc_dsc) { | |
533 | printf(" %s %s", sc->sc_dsc->sc_dev.dv_xname, | |
534 | sc->sc_hba.hba_dev.dv_xname); | |
535 | esphbareset(&sc->sc_hba, 1); | |
536 | } | |
537 | } | |
538 | ||
539 | static void | |
540 | esperror(sc, err) | |
541 | char *err; | |
542 | register struct esp_softc *sc; | |
543 | { | |
544 | ||
545 | printf("%s: %s (target=%d): stat=%b step=%x dmacsr=%b intr=%b\n", | |
546 | sc->sc_hba.hba_dev.dv_xname, err, sc->sc_targ, | |
547 | sc->sc_espstat, ESPSTAT_BITS, sc->sc_espstep, | |
548 | sc->sc_dmacsr, DMA_BITS, sc->sc_espintr, ESPINTR_BITS); | |
549 | } | |
550 | ||
551 | /* | |
552 | * An interrupt has occurred. Sequence through the SCSI state machine. | |
553 | * Return the action to take. | |
554 | * | |
555 | * Most of the work happens here. | |
556 | * | |
557 | * There are three interrupt sources: | |
558 | * -- ESP interrupt request (typically, some device wants something). | |
559 | * -- DMA memory error. | |
560 | * -- DMA byte count has reached 0 (we do not often want this one but | |
561 | * can only turn it off in rev 2 DMA chips, it seems). | |
562 | * DOES THIS OCCUR AT ALL HERE? THERE IS NOTHING TO HANDLE IT! | |
563 | */ | |
564 | static int | |
565 | espact(sc, esp, dma, cdb) | |
566 | register struct esp_softc *sc; | |
567 | register volatile struct espreg *esp; | |
568 | register volatile struct dmareg *dma; | |
569 | register struct scsi_cdb *cdb; | |
570 | { | |
571 | register char *xname = sc->sc_hba.hba_dev.dv_xname; | |
572 | register int reg, phase, i; | |
573 | ||
574 | /* check various error conditions, using as little code as possible */ | |
575 | if (sc->sc_dmacsr & DMA_EP) { | |
576 | esperror(sc, "DMA error"); | |
577 | dma->dma_csr |= DMA_FLUSH; | |
578 | return (ACT_ERROR); | |
579 | } | |
580 | reg = sc->sc_espstat; | |
581 | if (reg & ESPSTAT_GE) { | |
582 | /* | |
583 | * This often occurs when there is no target. | |
584 | * (See DSC code below.) | |
585 | */ | |
586 | if (sc->sc_espintr & ESPINTR_DSC && | |
587 | sc->sc_state == S_SEL && sc->sc_probing) { | |
588 | sc->sc_probing = PROBE_NO_TARGET; | |
589 | return (ACT_RESET); | |
590 | } | |
591 | esperror(sc, "DIAGNOSTIC: gross error (ignored)"); | |
592 | } | |
593 | if (reg & ESPSTAT_PE) { | |
594 | esperror(sc, "parity error"); | |
595 | return (ACT_RESET); | |
596 | } | |
597 | reg = sc->sc_espintr; | |
598 | #define ERR (ESPINTR_SBR|ESPINTR_ILC|ESPINTR_RSL|ESPINTR_SAT|ESPINTR_SEL) | |
599 | if (reg & ERR) { | |
600 | if (reg & ESPINTR_SBR) | |
601 | esperror(sc, "scsi bus reset"); | |
602 | else if (reg & ESPINTR_ILC) | |
603 | esperror(sc, "illegal command (driver bug)"); | |
604 | else { | |
605 | printf("%s: target %d", xname, sc->sc_targ); | |
606 | if (reg & ESPINTR_RSL) | |
607 | printf(" tried to reselect;"); | |
608 | if (reg & ESPINTR_SAT) | |
609 | printf(" selected with ATN;"); | |
610 | if (reg & ESPINTR_SEL) | |
611 | printf(" selected us as target;"); | |
612 | printf("we do not allow this yet\n"); | |
613 | } | |
614 | return (ACT_ERROR); | |
615 | } | |
616 | #undef ERR | |
617 | ||
618 | /* | |
619 | * Disconnect currently only allowed in `final interrupt' states. | |
620 | */ | |
621 | if (reg & ESPINTR_DSC) { | |
622 | if (sc->sc_state == S_FI) | |
623 | return (ACT_DONE); | |
624 | /* | |
625 | * If we were doing a select just to test the existence | |
626 | * of the target, note that it did not respond; otherwise | |
627 | * gripe. | |
628 | */ | |
629 | if (sc->sc_state == S_SEL) { | |
630 | if (sc->sc_probing) { | |
631 | sc->sc_probing = PROBE_NO_TARGET; | |
632 | return (ACT_RESET); | |
633 | } | |
634 | } | |
635 | /* flush fifo, in case we were selecting or sending data */ | |
636 | esp->esp_cmd = ESPCMD_FLUSH_FIFO; | |
637 | printf("%s: target %d not responding\n", | |
638 | xname, sc->sc_targ); | |
639 | return (ACT_ERROR); | |
640 | } | |
641 | ||
642 | /* | |
643 | * Okay, things are moving along. | |
644 | * What were we doing the last time we did something, | |
645 | * and did it complete normally? | |
646 | */ | |
647 | phase = sc->sc_espstat & ESPSTAT_PHASE; | |
648 | switch (sc->sc_state) { | |
649 | ||
650 | case S_SEL: | |
651 | /* | |
652 | * We were selecting. Arbitration and select are | |
653 | * complete (because ESPINTR_DSC was not set), but | |
654 | * there is no guarantee the command went out. | |
655 | */ | |
656 | if ((reg & (ESPINTR_SVC|ESPINTR_CMP)) != | |
657 | (ESPINTR_SVC|ESPINTR_CMP)) { | |
658 | esperror(sc, "selection failed"); | |
659 | return (ACT_RESET); | |
660 | } | |
661 | if (sc->sc_espstep == ESPSTEP_DONE) { | |
662 | sc->sc_sentcmd = 1; | |
663 | break; | |
664 | } | |
665 | if (sc->sc_espstep == 2) { | |
666 | /* | |
667 | * We got something other than command phase. | |
668 | * Just pretend things are normal; the | |
669 | * device will ask for the command later. | |
670 | */ | |
671 | esperror(sc, "DIAGNOSTIC: esp step 2"); | |
672 | } else if (sc->sc_espstep == 3) { | |
673 | /* | |
674 | * Device entered command phase and then exited it | |
675 | * before we finished handing out the command. | |
676 | * Let this happen iff we are trying to clear the | |
677 | * target state. | |
678 | */ | |
679 | esperror(sc, "DIAGNOSTIC: esp step 3"); | |
680 | if (!sc->sc_clearing) | |
681 | return (ACT_RESET); | |
682 | } else { | |
683 | printf("%s: mysterious esp step %d\n", | |
684 | xname, sc->sc_espstep); | |
685 | return (ACT_RESET); | |
686 | } | |
687 | /* | |
688 | * Part of the command may still be lodged in the FIFO. | |
689 | */ | |
690 | esp->esp_cmd = ESPCMD_FLUSH_FIFO; | |
691 | break; | |
692 | ||
693 | case S_CMDSVC: | |
694 | /* | |
695 | * We were waiting for phase change after stuffing the command | |
696 | * into the FIFO. Make sure it got out. | |
697 | */ | |
698 | reg = ESP_NFIFO(esp); | |
699 | if (reg) { | |
700 | esperror(sc, "DIAGNOSTIC: CMDSVC, fifo not empty"); | |
701 | printf("\tfifo count = %x\n", reg); | |
702 | esp->esp_cmd = ESPCMD_FLUSH_FIFO; | |
703 | } else | |
704 | sc->sc_sentcmd = 1; | |
705 | break; | |
706 | ||
707 | case S_IOSVC: | |
708 | /* | |
709 | * We were waiting for phase change after I/O. | |
710 | */ | |
711 | break; | |
712 | ||
713 | case S_DI: | |
714 | /* | |
715 | * We were doing DMA data in, and expecting a | |
716 | * transfer-count-zero interrupt or a phase change. | |
717 | * We got that; drain the pack register and | |
718 | * handle as for data out. | |
719 | */ | |
720 | dma->dma_csr |= DMA_DRAIN; | |
721 | reg = 0; /* FIFO auto flushed? */ | |
722 | goto dma_data_done; | |
723 | ||
724 | case S_DO: | |
725 | /* | |
726 | * We were doing DMA data out. If there is data in the | |
727 | * FIFO, it is stuff that got DMAed out but never made | |
728 | * it to the device, so it counts as residual. | |
729 | * | |
730 | * XXX handle DMA IO with large count or address | |
731 | * boundary condition by resuming here, or below? | |
732 | */ | |
733 | if ((reg = ESP_NFIFO(esp)) != 0) | |
734 | esp->esp_cmd = ESPCMD_FLUSH_FIFO; | |
735 | dma_data_done: | |
736 | if (sc->sc_dmaactive == 0) { | |
737 | printf("%s: dma done while %s, dmaactive==0\n", | |
738 | xname, espstates[sc->sc_state]); | |
739 | panic("espact"); | |
740 | } | |
741 | sc->sc_dmaactive = 0; | |
742 | reg += esp->esp_tcl | (esp->esp_tch << 8); | |
743 | if (reg == 0 && (sc->sc_espstat & ESPSTAT_TC) == 0) | |
744 | reg = 65536; | |
745 | if (reg > sc->sc_resid) { | |
746 | printf("%s: xfer resid (%d) > xfer req (%d)\n", | |
747 | xname, reg, sc->sc_resid); | |
748 | reg = sc->sc_resid; | |
749 | } | |
750 | /* | |
751 | * If data came in we must flush cache. | |
752 | */ | |
753 | if (sc->sc_state == S_DI) | |
754 | cache_flush(sc->sc_dmaaddr, sc->sc_resid - reg); | |
755 | sc->sc_resid = reg; | |
756 | if ((sc->sc_espintr & ESPINTR_SVC) == 0) { | |
757 | printf("%s: no bus service req\n", xname); | |
758 | return (ACT_RESET); | |
759 | } | |
760 | break; | |
761 | ||
762 | case S_STAT: | |
763 | /* | |
764 | * The last thing we did was tell it `initiator complete' | |
765 | * and so we expect to have gotten both the status byte | |
766 | * and the final message byte. It is possible that we | |
767 | * got something else.... | |
768 | * | |
769 | * Apparently, BUS SERVICE is set if we got just status, | |
770 | * while FUNCTION COMPLETE is set if we got both. | |
771 | */ | |
772 | if ((reg & (ESPINTR_SVC|ESPINTR_CMP)) != ESPINTR_CMP) { | |
773 | esperror(sc, "bad status interrupt state"); | |
774 | return (ACT_RESET); | |
775 | } | |
776 | reg = ESP_NFIFO(esp); | |
777 | if (reg < 2) { | |
778 | printf( | |
779 | "%s: command done but fifo count = %d; must be >= 2\n", xname, | |
780 | reg); | |
781 | return (ACT_RESET); | |
782 | } | |
783 | /* | |
784 | * Read the status and the first msg byte. | |
785 | * It should be CMD_COMPLETE. Eventually we | |
786 | * may handle IDENTIFY, DISCONNECT, etc., as well. | |
787 | */ | |
788 | sc->sc_stat[0] = esp->esp_fifo; | |
789 | sc->sc_msg[0] = reg = esp->esp_fifo; | |
790 | esp->esp_cmd = ESPCMD_MSG_ACCEPT; | |
791 | if (reg == MSG_CMD_COMPLETE) { | |
792 | sc->sc_state = S_FI; | |
793 | return (ACT_CONT); | |
794 | } | |
795 | if (SCSIMSGLEN(reg) != 1) { | |
796 | printf("%s: target %d is naughty\n", | |
797 | xname, sc->sc_targ); | |
798 | return (ACT_RESET); | |
799 | } | |
800 | printf("%s: warning: target %d returned msg 0x%x\n", | |
801 | xname, sc->sc_targ, reg); | |
802 | sc->sc_state = S_FI; | |
803 | return (ACT_CONT); | |
804 | ||
805 | case S_MI: | |
806 | if ((reg & ESPINTR_SVC) == 0) { | |
807 | esperror(sc, "missing phase after msg in"); | |
808 | return (ACT_RESET); | |
809 | } | |
810 | reg = ESP_NFIFO(esp); | |
811 | for (i = 0; i < reg; i++) | |
812 | sc->sc_msg[i] = esp->esp_fifo; | |
813 | break; | |
814 | ||
815 | case S_FI: | |
816 | esperror(sc, "target did not disconnect"); | |
817 | return (ACT_RESET); | |
818 | } | |
819 | ||
820 | /* | |
821 | * Things are still moving along. The phase tells us | |
822 | * what the device wants next. Do it. | |
823 | */ | |
824 | switch (phase) { | |
825 | ||
826 | case ESPPHASE_DATA_OUT: | |
827 | if (!sc->sc_sentcmd) esperror(sc, "DIAGNOSTIC: data out without command"); | |
828 | sc->sc_state = S_DO; | |
829 | return (ACT_WRITE); | |
830 | ||
831 | case ESPPHASE_DATA_IN: | |
832 | if (!sc->sc_sentcmd) esperror(sc, "DIAGNOSTIC: data in without command"); | |
833 | sc->sc_state = S_DI; | |
834 | return (ACT_READ); | |
835 | ||
836 | case ESPPHASE_CMD: | |
837 | /* | |
838 | * Silly thing wants the command again. | |
839 | * Load it into the FIFO and go to CMDSVC state. | |
840 | */ | |
841 | printf("%s: redoing command\n", xname); | |
842 | reg = SCSICMDLEN(cdb->cdb_bytes[0]); | |
843 | for (i = 0; i < reg; i++) | |
844 | esp->esp_fifo = cdb->cdb_bytes[i]; | |
845 | sc->sc_state = S_CMDSVC; | |
846 | esp->esp_cmd = ESPCMD_XFER_INFO; | |
847 | return (ACT_CONT); | |
848 | ||
849 | case ESPPHASE_STATUS: | |
850 | sc->sc_state = S_STAT; | |
851 | esp->esp_cmd = ESPCMD_INIT_COMP; | |
852 | return (ACT_CONT); | |
853 | ||
854 | case ESPPHASE_MSG_IN: | |
855 | printf("%s: accepting (& ignoring) msg from target %d\n", xname, sc->sc_targ); | |
856 | sc->sc_state = S_MI; | |
857 | esp->esp_cmd = ESPCMD_MSG_ACCEPT; | |
858 | return (ACT_CONT); | |
859 | ||
860 | default: | |
861 | printf("%s: target %d asked for strange phase (%s)\n", | |
862 | xname, sc->sc_targ, espphases[phase]); | |
863 | return (ACT_RESET); | |
864 | } | |
865 | /* NOTREACHED */ | |
866 | } | |
867 | ||
868 | /* | |
869 | * Issue a select, loading command into the FIFO. | |
870 | * Return nonzero on error, 0 if OK. | |
871 | * Sets state to `selecting'; espact() will sequence state FSM. | |
872 | */ | |
873 | void | |
874 | espselect(sc, esp, targ, cdb) | |
875 | register struct esp_softc *sc; | |
876 | register volatile struct espreg *esp; | |
877 | register int targ; | |
878 | register struct scsi_cdb *cdb; | |
879 | { | |
880 | register int i, cmdlen = SCSICMDLEN(cdb->cdb_bytes[0]); | |
881 | ||
882 | sc->sc_targ = targ; | |
883 | sc->sc_state = S_SEL; | |
884 | sc->sc_sentcmd = 0; | |
885 | sc->sc_stat[0] = 0xff; /* ??? */ | |
886 | sc->sc_msg[0] = 0xff; /* ??? */ | |
887 | ||
888 | /* | |
889 | * Try to talk to target. | |
890 | * Synch offset 0 => asynchronous transfer. | |
891 | */ | |
892 | esp->esp_id = targ; | |
893 | esp->esp_syncoff = 0; | |
894 | ||
895 | /* | |
896 | * Stuff the command bytes into the fifo. | |
897 | * Select without attention since we do not do disconnect yet. | |
898 | */ | |
899 | for (i = 0; i < cmdlen; i++) | |
900 | esp->esp_fifo = cdb->cdb_bytes[i]; | |
901 | esp->esp_cmd = ESPCMD_SEL_NATN; | |
902 | /* the rest is done elsewhere */ | |
903 | } | |
904 | ||
905 | /* | |
906 | * THIS SHOULD BE ADJUSTABLE | |
907 | */ | |
908 | /* name howlong purpose */ | |
909 | #define SELECT_WAIT 300000 /* wait for select to complete */ | |
910 | #define CMD_WAIT 1000 /* wait for next phase, generic */ | |
911 | #define IO_WAIT 1000000 /* time to xfer data in/out */ | |
912 | #define POSTDATA_WAIT 10000000 /* wait for next phase, after dataio */ | |
913 | ||
914 | /* | |
915 | * Transfer data out via polling. Return success (0) iff all | |
916 | * the bytes were sent and we got an interrupt. | |
917 | * | |
918 | * This returns -1 on timeout, resid count on early interrupt, | |
919 | * but no one really cares.... | |
920 | */ | |
921 | static int | |
922 | espixfer_out(sc, esp, dma, buf, len) | |
923 | register struct esp_softc *sc; | |
924 | register volatile struct espreg *esp; | |
925 | register volatile struct dmareg *dma; | |
926 | register caddr_t buf; | |
927 | register int len; | |
928 | { | |
929 | register int wait, n; | |
930 | ||
931 | if (CROSS_DMA(buf, len)) | |
932 | panic("espixfer_out: 16MB boundary"); | |
933 | ||
934 | /* set dma address and transfer count */ | |
935 | dma->dma_addr = (int)buf; | |
936 | esp->esp_tch = len >> 8; | |
937 | esp->esp_tcl = len; | |
938 | ||
939 | /* load count into counter via DMA NOP */ | |
940 | esp->esp_cmd = ESPCMD_DMA | ESPCMD_NOP; | |
941 | ||
942 | /* enable dma (but not interrupts) */ | |
943 | dma->dma_csr = DMA_ENA; | |
944 | ||
945 | /* and go */ | |
946 | esp->esp_cmd = ESPCMD_DMA | ESPCMD_XFER_INFO; | |
947 | ||
948 | /* wait for completion */ | |
949 | for (wait = IO_WAIT; wait > 0; --wait) { | |
950 | n = dma->dma_csr; | |
951 | if (DMA_INTR(n)) { | |
952 | sc->sc_espstat = esp->esp_stat; | |
953 | sc->sc_espstep = esp->esp_step & ESPSTEP_MASK; | |
954 | sc->sc_espintr = esp->esp_intr; | |
955 | sc->sc_dmacsr = n; | |
956 | n = esp->esp_tcl | (esp->esp_tch << 8); | |
957 | if (n == 0 && (sc->sc_espstat & ESPSTAT_TC) == 0) | |
958 | n = 65536; | |
959 | ||
960 | return (n); | |
961 | } | |
962 | DELAY(1); | |
963 | } | |
964 | return (-1); | |
965 | } | |
966 | ||
967 | /* | |
968 | * Transfer data in via polling. | |
969 | * Return resid count on interrupt, -1 if timed out. | |
970 | */ | |
971 | static int | |
972 | espixfer_in(sc, esp, dma, buf, len) | |
973 | register struct esp_softc *sc; | |
974 | register volatile struct espreg *esp; | |
975 | register volatile struct dmareg *dma; | |
976 | register caddr_t buf; | |
977 | register int len; | |
978 | { | |
979 | register int wait, n; | |
980 | ||
981 | if (CROSS_DMA(buf, len)) | |
982 | panic("espixfer_in: 16MB boundary"); | |
983 | ||
984 | /* set dma address and transfer count */ | |
985 | dma->dma_addr = (int)buf; | |
986 | esp->esp_tch = len >> 8; | |
987 | esp->esp_tcl = len; | |
988 | ||
989 | /* load count into counter via DMA NOP */ | |
990 | esp->esp_cmd = ESPCMD_DMA | ESPCMD_NOP; | |
991 | ||
992 | /* enable dma (but not interrupts) */ | |
993 | dma->dma_csr = DMA_ENA | DMA_READ; | |
994 | ||
995 | /* and go */ | |
996 | esp->esp_cmd = ESPCMD_DMA | ESPCMD_XFER_INFO; | |
997 | ||
998 | /* wait for completion */ | |
999 | for (wait = IO_WAIT; wait > 0; --wait) { | |
1000 | n = dma->dma_csr; | |
1001 | if (DMA_INTR(n)) { | |
1002 | sc->sc_espstat = esp->esp_stat; | |
1003 | sc->sc_espstep = esp->esp_step & ESPSTEP_MASK; | |
1004 | sc->sc_espintr = esp->esp_intr; | |
1005 | dma->dma_csr |= DMA_DRAIN; | |
1006 | sc->sc_dmacsr = n; | |
1007 | n = esp->esp_tcl | (esp->esp_tch << 8); | |
1008 | if (n == 0 && (sc->sc_espstat & ESPSTAT_TC) == 0) | |
1009 | n = 65536; | |
1010 | ||
1011 | cache_flush(buf, (u_int)len - n); | |
1012 | return (n); | |
1013 | } | |
1014 | DELAY(1); | |
1015 | } | |
1016 | return (-1); | |
1017 | } | |
1018 | ||
1019 | /* | |
1020 | * Clear out target state by doing a special TEST UNIT READY. | |
1021 | * Note that this calls espicmd (possibly recursively). | |
1022 | */ | |
1023 | void | |
1024 | espclear(sc, targ) | |
1025 | register struct esp_softc *sc; | |
1026 | register int targ; | |
1027 | { | |
1028 | ||
1029 | /* turn off needclear immediately since this calls espicmd() again */ | |
1030 | sc->sc_needclear &= ~(1 << targ); | |
1031 | sc->sc_clearing = 1; | |
1032 | (void) scsi_test_unit_ready(&sc->sc_hba, targ, 0); | |
1033 | sc->sc_clearing = 0; | |
1034 | } | |
1035 | ||
1036 | /* | |
1037 | * Send an `immediate' command, i.e., poll until the whole thing is done. | |
1038 | * Return the status byte from the device, or -1 if we timed out. | |
1039 | */ | |
1040 | int | |
1041 | espicmd(hba, targ, cdb, buf, len, rw) | |
1042 | register struct hba_softc *hba; | |
1043 | int targ; | |
1044 | register struct scsi_cdb *cdb; | |
1045 | caddr_t buf; | |
1046 | register int len; | |
1047 | int rw; | |
1048 | { | |
1049 | register struct esp_softc *sc = (struct esp_softc *)hba; | |
1050 | register volatile struct espreg *esp = sc->sc_esp; | |
1051 | register volatile struct dmareg *dma = sc->sc_dma; | |
1052 | register int r, wait; | |
1053 | char *msg; | |
1054 | ||
1055 | if ((unsigned)len > MAX_TRANSFER_SIZE) { | |
1056 | printf("%s: bad length %d\n", sc->sc_hba.hba_dev.dv_xname, len); | |
1057 | panic("espicmd"); | |
1058 | } | |
1059 | ||
1060 | /* | |
1061 | * Clear the target if necessary. | |
1062 | */ | |
1063 | if (sc->sc_needclear & (1 << targ) && !sc->sc_probing) | |
1064 | espclear(sc, targ); | |
1065 | ||
1066 | /* | |
1067 | * Disable hardware interrupts, start select sequence. | |
1068 | * Wait for interrupt-pending bit, then call espact() to | |
1069 | * sequence the state machine. When it tells us to do | |
1070 | * data transfer, we do programmed I/O. | |
1071 | * In any case, we loop calling espact() until done. | |
1072 | */ | |
1073 | dma->dma_csr = 0; /* disable hardware interrupts */ | |
1074 | espselect(sc, esp, targ, cdb); | |
1075 | wait = SELECT_WAIT; | |
1076 | loop: | |
1077 | for (;;) { | |
1078 | r = dma->dma_csr; | |
1079 | if (!DMA_INTR(r)) { | |
1080 | if (--wait < 0) { | |
1081 | msg = "timeout waiting for phase change"; | |
1082 | goto err; | |
1083 | } | |
1084 | DELAY(1); | |
1085 | continue; | |
1086 | } | |
1087 | break; | |
1088 | } | |
1089 | sc->sc_espstat = esp->esp_stat; | |
1090 | sc->sc_espstep = esp->esp_step & ESPSTEP_MASK; | |
1091 | sc->sc_espintr = esp->esp_intr; | |
1092 | sc->sc_dmacsr = r; | |
1093 | /* | |
1094 | * The action happens `twice around' for read and write. | |
1095 | * All the rest `goto loop' or return or some such. | |
1096 | */ | |
1097 | wait = CMD_WAIT; | |
1098 | for (;;) { | |
1099 | switch (r = espact(sc, esp, dma, cdb)) { | |
1100 | ||
1101 | case ACT_CONT: | |
1102 | case ACT_QUICKINTR: | |
1103 | goto loop; | |
1104 | ||
1105 | case ACT_READ: | |
1106 | if (len == 0 || (rw & B_READ) == 0) { | |
1107 | msg = "wrong phase"; | |
1108 | goto err; | |
1109 | } | |
1110 | r = espixfer_in(sc, esp, dma, buf, len); | |
1111 | if (r < 0) { | |
1112 | msg = "timeout reading from device"; | |
1113 | goto err; | |
1114 | } | |
1115 | buf += len - r; | |
1116 | len = r; | |
1117 | /* we did the io, expecting `generic service' */ | |
1118 | sc->sc_state = S_IOSVC; | |
1119 | wait = POSTDATA_WAIT; | |
1120 | break; | |
1121 | ||
1122 | case ACT_WRITE: | |
1123 | if (len == 0 || rw & B_READ) { | |
1124 | msg = "wrong phase"; | |
1125 | goto err; | |
1126 | } | |
1127 | if (espixfer_out(sc, esp, dma, buf, len)) { | |
1128 | msg = "timeout writing to device"; | |
1129 | goto err; | |
1130 | } | |
1131 | sc->sc_state = S_IOSVC; | |
1132 | wait = POSTDATA_WAIT; | |
1133 | break; | |
1134 | ||
1135 | case ACT_RESET: | |
1136 | sc->sc_state = S_IDLE; | |
1137 | goto reset; | |
1138 | ||
1139 | case ACT_DONE: | |
1140 | sc->sc_state = S_IDLE; | |
1141 | return (sc->sc_stat[0]); | |
1142 | ||
1143 | case ACT_ERROR: | |
1144 | sc->sc_state = S_IDLE; | |
1145 | return (-1); | |
1146 | ||
1147 | default: | |
1148 | panic("espicmd action"); | |
1149 | } | |
1150 | } | |
1151 | err: | |
1152 | printf("%s: target %d: %s (phase = %s)\n", | |
1153 | sc->sc_hba.hba_dev.dv_xname, targ, msg, | |
1154 | espphases[sc->sc_espstat & ESPSTAT_PHASE]); | |
1155 | reset: | |
1156 | espreset(sc); /* ??? */ | |
1157 | return (-1); | |
1158 | } | |
1159 | ||
1160 | /* | |
1161 | * Dump (write memory, possibly physmem). | |
1162 | * SPARC higher-level dump code always provides virtual addresses, | |
1163 | * so we need not do any I/O mapping here. | |
1164 | */ | |
1165 | int | |
1166 | espdump(hba, targ, cdb, buf, len) | |
1167 | register struct hba_softc *hba; | |
1168 | int targ; | |
1169 | register struct scsi_cdb *cdb; | |
1170 | caddr_t buf; | |
1171 | register int len; | |
1172 | { | |
1173 | ||
1174 | return (espicmd(hba, targ, cdb, buf, len, B_WRITE)); | |
1175 | } | |
1176 | ||
1177 | /* | |
1178 | * Allocate resources (SCSI bus and DVMA space) for the given transfer. | |
1179 | * Must be called at splbio(). | |
1180 | * | |
1181 | * THIS SHOULD RETURN SUCCESS/FAIL INDICATION | |
1182 | */ | |
1183 | void | |
1184 | espstart(self, sq, bp, dgo, dev) | |
1185 | struct device *self; | |
1186 | register struct sq *sq; | |
1187 | struct buf *bp; | |
1188 | scdgo_fn dgo; | |
1189 | struct device *dev; | |
1190 | { | |
1191 | register struct esp_softc *sc = (struct esp_softc *)self; | |
1192 | ||
1193 | if (sc->sc_hba.hba_busy == 0) { | |
1194 | /* | |
1195 | * Bus not busy, nothing to do here, just tell | |
1196 | * this target or unit that it has the SCSI bus. | |
1197 | */ | |
1198 | sc->sc_hba.hba_busy = 1; | |
1199 | (*dgo)(dev, &sc->sc_cdb); | |
1200 | } else { | |
1201 | /* | |
1202 | * Bus is busy; just enqueue. | |
1203 | */ | |
1204 | sq->sq_dgo = dgo; | |
1205 | sq->sq_dev = dev; | |
1206 | sq->sq_forw = NULL; | |
1207 | if (sc->sc_hba.hba_head == NULL) | |
1208 | sc->sc_hba.hba_head = sq; | |
1209 | else | |
1210 | sc->sc_hba.hba_tail->sq_forw = sq; | |
1211 | sc->sc_hba.hba_tail = sq; | |
1212 | } | |
1213 | } | |
1214 | ||
1215 | /* | |
1216 | * Send a `dma' command, i.e., send the cdb and use DMA to send the data. | |
1217 | * Return 0 on success, 1 on failure. | |
1218 | */ | |
1219 | int | |
1220 | espgo(self, targ, intr, dev, bp, pad) | |
1221 | struct device *self; | |
1222 | int targ; | |
1223 | scintr_fn intr; | |
1224 | struct device *dev; | |
1225 | register struct buf *bp; | |
1226 | int pad; | |
1227 | { | |
1228 | register struct esp_softc *sc = (struct esp_softc *)self; | |
1229 | register int len = bp->b_bcount; | |
1230 | register u_long addr; | |
1231 | ||
1232 | if ((unsigned)len > MAX_TRANSFER_SIZE) { | |
1233 | printf("%s: %s\n", sc->sc_hba.hba_dev.dv_xname, | |
1234 | len < 0 ? "negative length" : "transfer too big"); | |
1235 | return (1); | |
1236 | } | |
1237 | ||
1238 | if (sc->sc_needclear & (1 << targ)) | |
1239 | espclear(sc, targ); | |
1240 | ||
1241 | /* | |
1242 | * Set dma registers later, on data transfer, | |
1243 | * but compute the contents now. | |
1244 | * COULD JUST REMEMBER bp HERE...? | |
1245 | * | |
1246 | * The DMA chip cannot cross a 16 MB address boundary. | |
1247 | * We should do this as multiple DMA transactions on a | |
1248 | * single SCSI command, but I have not written that yet. | |
1249 | */ | |
1250 | sc->sc_dmactl = bp->b_flags & B_READ ? DMA_ENA | DMA_READ | DMA_IE : | |
1251 | DMA_ENA | DMA_IE; | |
1252 | addr = (u_long)bp->b_un.b_addr; | |
1253 | /* dma chip cannot cross 16MB boundary XXX */ | |
1254 | if (CROSS_DMA(addr, len)) | |
1255 | panic("dma crosses 16MB boundary: fix esp.c"); | |
1256 | sc->sc_dmaaddr = addr; | |
1257 | sc->sc_resid = len; | |
1258 | ||
1259 | /* | |
1260 | * Enable interrupts and start selection. | |
1261 | * The rest is done in our interrupt handler. | |
1262 | */ | |
1263 | sc->sc_hba.hba_intr = intr; /* remember dev done function */ | |
1264 | sc->sc_hba.hba_intrdev = dev; /* and its first arg */ | |
1265 | sc->sc_dma->dma_csr = DMA_IE; | |
1266 | espselect(sc, sc->sc_esp, targ, &sc->sc_cdb); | |
1267 | return (0); | |
1268 | } | |
1269 | ||
1270 | /* | |
1271 | * Handle interrupt. Return 1 if taken. | |
1272 | */ | |
1273 | int | |
1274 | espintr(sc0) | |
1275 | void *sc0; | |
1276 | { | |
1277 | register struct esp_softc *sc = (struct esp_softc *)sc0; | |
1278 | register volatile struct espreg *esp = sc->sc_esp; | |
1279 | register volatile struct dmareg *dma = sc->sc_dma; | |
1280 | register int r, wait; | |
1281 | register struct sq *sq; | |
1282 | ||
1283 | r = dma->dma_csr; | |
1284 | if (!DMA_INTR(r)) | |
1285 | return (0); /* not ours */ | |
1286 | sc->sc_interrupts++; | |
1287 | ||
1288 | again: | |
1289 | sc->sc_espstat = esp->esp_stat; | |
1290 | sc->sc_espstep = esp->esp_step & ESPSTEP_MASK; | |
1291 | sc->sc_espintr = esp->esp_intr; | |
1292 | sc->sc_dmacsr = r; | |
1293 | ||
1294 | if (sc->sc_state == S_IDLE) { | |
1295 | printf("%s: stray interrupt\n", sc->sc_hba.hba_dev.dv_xname); | |
1296 | dma->dma_csr &= ~DMA_IE; /* ??? */ | |
1297 | return (1); | |
1298 | } | |
1299 | switch (r = espact(sc, esp, dma, &sc->sc_cdb)) { | |
1300 | ||
1301 | case ACT_CONT: /* just return */ | |
1302 | break; | |
1303 | ||
1304 | case ACT_READ: | |
1305 | case ACT_WRITE: | |
1306 | /* | |
1307 | * We have to do this ourselves since another | |
1308 | * user of espact() wants to do programmed I/O. | |
1309 | * If we already did dma, and are done, stop. | |
1310 | */ | |
1311 | if (sc->sc_resid == 0) { | |
1312 | printf("%s: target %d sent too much data\n", | |
1313 | sc->sc_hba.hba_dev.dv_xname, sc->sc_targ); | |
1314 | goto reset; | |
1315 | } | |
1316 | sc->sc_dmaactive = 1; | |
1317 | dma->dma_addr = sc->sc_dmaaddr; | |
1318 | esp->esp_tch = sc->sc_resid >> 8; | |
1319 | esp->esp_tcl = sc->sc_resid; | |
1320 | /* load count into counter via DMA NOP */ | |
1321 | esp->esp_cmd = ESPCMD_DMA | ESPCMD_NOP; | |
1322 | /* enable dma */ | |
1323 | dma->dma_csr = sc->sc_dmactl; | |
1324 | /* and go */ | |
1325 | esp->esp_cmd = ESPCMD_DMA | ESPCMD_XFER_INFO; | |
1326 | break; | |
1327 | ||
1328 | case ACT_RESET: /* please reset esp */ | |
1329 | reset: | |
1330 | espreset(sc); /* ??? */ | |
1331 | /* FALLTHROUGH */ | |
1332 | ||
1333 | case ACT_DONE: /* this one is done, successfully */ | |
1334 | case ACT_ERROR: /* this one is done due to `severe' error */ | |
1335 | sc->sc_state = S_IDLE; | |
1336 | if (!sc->sc_hba.hba_busy) | |
1337 | panic("espintr sq"); | |
1338 | /* | |
1339 | * This transaction is done. | |
1340 | * Call the driver's intr routine, | |
1341 | * then start the next guy if any. | |
1342 | */ | |
1343 | (*sc->sc_hba.hba_intr)(sc->sc_hba.hba_intrdev, | |
1344 | r == ACT_DONE ? sc->sc_stat[0] : -1, sc->sc_resid); | |
1345 | if ((sq = sc->sc_hba.hba_head) != NULL) { | |
1346 | sc->sc_hba.hba_head = sq->sq_forw; | |
1347 | (*sq->sq_dgo)(sq->sq_dev, &sc->sc_cdb); | |
1348 | } else | |
1349 | sc->sc_hba.hba_busy = 0; | |
1350 | break; | |
1351 | ||
1352 | case ACT_QUICKINTR: /* wait a short while for another interrupt */ | |
1353 | printf("%s: quickintr: ", sc->sc_hba.hba_dev.dv_xname); | |
1354 | wait = 100; | |
1355 | do { | |
1356 | r = dma->dma_csr; | |
1357 | if (DMA_INTR(r)) { | |
1358 | printf("got one, wait=%d\n", wait); | |
1359 | goto again; | |
1360 | } | |
1361 | } while (--wait > 0); | |
1362 | printf("did not get one\n"); | |
1363 | break; | |
1364 | ||
1365 | default: | |
1366 | panic("espintr action"); | |
1367 | } | |
1368 | return (1); | |
1369 | } | |
1370 | ||
1371 | /* | |
1372 | * Target or unit decided to let go of the bus early. | |
1373 | */ | |
1374 | void | |
1375 | esprel(self) | |
1376 | struct device *self; | |
1377 | { | |
1378 | register struct esp_softc *sc = (struct esp_softc *)self; | |
1379 | register struct sq *sq; | |
1380 | ||
1381 | /* if there is someone else waiting, give them a crack at it */ | |
1382 | if ((sq = sc->sc_hba.hba_head) != NULL) | |
1383 | (*sq->sq_dgo)(sq->sq_dev, &sc->sc_cdb); | |
1384 | else | |
1385 | sc->sc_hba.hba_busy = 0; | |
1386 | } |