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1 | /* |
2 | * Copyright (c) 1988 University of Utah. | |
3 | * Copyright (c) 1982, 1990 The Regents of the University of California. | |
4 | * All rights reserved. | |
5 | * | |
6 | * This code is derived from software contributed to Berkeley by | |
7 | * the Systems Programming Group of the University of Utah Computer | |
8 | * Science Department. | |
9 | * | |
10 | * %sccs.include.redist.c% | |
11 | * | |
9e153d67 | 12 | * from: Utah $Hdr: cpu.h 1.16 91/03/25$ |
88a7e859 | 13 | * |
b6bda484 | 14 | * @(#)cpu.h 7.9 (Berkeley) %G% |
ba327c15 MK |
15 | */ |
16 | ||
ba327c15 MK |
17 | /* |
18 | * Exported definitions unique to hp300/68k cpu support. | |
19 | */ | |
20 | ||
21 | /* | |
22 | * definitions of cpu-dependent requirements | |
23 | * referenced in generic code | |
24 | */ | |
25 | #define COPY_SIGCODE /* copy sigcode above user stack in exec */ | |
26 | ||
27 | /* | |
28 | * function vs. inline configuration; | |
29 | * these are defined to get generic functions | |
30 | * rather than inline or machine-dependent implementations | |
31 | */ | |
32 | #define NEED_MINMAX /* need {,i,l,ul}{min,max} functions */ | |
33 | #undef NEED_FFS /* don't need ffs function */ | |
34 | #undef NEED_BCMP /* don't need bcmp function */ | |
35 | #undef NEED_STRLEN /* don't need strlen function */ | |
36 | ||
37 | #define cpu_exec(p) /* nothing */ | |
54ba99e8 | 38 | #define cpu_wait(p) /* nothing */ |
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39 | #define cpu_setstack(p, ap) \ |
40 | (p)->p_md.md_regs[SP] = ap | |
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41 | |
42 | /* | |
43 | * Arguments to hardclock, softclock and gatherstats | |
44 | * encapsulate the previous machine state in an opaque | |
45 | * clockframe; for hp300, use just what the hardware | |
46 | * leaves on the stack. | |
47 | */ | |
48 | typedef struct intrframe { | |
b6bda484 | 49 | char *pc; |
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50 | int ps; |
51 | } clockframe; | |
52 | ||
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53 | #define CLKF_USERMODE(framep) (((framep)->ps & PSL_S) == 0) |
54 | #define CLKF_BASEPRI(framep) (((framep)->ps & PSL_IPL7) == 0) | |
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55 | #define CLKF_PC(framep) ((framep)->pc) |
56 | ||
57 | ||
58 | /* | |
59 | * Preempt the current process if in interrupt from user mode, | |
60 | * or after the current trap/syscall if in system mode. | |
61 | */ | |
62 | #define need_resched() { want_resched++; aston(); } | |
63 | ||
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64 | /* |
65 | * Give a profiling tick to the current process from the softclock | |
66 | * interrupt. On hp300, request an ast to send us through trap(), | |
67 | * marking the proc as needing a profiling tick. | |
68 | */ | |
69 | #define profile_tick(p, framep) { (p)->p_flag |= SOWEUPC; aston(); } | |
70 | ||
600bf028 MK |
71 | /* |
72 | * Notify the current process (p) that it has a signal pending, | |
73 | * process as soon as possible. | |
74 | */ | |
75 | #define signotify(p) aston() | |
76 | ||
77 | #define aston() (astpending++) | |
78 | ||
79 | int astpending; /* need to trap before returning to user mode */ | |
ba327c15 MK |
80 | int want_resched; /* resched() was called */ |
81 | ||
82 | ||
83 | /* | |
84 | * simulated software interrupt register | |
85 | */ | |
86 | extern unsigned char ssir; | |
87 | ||
88 | #define SIR_NET 0x1 | |
89 | #define SIR_CLOCK 0x2 | |
90 | ||
91 | #define siroff(x) ssir &= ~(x) | |
92 | #define setsoftnet() ssir |= SIR_NET | |
93 | #define setsoftclock() ssir |= SIR_CLOCK | |
94 | ||
95 | ||
96 | ||
97 | /* | |
98 | * The rest of this should probably be moved to ../hp300/hp300cpu.h, | |
99 | * although some of it could probably be put into generic 68k headers. | |
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100 | */ |
101 | ||
102 | /* values for machineid */ | |
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103 | #define HP_320 0 /* 16Mhz 68020+HP MMU+16K external cache */ |
104 | #define HP_330 1 /* 16Mhz 68020+68851 MMU */ | |
105 | #define HP_350 2 /* 25Mhz 68020+HP MMU+32K external cache */ | |
106 | #define HP_360 3 /* 25Mhz 68030 */ | |
107 | #define HP_370 4 /* 33Mhz 68030+64K external cache */ | |
108 | #define HP_340 5 /* 16Mhz 68030 */ | |
109 | #define HP_375 6 /* 50Mhz 68030+32K external cache */ | |
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110 | |
111 | /* values for mmutype (assigned for quick testing) */ | |
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112 | #define MMU_68030 -1 /* 68030 on-chip subset of 68851 */ |
113 | #define MMU_HP 0 /* HP proprietary */ | |
114 | #define MMU_68851 1 /* Motorola 68851 */ | |
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115 | |
116 | /* values for ectype */ | |
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117 | #define EC_PHYS -1 /* external physical address cache */ |
118 | #define EC_NONE 0 /* no external cache */ | |
119 | #define EC_VIRT 1 /* external virtual address cache */ | |
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120 | |
121 | /* values for cpuspeed (not really related to clock speed due to caches) */ | |
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122 | #define MHZ_8 1 |
123 | #define MHZ_16 2 | |
124 | #define MHZ_25 3 | |
125 | #define MHZ_33 4 | |
126 | #define MHZ_50 6 | |
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127 | |
128 | #ifdef KERNEL | |
129 | extern int machineid, mmutype, ectype; | |
9e153d67 | 130 | extern char *intiobase, *intiolimit; |
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131 | |
132 | /* what is this supposed to do? i.e. how is it different than startrtclock? */ | |
133 | #define enablertclock() | |
134 | ||
135 | #endif | |
136 | ||
137 | /* physical memory sections */ | |
4534a638 | 138 | #define ROMBASE (0x00000000) |
9e153d67 MH |
139 | #define INTIOBASE (0x00400000) |
140 | #define INTIOTOP (0x00600000) | |
141 | #define EXTIOBASE (0x00600000) | |
142 | #define EXTIOTOP (0x20000000) | |
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143 | #define MAXADDR (0xFFFFF000) |
144 | ||
9e153d67 MH |
145 | /* |
146 | * Internal IO space: | |
147 | * | |
148 | * Ranges from 0x400000 to 0x600000 (IIOMAPSIZE). | |
149 | * | |
150 | * Internal IO space is mapped in the kernel from ``intiobase'' to | |
151 | * ``intiolimit'' (defined in locore.s). Since it is always mapped, | |
152 | * conversion between physical and kernel virtual addresses is easy. | |
153 | */ | |
154 | #define ISIIOVA(va) \ | |
155 | ((char *)(va) >= intiobase && (char *)(va) < intiolimit) | |
156 | #define IIOV(pa) ((int)(pa)-INTIOBASE+(int)intiobase) | |
157 | #define IIOP(va) ((int)(va)-(int)intiobase+INTIOBASE) | |
158 | #define IIOPOFF(pa) ((int)(pa)-INTIOBASE) | |
159 | #define IIOMAPSIZE btoc(INTIOTOP-INTIOBASE) /* 2mb */ | |
88a7e859 | 160 | |
9e153d67 MH |
161 | /* |
162 | * External IO space: | |
163 | * | |
164 | * DIO ranges from select codes 0-63 at physical addresses given by: | |
165 | * 0x600000 + (sc - 32) * 0x10000 | |
166 | * DIO cards are addressed in the range 0-31 [0x600000-0x800000) for | |
167 | * their control space and the remaining areas, [0x200000-0x400000) and | |
168 | * [0x800000-0x1000000), are for additional space required by a card; | |
169 | * e.g. a display framebuffer. | |
170 | * | |
171 | * DIO-II ranges from select codes 132-255 at physical addresses given by: | |
172 | * 0x1000000 + (sc - 132) * 0x400000 | |
173 | * The address range of DIO-II space is thus [0x1000000-0x20000000). | |
174 | * | |
175 | * DIO/DIO-II space is too large to map in its entirety, instead devices | |
176 | * are mapped into kernel virtual address space allocated from a range | |
177 | * of EIOMAPSIZE pages (vmparam.h) starting at ``extiobase''. | |
178 | */ | |
179 | #define DIOBASE (0x600000) | |
180 | #define DIOTOP (0x1000000) | |
181 | #define DIOCSIZE (0x10000) | |
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182 | #define DIOIIBASE (0x01000000) |
183 | #define DIOIITOP (0x20000000) | |
184 | #define DIOIICSIZE (0x00400000) | |
185 | ||
9e153d67 MH |
186 | /* |
187 | * HP MMU | |
188 | */ | |
189 | #define MMUBASE IIOPOFF(0x5F4000) | |
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190 | #define MMUSSTP 0x0 |
191 | #define MMUUSTP 0x4 | |
192 | #define MMUTBINVAL 0x8 | |
193 | #define MMUSTAT 0xC | |
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194 | #define MMUCMD MMUSTAT |
195 | ||
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196 | #define MMU_UMEN 0x0001 /* enable user mapping */ |
197 | #define MMU_SMEN 0x0002 /* enable supervisor mapping */ | |
198 | #define MMU_CEN 0x0004 /* enable data cache */ | |
199 | #define MMU_BERR 0x0008 /* bus error */ | |
200 | #define MMU_IEN 0x0020 /* enable instruction cache */ | |
201 | #define MMU_FPE 0x0040 /* enable 68881 FP coprocessor */ | |
202 | #define MMU_WPF 0x2000 /* write protect fault */ | |
203 | #define MMU_PF 0x4000 /* page fault */ | |
204 | #define MMU_PTF 0x8000 /* page table fault */ | |
205 | ||
206 | #define MMU_FAULT (MMU_PTF|MMU_PF|MMU_WPF|MMU_BERR) | |
207 | #define MMU_ENAB (MMU_UMEN|MMU_SMEN|MMU_IEN|MMU_FPE) | |
208 | ||
9e153d67 MH |
209 | /* |
210 | * 68851 and 68030 MMU | |
211 | */ | |
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212 | #define PMMU_LVLMASK 0x0007 |
213 | #define PMMU_INV 0x0400 | |
214 | #define PMMU_WP 0x0800 | |
215 | #define PMMU_ALV 0x1000 | |
216 | #define PMMU_SO 0x2000 | |
217 | #define PMMU_LV 0x4000 | |
218 | #define PMMU_BE 0x8000 | |
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219 | #define PMMU_FAULT (PMMU_WP|PMMU_INV) |
220 | ||
221 | /* 680X0 function codes */ | |
222 | #define FC_USERD 1 /* user data space */ | |
223 | #define FC_USERP 2 /* user program space */ | |
224 | #define FC_PURGE 3 /* HPMMU: clear TLB entries */ | |
225 | #define FC_SUPERD 5 /* supervisor data space */ | |
226 | #define FC_SUPERP 6 /* supervisor program space */ | |
227 | #define FC_CPU 7 /* CPU space */ | |
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228 | |
229 | /* fields in the 68020 cache control register */ | |
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230 | #define IC_ENABLE 0x0001 /* enable instruction cache */ |
231 | #define IC_FREEZE 0x0002 /* freeze instruction cache */ | |
232 | #define IC_CE 0x0004 /* clear instruction cache entry */ | |
233 | #define IC_CLR 0x0008 /* clear entire instruction cache */ | |
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234 | |
235 | /* additional fields in the 68030 cache control register */ | |
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236 | #define IC_BE 0x0010 /* instruction burst enable */ |
237 | #define DC_ENABLE 0x0100 /* data cache enable */ | |
238 | #define DC_FREEZE 0x0200 /* data cache freeze */ | |
239 | #define DC_CE 0x0400 /* clear data cache entry */ | |
240 | #define DC_CLR 0x0800 /* clear entire data cache */ | |
241 | #define DC_BE 0x1000 /* data burst enable */ | |
242 | #define DC_WA 0x2000 /* write allocate */ | |
243 | ||
244 | #define CACHE_ON (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) | |
245 | #define CACHE_OFF (DC_CLR|IC_CLR) | |
246 | #define CACHE_CLR (CACHE_ON) | |
247 | #define IC_CLEAR (DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) | |
248 | #define DC_CLEAR (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE) |