projects / unix-history / blame
| Commit | Line | Data |
|---|---|---|
| 430f81c3 | 1 | /* |
| d2e049c0 KB |
2 | * Copyright (c) 1986 The Regents of the University of California. |
| 3 | * All rights reserved. | |
| 4 | * | |
| b702c21d | 5 | * %sccs.include.redist.c% |
| d2e049c0 | 6 | * |
| b702c21d | 7 | * @(#)ikreg.h 7.3 (Berkeley) %G% |
| 430f81c3 | 8 | */ |
| 1287b07c SL |
9 | |
| 10 | /* | |
| 11 | * IKON DR-11W register definitions. | |
| 12 | */ | |
| 70351527 SL |
13 | struct ikdevice { |
| 14 | u_short ik_csr; /* control status register */ | |
| 15 | u_short ik_data; /* data in/out register */ | |
| 16 | u_char ik_mod; /* address modifier */ | |
| 17 | u_char ik_vec; /* interrupt vector */ | |
| 18 | u_short ik_pulse; /* pulse commands (w) */ | |
| 19 | u_short ik_fill[5]; | |
| 20 | u_short ik_balo; /* low word of dma beginning address (w) */ | |
| 21 | u_short ik_wc; /* dma word count */ | |
| 22 | u_short ik_calo; /* low word of dma current address (r) */ | |
| 23 | u_short ik_fill1; | |
| 24 | u_short ik_bahi; /* high word of dma beginning address (w) */ | |
| 25 | u_short ik_fill2; | |
| 26 | u_short ik_cahi; /* high word of dma current address (r) */ | |
| 1287b07c SL |
27 | }; |
| 28 | ||
| 29 | /* | |
| 30 | * CSR control definitions (write-only). | |
| 31 | */ | |
| 70351527 SL |
32 | #define IKCSR_GO 0x0001 /* start dma */ |
| 33 | #define IKCSR_FNC1 0x0002 /* function bit 1 */ | |
| 34 | #define IKCSR_FNC2 0x0004 /* function bit 2 */ | |
| 35 | #define IKCSR_FNC3 0x0008 /* function bit 3 */ | |
| 1287b07c | 36 | /* bits 4-5 are unused */ |
| 70351527 | 37 | #define IKCSR_IENA 0x0040 /* enable/disable interrupts */ |
| 1287b07c | 38 | /* bit 7 is unused */ |
| 70351527 | 39 | #define IKCSR_CYCLE 0x0100 /* force dma to cycle */ |
| 1287b07c | 40 | /* bits 9-11 are unused */ |
| 70351527 SL |
41 | #define IKCSR_MCLR 0x1000 /* master clear board */ |
| 42 | #define IKCSR_RPERR 0x2000 /* reset parity error */ | |
| 43 | #define IKCSR_RATTF 0x4000 /* reset attention */ | |
| 44 | #define IKCSR_RDMAF 0x8000 /* reset dma completion */ | |
| 1287b07c SL |
45 | |
| 46 | /* | |
| 47 | * CSR status definitions (read-only). | |
| 48 | */ | |
| 70351527 | 49 | #define IKCSR_DEV 0x0001 /* device flag (0 = 10083, 1 = 10077) */ |
| 1287b07c | 50 | /* bits 1-3 reflect the function latch state */ |
| 70351527 SL |
51 | #define IKCSR_TIMO 0x0010 /* bus timeout during dma */ |
| 52 | #define IKCSR_BERR 0x0020 /* bus error during dma */ | |
| 1287b07c | 53 | /* bit 6 reflects interrupt enable state */ |
| 70351527 | 54 | #define IKCSR_READY 0x0080 /* device ready for next command */ |
| 1287b07c | 55 | /* bit 8 should be 0 */ |
| 70351527 SL |
56 | #define IKCSR_STATC 0x0200 /* status bit C */ |
| 57 | #define IKCSR_STATB 0x0400 /* status bit B */ | |
| 58 | #define IKCSR_STATA 0x0800 /* status bit A */ | |
| 59 | #define IKCSR_PERR 0x1000 /* parity error during pi/o or dma */ | |
| 60 | #define IKCSR_ATTN 0x2000 /* current state of attention bit */ | |
| 61 | #define IKCSR_ATTF 0x4000 /* latched attention t-f transition */ | |
| 62 | #define IKCSR_DMAF 0x8000 /* dma completed or terminated */ | |
| 1287b07c SL |
63 | |
| 64 | #define IKCSR_BITS \ | |
| 65 | "\020\1DEV\2FNC1\3FNC2\4FNC3\5TIMO\6BERR\7IENA\10READY\12STATC\13STATB\14STATA\ | |
| 66 | \15PERR\16ATTN\17ATTF\20DMAF" | |
| 67 | ||
| 1287b07c SL |
68 | /* |
| 69 | * Pulse command register definitions (write-only). | |
| 70 | */ | |
| 70351527 SL |
71 | #define IKPULSE_GO 0x0001 /* enable dma */ |
| 72 | #define IKPULSE_FNC2 0x0004 /* pulse function bit 1 */ | |
| 73 | #define IKPULSE_RIENA 0x0020 /* reset IKCSR_IENA */ | |
| 74 | #define IKPULSE_SIENA 0x0040 /* set IKCSR_IENA */ | |
| 75 | #define IKPULSE_CYCL 0x0100 /* force dma to cycle */ | |
| 76 | #define IKPULSE_MCLR 0x1000 /* initialize interface */ | |
| 77 | #define IKPULSE_RPERR 0x2000 /* reset IKCSR_PERR */ | |
| 78 | #define IKPULSE_RATTF 0x4000 /* reset IKCSR_ATTF */ | |
| 79 | #define IKPULSE_RDMAF 0x8000 /* reset IKCSR_DMAF */ |